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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#define DRM_DISPLAY_INFO_LEN 32
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define DRM_CONNECTOR_NAME_LEN 32
27#define DRM_DISPLAY_MODE_LEN 32
28#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -080029#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -080030#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
32#define DRM_MODE_TYPE_PREFERRED (1 << 3)
33#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -080034#define DRM_MODE_TYPE_USERDEF (1 << 5)
35#define DRM_MODE_TYPE_DRIVER (1 << 6)
Christopher Ferris76a1d452018-06-27 14:12:29 -070036#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)
Tao Baod7db5942015-01-28 10:07:51 -080037#define DRM_MODE_FLAG_PHSYNC (1 << 0)
38#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -080039#define DRM_MODE_FLAG_PVSYNC (1 << 2)
40#define DRM_MODE_FLAG_NVSYNC (1 << 3)
41#define DRM_MODE_FLAG_INTERLACE (1 << 4)
42#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -080043#define DRM_MODE_FLAG_CSYNC (1 << 6)
44#define DRM_MODE_FLAG_PCSYNC (1 << 7)
45#define DRM_MODE_FLAG_NCSYNC (1 << 8)
46#define DRM_MODE_FLAG_HSKEW (1 << 9)
Tao Baod7db5942015-01-28 10:07:51 -080047#define DRM_MODE_FLAG_BCAST (1 << 10)
48#define DRM_MODE_FLAG_PIXMUX (1 << 11)
49#define DRM_MODE_FLAG_DBLCLK (1 << 12)
50#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Tao Baod7db5942015-01-28 10:07:51 -080051#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
52#define DRM_MODE_FLAG_3D_NONE (0 << 14)
53#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
54#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080055#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
56#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
57#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
58#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080059#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
60#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Christopher Ferris82d75042015-01-26 10:57:07 -080061#define DRM_MODE_PICTURE_ASPECT_NONE 0
62#define DRM_MODE_PICTURE_ASPECT_4_3 1
Christopher Ferris82d75042015-01-26 10:57:07 -080063#define DRM_MODE_PICTURE_ASPECT_16_9 2
Christopher Ferris9ce28842018-10-25 12:11:39 -070064#define DRM_MODE_PICTURE_ASPECT_64_27 3
65#define DRM_MODE_PICTURE_ASPECT_256_135 4
66#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
67#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
68#define DRM_MODE_CONTENT_TYPE_PHOTO 2
69#define DRM_MODE_CONTENT_TYPE_CINEMA 3
70#define DRM_MODE_CONTENT_TYPE_GAME 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -080071#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080072#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
73#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
74#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
Christopher Ferris9ce28842018-10-25 12:11:39 -070075#define DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27 << 19)
76#define DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135 << 19)
Christopher Ferris76a1d452018-06-27 14:12:29 -070077#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080078#define DRM_MODE_DPMS_ON 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080079#define DRM_MODE_DPMS_STANDBY 1
80#define DRM_MODE_DPMS_SUSPEND 2
81#define DRM_MODE_DPMS_OFF 3
82#define DRM_MODE_SCALE_NONE 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080083#define DRM_MODE_SCALE_FULLSCREEN 1
84#define DRM_MODE_SCALE_CENTER 2
85#define DRM_MODE_SCALE_ASPECT 3
Ben Cheng655a7c02013-10-16 16:09:24 -070086#define DRM_MODE_DITHERING_OFF 0
87#define DRM_MODE_DITHERING_ON 1
88#define DRM_MODE_DITHERING_AUTO 2
89#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -070090#define DRM_MODE_DIRTY_ON 1
91#define DRM_MODE_DIRTY_ANNOTATE 2
Christopher Ferris525ce912017-07-26 13:12:53 -070092#define DRM_MODE_LINK_STATUS_GOOD 0
93#define DRM_MODE_LINK_STATUS_BAD 1
Christopher Ferris1308ad32017-11-14 17:32:13 -080094#define DRM_MODE_ROTATE_0 (1 << 0)
95#define DRM_MODE_ROTATE_90 (1 << 1)
96#define DRM_MODE_ROTATE_180 (1 << 2)
97#define DRM_MODE_ROTATE_270 (1 << 3)
98#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
99#define DRM_MODE_REFLECT_X (1 << 4)
100#define DRM_MODE_REFLECT_Y (1 << 5)
101#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
Christopher Ferris76a1d452018-06-27 14:12:29 -0700102#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
103#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
104#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700105struct drm_mode_modeinfo {
Tao Baod7db5942015-01-28 10:07:51 -0800106 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800107 __u16 hdisplay;
108 __u16 hsync_start;
109 __u16 hsync_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 __u16 htotal;
111 __u16 hskew;
112 __u16 vdisplay;
113 __u16 vsync_start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114 __u16 vsync_end;
115 __u16 vtotal;
116 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800117 __u32 vrefresh;
Tao Baod7db5942015-01-28 10:07:51 -0800118 __u32 flags;
119 __u32 type;
120 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700121};
122struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800123 __u64 fb_id_ptr;
124 __u64 crtc_id_ptr;
125 __u64 connector_id_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800126 __u64 encoder_id_ptr;
127 __u32 count_fbs;
128 __u32 count_crtcs;
129 __u32 count_connectors;
Tao Baod7db5942015-01-28 10:07:51 -0800130 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131 __u32 min_width;
132 __u32 max_width;
133 __u32 min_height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134 __u32 max_height;
135};
Ben Cheng655a7c02013-10-16 16:09:24 -0700136struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800137 __u64 set_connectors_ptr;
138 __u32 count_connectors;
139 __u32 crtc_id;
Tao Baod7db5942015-01-28 10:07:51 -0800140 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800143 __u32 gamma_size;
144 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800145 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700146};
Tao Baod7db5942015-01-28 10:07:51 -0800147#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
148#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700149struct drm_mode_set_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800150 __u32 plane_id;
151 __u32 crtc_id;
152 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800153 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154 __s32 crtc_x;
155 __s32 crtc_y;
156 __u32 crtc_w;
157 __u32 crtc_h;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800158 __u32 src_x;
159 __u32 src_y;
160 __u32 src_h;
161 __u32 src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700162};
163struct drm_mode_get_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800164 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800165 __u32 crtc_id;
166 __u32 fb_id;
167 __u32 possible_crtcs;
168 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800169 __u32 count_format_types;
170 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700171};
172struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800173 __u64 plane_id_ptr;
174 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700175};
176#define DRM_MODE_ENCODER_NONE 0
177#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700178#define DRM_MODE_ENCODER_TMDS 2
179#define DRM_MODE_ENCODER_LVDS 3
180#define DRM_MODE_ENCODER_TVDAC 4
181#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700182#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700183#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700184#define DRM_MODE_ENCODER_DPI 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700185struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800186 __u32 encoder_id;
187 __u32 encoder_type;
188 __u32 crtc_id;
189 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800190 __u32 possible_clones;
Ben Cheng655a7c02013-10-16 16:09:24 -0700191};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800192enum drm_mode_subconnector {
193 DRM_MODE_SUBCONNECTOR_Automatic = 0,
194 DRM_MODE_SUBCONNECTOR_Unknown = 0,
195 DRM_MODE_SUBCONNECTOR_DVID = 3,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800196 DRM_MODE_SUBCONNECTOR_DVIA = 4,
197 DRM_MODE_SUBCONNECTOR_Composite = 5,
198 DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
199 DRM_MODE_SUBCONNECTOR_Component = 8,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800200 DRM_MODE_SUBCONNECTOR_SCART = 9,
201};
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700203#define DRM_MODE_CONNECTOR_VGA 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700204#define DRM_MODE_CONNECTOR_DVII 2
205#define DRM_MODE_CONNECTOR_DVID 3
206#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700207#define DRM_MODE_CONNECTOR_Composite 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700208#define DRM_MODE_CONNECTOR_SVIDEO 6
209#define DRM_MODE_CONNECTOR_LVDS 7
210#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700211#define DRM_MODE_CONNECTOR_9PinDIN 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700212#define DRM_MODE_CONNECTOR_DisplayPort 10
213#define DRM_MODE_CONNECTOR_HDMIA 11
214#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700215#define DRM_MODE_CONNECTOR_TV 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700216#define DRM_MODE_CONNECTOR_eDP 14
217#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700218#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700219#define DRM_MODE_CONNECTOR_DPI 17
Christopher Ferris9ce28842018-10-25 12:11:39 -0700220#define DRM_MODE_CONNECTOR_WRITEBACK 18
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700221struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800222 __u64 encoders_ptr;
223 __u64 modes_ptr;
224 __u64 props_ptr;
225 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800226 __u32 count_modes;
227 __u32 count_props;
228 __u32 count_encoders;
229 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800230 __u32 connector_id;
231 __u32 connector_type;
232 __u32 connector_type_id;
233 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800234 __u32 mm_width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800235 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800236 __u32 subpixel;
237 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700238};
Tao Baod7db5942015-01-28 10:07:51 -0800239#define DRM_MODE_PROP_PENDING (1 << 0)
240#define DRM_MODE_PROP_RANGE (1 << 1)
241#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
242#define DRM_MODE_PROP_ENUM (1 << 3)
Tao Baod7db5942015-01-28 10:07:51 -0800243#define DRM_MODE_PROP_BLOB (1 << 4)
244#define DRM_MODE_PROP_BITMASK (1 << 5)
245#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700246#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
247#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
248#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
249#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800250#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800251struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800252 __u64 value;
253 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700254};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800255struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800256 __u64 values_ptr;
257 __u64 enum_blob_ptr;
258 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800259 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800260 char name[DRM_PROP_NAME_LEN];
261 __u32 count_values;
262 __u32 count_enum_blobs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800263};
Ben Cheng655a7c02013-10-16 16:09:24 -0700264struct drm_mode_connector_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800265 __u64 value;
266 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800267 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700268};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700269#define DRM_MODE_OBJECT_CRTC 0xcccccccc
270#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700271#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
272#define DRM_MODE_OBJECT_MODE 0xdededede
273#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
274#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
Christopher Ferris106b3a82016-08-24 12:15:38 -0700275#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
276#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
277#define DRM_MODE_OBJECT_ANY 0
278struct drm_mode_obj_get_properties {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700279 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800280 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800281 __u32 count_props;
282 __u32 obj_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700283 __u32 obj_type;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800284};
Ben Cheng655a7c02013-10-16 16:09:24 -0700285struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800286 __u64 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700287 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800288 __u32 obj_id;
Tao Baod7db5942015-01-28 10:07:51 -0800289 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700290};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700291struct drm_mode_get_blob {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800292 __u32 blob_id;
Tao Baod7db5942015-01-28 10:07:51 -0800293 __u32 length;
294 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700295};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800296struct drm_mode_fb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800297 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800298 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700299 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800300 __u32 pitch;
301 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800302 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700303 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700304};
Tao Baod7db5942015-01-28 10:07:51 -0800305#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800306#define DRM_MODE_FB_MODIFIERS (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700307struct drm_mode_fb_cmd2 {
Tao Baod7db5942015-01-28 10:07:51 -0800308 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800309 __u32 width;
310 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700311 __u32 pixel_format;
Tao Baod7db5942015-01-28 10:07:51 -0800312 __u32 flags;
313 __u32 handles[4];
314 __u32 pitches[4];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700315 __u32 offsets[4];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800316 __u64 modifier[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700317};
Christopher Ferris38062f92014-07-09 15:33:25 -0700318#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700319#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800320#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700321#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700322struct drm_mode_fb_dirty_cmd {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700323 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800324 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800325 __u32 color;
326 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700327 __u64 clips_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800328};
Ben Cheng655a7c02013-10-16 16:09:24 -0700329struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800330 __u32 connector_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700331 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800332};
Ben Cheng655a7c02013-10-16 16:09:24 -0700333#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700334#define DRM_MODE_CURSOR_MOVE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700335#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800336struct drm_mode_cursor {
Tao Baod7db5942015-01-28 10:07:51 -0800337 __u32 flags;
338 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700339 __s32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800340 __s32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800341 __u32 width;
342 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700343 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800344};
Christopher Ferris38062f92014-07-09 15:33:25 -0700345struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800346 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700347 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800348 __s32 x;
Tao Baod7db5942015-01-28 10:07:51 -0800349 __s32 y;
350 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700351 __u32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800352 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800353 __s32 hot_x;
354 __s32 hot_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700355};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800356struct drm_mode_crtc_lut {
Tao Baod7db5942015-01-28 10:07:51 -0800357 __u32 crtc_id;
358 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700359 __u64 red;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800360 __u64 green;
Tao Baod7db5942015-01-28 10:07:51 -0800361 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800362};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700363struct drm_color_ctm {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700364 __u64 matrix[9];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700365};
366struct drm_color_lut {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700367 __u16 red;
368 __u16 green;
369 __u16 blue;
370 __u16 reserved;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700371};
372#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800373#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800374#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800375#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
376#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
377#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
Christopher Ferris38062f92014-07-09 15:33:25 -0700378struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800379 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800380 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800381 __u32 flags;
382 __u32 reserved;
383 __u64 user_data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800384};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800385struct drm_mode_crtc_page_flip_target {
386 __u32 crtc_id;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800387 __u32 fb_id;
388 __u32 flags;
389 __u32 sequence;
390 __u64 user_data;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800391};
Ben Cheng655a7c02013-10-16 16:09:24 -0700392struct drm_mode_create_dumb {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700393 __u32 height;
394 __u32 width;
395 __u32 bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800396 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700397 __u32 handle;
398 __u32 pitch;
399 __u64 size;
400};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700401struct drm_mode_map_dumb {
402 __u32 handle;
403 __u32 pad;
404 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700405};
406struct drm_mode_destroy_dumb {
407 __u32 handle;
408};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700409#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
410#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
411#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
412#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700413struct drm_mode_atomic {
414 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800415 __u32 count_objs;
416 __u64 objs_ptr;
417 __u64 count_props_ptr;
418 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800419 __u64 prop_values_ptr;
420 __u64 reserved;
421 __u64 user_data;
422};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800423struct drm_format_modifier_blob {
424#define FORMAT_BLOB_CURRENT 1
425 __u32 version;
426 __u32 flags;
427 __u32 count_formats;
428 __u32 formats_offset;
429 __u32 count_modifiers;
430 __u32 modifiers_offset;
431};
432struct drm_format_modifier {
433 __u64 formats;
434 __u32 offset;
435 __u32 pad;
436 __u64 modifier;
437};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800438struct drm_mode_create_blob {
439 __u64 data;
440 __u32 length;
441 __u32 blob_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700442};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800443struct drm_mode_destroy_blob {
444 __u32 blob_id;
445};
Christopher Ferris934ec942018-01-31 15:29:16 -0800446struct drm_mode_create_lease {
447 __u64 object_ids;
448 __u32 object_count;
449 __u32 flags;
450 __u32 lessee_id;
451 __u32 fd;
452};
453struct drm_mode_list_lessees {
454 __u32 count_lessees;
455 __u32 pad;
456 __u64 lessees_ptr;
457};
458struct drm_mode_get_lease {
459 __u32 count_objects;
460 __u32 pad;
461 __u64 objects_ptr;
462};
463struct drm_mode_revoke_lease {
464 __u32 lessee_id;
465};
Christopher Ferrisd842e432019-03-07 10:21:59 -0800466struct drm_mode_rect {
467 __s32 x1;
468 __s32 y1;
469 __s32 x2;
470 __s32 y2;
471};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700472#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800473}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700474#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700475#endif