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gerrit.omnirom.org / android_bionic / 48af7cb2e205dcc2f09a1a1b8a1a37c93e1943f0 / . / libc / kernel / uapi / drm / drm_mode.h
blob: c5c0e516e23d28967bdd08c9983ce84663b0577a [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]24#endif
25#define DRM_DISPLAY_INFO_LEN 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26#define DRM_CONNECTOR_NAME_LEN 32
27#define DRM_DISPLAY_MODE_LEN 32
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]30#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]31#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
32#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]34#define DRM_MODE_TYPE_PREFERRED (1 << 3)
35#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]36#define DRM_MODE_TYPE_USERDEF (1 << 5)
37#define DRM_MODE_TYPE_DRIVER (1 << 6)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39#define DRM_MODE_FLAG_PHSYNC (1 << 0)
40#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]41#define DRM_MODE_FLAG_PVSYNC (1 << 2)
42#define DRM_MODE_FLAG_NVSYNC (1 << 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44#define DRM_MODE_FLAG_INTERLACE (1 << 4)
45#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]46#define DRM_MODE_FLAG_CSYNC (1 << 6)
47#define DRM_MODE_FLAG_PCSYNC (1 << 7)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49#define DRM_MODE_FLAG_NCSYNC (1 << 8)
50#define DRM_MODE_FLAG_HSKEW (1 << 9)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]51#define DRM_MODE_FLAG_BCAST (1 << 10)
52#define DRM_MODE_FLAG_PIXMUX (1 << 11)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54#define DRM_MODE_FLAG_DBLCLK (1 << 12)
55#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]56#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
57#define DRM_MODE_FLAG_3D_NONE (0 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
60#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]61#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
62#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
65#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]66#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
67#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]69#define DRM_MODE_PICTURE_ASPECT_NONE 0
70#define DRM_MODE_PICTURE_ASPECT_4_3 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]71#define DRM_MODE_PICTURE_ASPECT_16_9 2
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]72#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
74#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
75#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
76#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
77#define DRM_MODE_DPMS_ON 0
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define DRM_MODE_DPMS_STANDBY 1
80#define DRM_MODE_DPMS_SUSPEND 2
81#define DRM_MODE_DPMS_OFF 3
82#define DRM_MODE_SCALE_NONE 0
83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
84#define DRM_MODE_SCALE_FULLSCREEN 1
85#define DRM_MODE_SCALE_CENTER 2
86#define DRM_MODE_SCALE_ASPECT 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87#define DRM_MODE_DITHERING_OFF 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define DRM_MODE_DITHERING_ON 1
90#define DRM_MODE_DITHERING_AUTO 2
91#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92#define DRM_MODE_DIRTY_ON 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define DRM_MODE_DIRTY_ANNOTATE 2
95struct drm_mode_modeinfo {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]96 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]97 __u16 hdisplay;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]99 __u16 hsync_start;
100 __u16 hsync_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]101 __u16 htotal;
102 __u16 hskew;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]104 __u16 vdisplay;
105 __u16 vsync_start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]106 __u16 vsync_end;
107 __u16 vtotal;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]109 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 __u32 vrefresh;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]111 __u32 flags;
112 __u32 type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115};
116struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 __u64 fb_id_ptr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 __u64 crtc_id_ptr;
120 __u64 connector_id_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]121 __u64 encoder_id_ptr;
122 __u32 count_fbs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]124 __u32 count_crtcs;
125 __u32 count_connectors;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]126 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]127 __u32 min_width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]129 __u32 max_width;
130 __u32 min_height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]131 __u32 max_height;
132};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]135 __u64 set_connectors_ptr;
136 __u32 count_connectors;
137 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]139 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]140 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]141 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]142 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]145 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]146};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]147#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150struct drm_mode_set_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]151 __u32 plane_id;
152 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]154 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]156 __s32 crtc_x;
157 __s32 crtc_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]159 __u32 crtc_w;
160 __u32 crtc_h;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]161 __u32 src_x;
162 __u32 src_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]164 __u32 src_h;
165 __u32 src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]166};
167struct drm_mode_get_plane {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]170 __u32 crtc_id;
171 __u32 fb_id;
172 __u32 possible_crtcs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]175 __u32 count_format_types;
176 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]180 __u64 plane_id_ptr;
181 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_MODE_ENCODER_NONE 0
185#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]186#define DRM_MODE_ENCODER_TMDS 2
187#define DRM_MODE_ENCODER_LVDS 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define DRM_MODE_ENCODER_TVDAC 4
190#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]191#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]192#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
194#define DRM_MODE_ENCODER_DPI 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]195struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]196 __u32 encoder_id;
197 __u32 encoder_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]199 __u32 crtc_id;
200 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]201 __u32 possible_clones;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]204enum drm_mode_subconnector {
205 DRM_MODE_SUBCONNECTOR_Automatic = 0,
206 DRM_MODE_SUBCONNECTOR_Unknown = 0,
207 DRM_MODE_SUBCONNECTOR_DVID = 3,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]209 DRM_MODE_SUBCONNECTOR_DVIA = 4,
210 DRM_MODE_SUBCONNECTOR_Composite = 5,
211 DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
212 DRM_MODE_SUBCONNECTOR_Component = 8,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]214 DRM_MODE_SUBCONNECTOR_SCART = 9,
215};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]217#define DRM_MODE_CONNECTOR_VGA 1
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define DRM_MODE_CONNECTOR_DVII 2
220#define DRM_MODE_CONNECTOR_DVID 3
221#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]222#define DRM_MODE_CONNECTOR_Composite 5
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define DRM_MODE_CONNECTOR_SVIDEO 6
225#define DRM_MODE_CONNECTOR_LVDS 7
226#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]227#define DRM_MODE_CONNECTOR_9PinDIN 9
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229#define DRM_MODE_CONNECTOR_DisplayPort 10
230#define DRM_MODE_CONNECTOR_HDMIA 11
231#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]232#define DRM_MODE_CONNECTOR_TV 13
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]234#define DRM_MODE_CONNECTOR_eDP 14
235#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]236#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]237#define DRM_MODE_CONNECTOR_DPI 17
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]239struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]240 __u64 encoders_ptr;
241 __u64 modes_ptr;
242 __u64 props_ptr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]245 __u32 count_modes;
246 __u32 count_props;
247 __u32 count_encoders;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]249 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]250 __u32 connector_id;
251 __u32 connector_type;
252 __u32 connector_type_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]255 __u32 mm_width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]256 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]257 __u32 subpixel;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]259 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]260};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]261#define DRM_MODE_PROP_PENDING (1 << 0)
262#define DRM_MODE_PROP_RANGE (1 << 1)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]264#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
265#define DRM_MODE_PROP_ENUM (1 << 3)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]266#define DRM_MODE_PROP_BLOB (1 << 4)
267#define DRM_MODE_PROP_BITMASK (1 << 5)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]269#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]270#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
271#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
272#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]274#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]275#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]276struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]277 __u64 value;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]279 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]280};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]281struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]282 __u64 values_ptr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]284 __u64 enum_blob_ptr;
285 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]286 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]287 char name[DRM_PROP_NAME_LEN];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]289 __u32 count_values;
290 __u32 count_enum_blobs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]291};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]292struct drm_mode_connector_set_property {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]294 __u64 value;
295 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]296 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]297};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]299#define DRM_MODE_OBJECT_CRTC 0xcccccccc
300#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]301#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
302#define DRM_MODE_OBJECT_MODE 0xdededede
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]304#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
305#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]306#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
307#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]309#define DRM_MODE_OBJECT_ANY 0
310struct drm_mode_obj_get_properties {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]311 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]312 __u64 prop_values_ptr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]314 __u32 count_props;
315 __u32 obj_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]316 __u32 obj_type;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]317};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]320 __u64 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]321 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]322 __u32 obj_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]324 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]325};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]326struct drm_mode_get_blob {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]327 __u32 blob_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]329 __u32 length;
330 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]331};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]332struct drm_mode_fb_cmd {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]334 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]335 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]336 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]337 __u32 pitch;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]339 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]340 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]341 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]342};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]344#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]345#define DRM_MODE_FB_MODIFIERS (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]346struct drm_mode_fb_cmd2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]347 __u32 fb_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]349 __u32 width;
350 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]351 __u32 pixel_format;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]352 __u32 flags;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]354 __u32 handles[4];
355 __u32 pitches[4];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]356 __u32 offsets[4];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]357 __u64 modifier[4];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]359};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]360#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]361#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]362#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]365struct drm_mode_fb_dirty_cmd {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]366 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]367 __u32 flags;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]369 __u32 color;
370 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]371 __u64 clips_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]372};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375 __u32 connector_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]376 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]377};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]379#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]380#define DRM_MODE_CURSOR_MOVE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]381#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]382struct drm_mode_cursor {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]384 __u32 flags;
385 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]386 __s32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]387 __s32 y;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]389 __u32 width;
390 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]391 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]392};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]394struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]395 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]396 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]397 __s32 x;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]399 __s32 y;
400 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]401 __u32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]402 __u32 handle;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]404 __s32 hot_x;
405 __s32 hot_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]406};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]407struct drm_mode_crtc_lut {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]409 __u32 crtc_id;
410 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]411 __u64 red;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]412 __u64 green;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]414 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]415};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]416struct drm_color_ctm {
417 __s64 matrix[9];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]419};
420struct drm_color_lut {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]421 __u16 red;
422 __u16 green;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]424 __u16 blue;
425 __u16 reserved;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]426};
427#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]429#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]430#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]431#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
432#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]434#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]435struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]436 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]437 __u32 fb_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]439 __u32 flags;
440 __u32 reserved;
441 __u64 user_data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]442};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]444struct drm_mode_crtc_page_flip_target {
445 __u32 crtc_id;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]446 __u32 fb_id;
447 __u32 flags;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]449 __u32 sequence;
450 __u64 user_data;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800[diff] [blame]451};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]452struct drm_mode_create_dumb {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]454 __u32 height;
455 __u32 width;
456 __u32 bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]457 __u32 flags;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]459 __u32 handle;
460 __u32 pitch;
461 __u64 size;
462};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]464struct drm_mode_map_dumb {
465 __u32 handle;
466 __u32 pad;
467 __u64 offset;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]469};
470struct drm_mode_destroy_dumb {
471 __u32 handle;
472};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]474#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
475#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
476#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
477#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]479struct drm_mode_atomic {
480 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]481 __u32 count_objs;
482 __u64 objs_ptr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]484 __u64 count_props_ptr;
485 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]486 __u64 prop_values_ptr;
487 __u64 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]488/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]489 __u64 user_data;
490};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]491struct drm_mode_create_blob {
492 __u64 data;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]493/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]494 __u32 length;
495 __u32 blob_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]496};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]497struct drm_mode_destroy_blob {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]498/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]499 __u32 blob_id;
500};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame]501#ifdef __cplusplus
502#endif
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800[diff] [blame^]503/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]504#endif