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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / drm_mode.h
blob: 8fda8d80b02744eb0438dc269b0ba5f5c8e1fbcd [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
25#define DRM_DISPLAY_INFO_LEN 32
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]26#define DRM_CONNECTOR_NAME_LEN 32
27#define DRM_DISPLAY_MODE_LEN 32
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]30#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]31#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
32#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]34#define DRM_MODE_TYPE_PREFERRED (1 << 3)
35#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]36#define DRM_MODE_TYPE_USERDEF (1 << 5)
37#define DRM_MODE_TYPE_DRIVER (1 << 6)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39#define DRM_MODE_FLAG_PHSYNC (1 << 0)
40#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]41#define DRM_MODE_FLAG_PVSYNC (1 << 2)
42#define DRM_MODE_FLAG_NVSYNC (1 << 3)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44#define DRM_MODE_FLAG_INTERLACE (1 << 4)
45#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]46#define DRM_MODE_FLAG_CSYNC (1 << 6)
47#define DRM_MODE_FLAG_PCSYNC (1 << 7)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49#define DRM_MODE_FLAG_NCSYNC (1 << 8)
50#define DRM_MODE_FLAG_HSKEW (1 << 9)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]51#define DRM_MODE_FLAG_BCAST (1 << 10)
52#define DRM_MODE_FLAG_PIXMUX (1 << 11)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54#define DRM_MODE_FLAG_DBLCLK (1 << 12)
55#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]56#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
57#define DRM_MODE_FLAG_3D_NONE (0 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
60#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]61#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
62#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
65#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]66#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
67#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define DRM_MODE_DPMS_ON 0
70#define DRM_MODE_DPMS_STANDBY 1
71#define DRM_MODE_DPMS_SUSPEND 2
72#define DRM_MODE_DPMS_OFF 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define DRM_MODE_SCALE_NONE 0
75#define DRM_MODE_SCALE_FULLSCREEN 1
76#define DRM_MODE_SCALE_CENTER 2
77#define DRM_MODE_SCALE_ASPECT 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]79#define DRM_MODE_PICTURE_ASPECT_NONE 0
80#define DRM_MODE_PICTURE_ASPECT_4_3 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]81#define DRM_MODE_PICTURE_ASPECT_16_9 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82#define DRM_MODE_DITHERING_OFF 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define DRM_MODE_DITHERING_ON 1
85#define DRM_MODE_DITHERING_AUTO 2
86#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87#define DRM_MODE_DIRTY_ON 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define DRM_MODE_DIRTY_ANNOTATE 2
90struct drm_mode_modeinfo {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]91 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]92 __u16 hdisplay;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]94 __u16 hsync_start;
95 __u16 hsync_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]96 __u16 htotal;
97 __u16 hskew;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]99 __u16 vdisplay;
100 __u16 vsync_start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]101 __u16 vsync_end;
102 __u16 vtotal;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]104 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]105 __u32 vrefresh;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]106 __u32 flags;
107 __u32 type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]109 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]110};
111struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]112 __u64 fb_id_ptr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 __u64 crtc_id_ptr;
115 __u64 connector_id_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]116 __u64 encoder_id_ptr;
117 __u32 count_fbs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 __u32 count_crtcs;
120 __u32 count_connectors;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]121 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]122 __u32 min_width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]124 __u32 max_width;
125 __u32 min_height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]126 __u32 max_height;
127};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]130 __u64 set_connectors_ptr;
131 __u32 count_connectors;
132 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]134 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]135 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]136 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]137 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]139 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]142#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145struct drm_mode_set_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]146 __u32 plane_id;
147 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]150 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]151 __s32 crtc_x;
152 __s32 crtc_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]154 __u32 crtc_w;
155 __u32 crtc_h;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]156 __u32 src_x;
157 __u32 src_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]159 __u32 src_h;
160 __u32 src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]161};
162struct drm_mode_get_plane {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]164 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 __u32 crtc_id;
166 __u32 fb_id;
167 __u32 possible_crtcs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]170 __u32 count_format_types;
171 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]175 __u64 plane_id_ptr;
176 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define DRM_MODE_ENCODER_NONE 0
180#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]181#define DRM_MODE_ENCODER_TMDS 2
182#define DRM_MODE_ENCODER_LVDS 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_MODE_ENCODER_TVDAC 4
185#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]186#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]187#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
189#define DRM_MODE_ENCODER_DPI 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]190struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]191 __u32 encoder_id;
192 __u32 encoder_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]194 __u32 crtc_id;
195 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]196 __u32 possible_clones;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define DRM_MODE_SUBCONNECTOR_Automatic 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]200#define DRM_MODE_SUBCONNECTOR_Unknown 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]201#define DRM_MODE_SUBCONNECTOR_DVID 3
202#define DRM_MODE_SUBCONNECTOR_DVIA 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define DRM_MODE_SUBCONNECTOR_Composite 5
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]205#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]206#define DRM_MODE_SUBCONNECTOR_Component 8
207#define DRM_MODE_SUBCONNECTOR_SCART 9
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]210#define DRM_MODE_CONNECTOR_VGA 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]211#define DRM_MODE_CONNECTOR_DVII 2
212#define DRM_MODE_CONNECTOR_DVID 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]215#define DRM_MODE_CONNECTOR_Composite 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216#define DRM_MODE_CONNECTOR_SVIDEO 6
217#define DRM_MODE_CONNECTOR_LVDS 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]220#define DRM_MODE_CONNECTOR_9PinDIN 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]221#define DRM_MODE_CONNECTOR_DisplayPort 10
222#define DRM_MODE_CONNECTOR_HDMIA 11
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]225#define DRM_MODE_CONNECTOR_TV 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]226#define DRM_MODE_CONNECTOR_eDP 14
227#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]229#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]230#define DRM_MODE_CONNECTOR_DPI 17
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]231struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]232 __u64 encoders_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234 __u64 modes_ptr;
235 __u64 props_ptr;
236 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]237 __u32 count_modes;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]239 __u32 count_props;
240 __u32 count_encoders;
241 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]242 __u32 connector_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]244 __u32 connector_type;
245 __u32 connector_type_id;
246 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]247 __u32 mm_width;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]249 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]250 __u32 subpixel;
251 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]252};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254#define DRM_MODE_PROP_PENDING (1 << 0)
255#define DRM_MODE_PROP_RANGE (1 << 1)
256#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
257#define DRM_MODE_PROP_ENUM (1 << 3)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]259#define DRM_MODE_PROP_BLOB (1 << 4)
260#define DRM_MODE_PROP_BITMASK (1 << 5)
261#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]262#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]264#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
265#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
266#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]267#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]269struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]270 __u64 value;
271 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]274struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]275 __u64 values_ptr;
276 __u64 enum_blob_ptr;
277 __u32 prop_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]279 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]280 char name[DRM_PROP_NAME_LEN];
281 __u32 count_values;
282 __u32 count_enum_blobs;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]284};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]285struct drm_mode_connector_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]286 __u64 value;
287 __u32 prop_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]289 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]290};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]291#define DRM_MODE_OBJECT_CRTC 0xcccccccc
292#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]294#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
295#define DRM_MODE_OBJECT_MODE 0xdededede
296#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
297#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
299#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
300#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
301#define DRM_MODE_OBJECT_ANY 0
302struct drm_mode_obj_get_properties {
303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
304 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]305 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]306 __u32 count_props;
307 __u32 obj_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]309 __u32 obj_type;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]310};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]311struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]312 __u64 value;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]314 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]315 __u32 obj_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]316 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]317};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]319struct drm_mode_get_blob {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]320 __u32 blob_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]321 __u32 length;
322 __u64 data;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]324};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]325struct drm_mode_fb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]326 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]327 __u32 width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]329 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]330 __u32 pitch;
331 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]332 __u32 depth;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]334 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]335};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]336#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]337#define DRM_MODE_FB_MODIFIERS (1 << 1)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]339struct drm_mode_fb_cmd2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]340 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]341 __u32 width;
342 __u32 height;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]344 __u32 pixel_format;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]345 __u32 flags;
346 __u32 handles[4];
347 __u32 pitches[4];
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]349 __u32 offsets[4];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]350 __u64 modifier[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]351};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]352#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]354#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]355#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]356#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]357struct drm_mode_fb_dirty_cmd {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]359 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]360 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]361 __u32 color;
362 __u32 num_clips;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]364 __u64 clips_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]365};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]366struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]367 __u32 connector_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]369 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]370};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]371#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]372#define DRM_MODE_CURSOR_MOVE 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]374#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]375struct drm_mode_cursor {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]376 __u32 flags;
377 __u32 crtc_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]379 __s32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]380 __s32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]381 __u32 width;
382 __u32 height;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]384 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]385};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]386struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]387 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]389 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]390 __s32 x;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]391 __s32 y;
392 __u32 width;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]394 __u32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]395 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]396 __s32 hot_x;
397 __s32 hot_y;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]399};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]400struct drm_mode_crtc_lut {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]401 __u32 crtc_id;
402 __u32 gamma_size;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]404 __u64 red;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]405 __u64 green;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]406 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]407};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]409struct drm_color_ctm {
410 __s64 matrix[9];
411};
412struct drm_color_lut {
413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
414 __u16 red;
415 __u16 green;
416 __u16 blue;
417 __u16 reserved;
418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
419};
420#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]421#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]422#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]424struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]425 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]426 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]427 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]429 __u32 reserved;
430 __u64 user_data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]431};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]432struct drm_mode_create_dumb {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]434 __u32 height;
435 __u32 width;
436 __u32 bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]437 __u32 flags;
438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]439 __u32 handle;
440 __u32 pitch;
441 __u64 size;
442};
443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
444struct drm_mode_map_dumb {
445 __u32 handle;
446 __u32 pad;
447 __u64 offset;
448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
449};
450struct drm_mode_destroy_dumb {
451 __u32 handle;
452};
453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
454#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
455#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
456#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
457#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
458/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
459struct drm_mode_atomic {
460 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]461 __u32 count_objs;
462 __u64 objs_ptr;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]463/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]464 __u64 count_props_ptr;
465 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]466 __u64 prop_values_ptr;
467 __u64 reserved;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]468/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]469 __u64 user_data;
470};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]471struct drm_mode_create_blob {
472 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]473/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]474 __u32 length;
475 __u32 blob_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]476};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]477struct drm_mode_destroy_blob {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]478/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]479 __u32 blob_id;
480};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]481#ifdef __cplusplus
482#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]483/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]484#endif