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gerrit.omnirom.org / android_bionic / 82d7504cd7d5c8d2175fb3b1a4ee3518cad6aa0f / . / libc / kernel / uapi / drm / drm_mode.h
blob: 4a69518718b2055e0d3b3a8470e980c0db5579ee [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
21#include <linux/types.h>
22#define DRM_DISPLAY_INFO_LEN 32
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define DRM_CONNECTOR_NAME_LEN 32
25#define DRM_DISPLAY_MODE_LEN 32
26#define DRM_PROP_NAME_LEN 32
27#define DRM_MODE_TYPE_BUILTIN (1<<0)
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
29#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1<<3)
32#define DRM_MODE_TYPE_DEFAULT (1<<4)
33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
34#define DRM_MODE_TYPE_USERDEF (1<<5)
35#define DRM_MODE_TYPE_DRIVER (1<<6)
36#define DRM_MODE_FLAG_PHSYNC (1<<0)
37#define DRM_MODE_FLAG_NHSYNC (1<<1)
38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
39#define DRM_MODE_FLAG_PVSYNC (1<<2)
40#define DRM_MODE_FLAG_NVSYNC (1<<3)
41#define DRM_MODE_FLAG_INTERLACE (1<<4)
42#define DRM_MODE_FLAG_DBLSCAN (1<<5)
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
44#define DRM_MODE_FLAG_CSYNC (1<<6)
45#define DRM_MODE_FLAG_PCSYNC (1<<7)
46#define DRM_MODE_FLAG_NCSYNC (1<<8)
47#define DRM_MODE_FLAG_HSKEW (1<<9)
48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
49#define DRM_MODE_FLAG_BCAST (1<<10)
50#define DRM_MODE_FLAG_PIXMUX (1<<11)
51#define DRM_MODE_FLAG_DBLCLK (1<<12)
52#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]54#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
55#define DRM_MODE_FLAG_3D_NONE (0<<14)
56#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
57#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
59#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
60#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
61#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
62#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
64#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
65#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66#define DRM_MODE_DPMS_ON 0
67#define DRM_MODE_DPMS_STANDBY 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define DRM_MODE_DPMS_SUSPEND 2
70#define DRM_MODE_DPMS_OFF 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define DRM_MODE_SCALE_NONE 0
72#define DRM_MODE_SCALE_FULLSCREEN 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define DRM_MODE_SCALE_CENTER 2
75#define DRM_MODE_SCALE_ASPECT 3
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]76#define DRM_MODE_PICTURE_ASPECT_NONE 0
77#define DRM_MODE_PICTURE_ASPECT_4_3 1
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define DRM_MODE_PICTURE_ASPECT_16_9 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80#define DRM_MODE_DITHERING_OFF 0
81#define DRM_MODE_DITHERING_ON 1
82#define DRM_MODE_DITHERING_AUTO 2
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85#define DRM_MODE_DIRTY_ON 1
86#define DRM_MODE_DIRTY_ANNOTATE 2
87struct drm_mode_modeinfo {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89 __u32 clock;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90 __u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
91 __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
92 __u32 vrefresh;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95 __u32 type;
96 char name[DRM_DISPLAY_MODE_LEN];
97};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99struct drm_mode_card_res {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100 __u64 fb_id_ptr;
101 __u64 crtc_id_ptr;
102 __u64 connector_id_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104 __u64 encoder_id_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]105 __u32 count_fbs;
106 __u32 count_crtcs;
107 __u32 count_connectors;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109 __u32 count_encoders;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]110 __u32 min_width, max_width;
111 __u32 min_height, max_height;
112};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114struct drm_mode_crtc {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115 __u64 set_connectors_ptr;
116 __u32 count_connectors;
117 __u32 crtc_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119 __u32 fb_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]120 __u32 x, y;
121 __u32 gamma_size;
122 __u32 mode_valid;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]125};
126#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
127#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129struct drm_mode_set_plane {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130 __u32 plane_id;
131 __u32 crtc_id;
132 __u32 fb_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]135 __s32 crtc_x, crtc_y;
136 __u32 crtc_w, crtc_h;
137 __u32 src_x, src_y;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139 __u32 src_h, src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]140};
141struct drm_mode_get_plane {
142 __u32 plane_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144 __u32 crtc_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145 __u32 fb_id;
146 __u32 possible_crtcs;
147 __u32 gamma_size;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149 __u32 count_format_types;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150 __u64 format_type_ptr;
151};
152struct drm_mode_get_plane_res {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154 __u64 plane_id_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]155 __u32 count_planes;
156};
157#define DRM_MODE_ENCODER_NONE 0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]160#define DRM_MODE_ENCODER_TMDS 2
161#define DRM_MODE_ENCODER_LVDS 3
162#define DRM_MODE_ENCODER_TVDAC 4
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]165#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]166#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]167struct drm_mode_get_encoder {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169 __u32 encoder_id;
170 __u32 encoder_type;
171 __u32 crtc_id;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]172 __u32 possible_crtcs;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174 __u32 possible_clones;
175};
176#define DRM_MODE_SUBCONNECTOR_Automatic 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]177#define DRM_MODE_SUBCONNECTOR_Unknown 0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define DRM_MODE_SUBCONNECTOR_DVID 3
180#define DRM_MODE_SUBCONNECTOR_DVIA 4
181#define DRM_MODE_SUBCONNECTOR_Composite 5
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]182#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_MODE_SUBCONNECTOR_Component 8
185#define DRM_MODE_SUBCONNECTOR_SCART 9
186#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]187#define DRM_MODE_CONNECTOR_VGA 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define DRM_MODE_CONNECTOR_DVII 2
190#define DRM_MODE_CONNECTOR_DVID 3
191#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]192#define DRM_MODE_CONNECTOR_Composite 5
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define DRM_MODE_CONNECTOR_SVIDEO 6
195#define DRM_MODE_CONNECTOR_LVDS 7
196#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]197#define DRM_MODE_CONNECTOR_9PinDIN 9
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define DRM_MODE_CONNECTOR_DisplayPort 10
200#define DRM_MODE_CONNECTOR_HDMIA 11
201#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]202#define DRM_MODE_CONNECTOR_TV 13
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define DRM_MODE_CONNECTOR_eDP 14
205#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]206#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]207struct drm_mode_get_connector {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209 __u64 encoders_ptr;
210 __u64 modes_ptr;
211 __u64 props_ptr;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]212 __u64 prop_values_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214 __u32 count_modes;
215 __u32 count_props;
216 __u32 count_encoders;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]217 __u32 encoder_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219 __u32 connector_id;
220 __u32 connector_type;
221 __u32 connector_type_id;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]222 __u32 connection;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224 __u32 mm_width, mm_height;
225 __u32 subpixel;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]226 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]227};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]229#define DRM_MODE_PROP_PENDING (1<<0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]230#define DRM_MODE_PROP_RANGE (1<<1)
231#define DRM_MODE_PROP_IMMUTABLE (1<<2)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]232#define DRM_MODE_PROP_ENUM (1<<3)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]234#define DRM_MODE_PROP_BLOB (1<<4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]235#define DRM_MODE_PROP_BITMASK (1<<5)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]236#define DRM_MODE_PROP_LEGACY_TYPE ( DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]237#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]239#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
240#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
241#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]242struct drm_mode_property_enum {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]244 __u64 value;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]245 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]246};
247struct drm_mode_get_property {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]249 __u64 values_ptr;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]250 __u64 enum_blob_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]251 __u32 prop_id;
252 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]254 char name[DRM_PROP_NAME_LEN];
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]255 __u32 count_values;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]256 __u32 count_enum_blobs;
257};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]259struct drm_mode_connector_set_property {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]260 __u64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]261 __u32 prop_id;
262 __u32 connector_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]265struct drm_mode_obj_get_properties {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]266 __u64 props_ptr;
267 __u64 prop_values_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]269 __u32 count_props;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]270 __u32 obj_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]271 __u32 obj_type;
272};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274struct drm_mode_obj_set_property {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]275 __u64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]276 __u32 prop_id;
277 __u32 obj_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]279 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]280};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]281struct drm_mode_get_blob {
282 __u32 blob_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284 __u32 length;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]285 __u64 data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]286};
287struct drm_mode_fb_cmd {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]289 __u32 fb_id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]290 __u32 width, height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]291 __u32 pitch;
292 __u32 bpp;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]294 __u32 depth;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]295 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]296};
297#define DRM_MODE_FB_INTERLACED (1<<0)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]299struct drm_mode_fb_cmd2 {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]300 __u32 fb_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]301 __u32 width, height;
302 __u32 pixel_format;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]304 __u32 flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]305 __u32 handles[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]306 __u32 pitches[4];
307 __u32 offsets[4];
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]309};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]310#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]311#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
312#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]314#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]315struct drm_mode_fb_dirty_cmd {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]316 __u32 fb_id;
317 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319 __u32 color;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]320 __u32 num_clips;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]321 __u64 clips_ptr;
322};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]324struct drm_mode_mode_cmd {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]325 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]326 struct drm_mode_modeinfo mode;
327};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]329#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]330#define DRM_MODE_CURSOR_MOVE 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]331#define DRM_MODE_CURSOR_FLAGS 0x03
332struct drm_mode_cursor {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]334 __u32 flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]335 __u32 crtc_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]336 __s32 x;
337 __s32 y;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]339 __u32 width;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]340 __u32 height;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]341 __u32 handle;
342};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]344struct drm_mode_cursor2 {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]345 __u32 flags;
346 __u32 crtc_id;
347 __s32 x;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]349 __s32 y;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]350 __u32 width;
351 __u32 height;
352 __u32 handle;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]354 __s32 hot_x;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]355 __s32 hot_y;
356};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]357struct drm_mode_crtc_lut {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]359 __u32 crtc_id;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]360 __u32 gamma_size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]361 __u64 red;
362 __u64 green;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]364 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]365};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]366#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]367#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]369#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]370struct drm_mode_crtc_page_flip {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]371 __u32 crtc_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]372 __u32 fb_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]374 __u32 flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]375 __u32 reserved;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]376 __u64 user_data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]377};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]379struct drm_mode_create_dumb {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]380 uint32_t height;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]381 uint32_t width;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]382 uint32_t bpp;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]384 uint32_t flags;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]385 uint32_t handle;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]386 uint32_t pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]387 uint64_t size;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]389};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]390struct drm_mode_map_dumb {
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]391 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]392 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]394 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]395};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]396struct drm_mode_destroy_dumb {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]397 uint32_t handle;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame^]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]399};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]400#endif