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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / drm / drm_mode.h
blob: 240a8ae9c81c043cb1b2383a19522aa99e4b527b [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
21#include <linux/types.h>
22#define DRM_DISPLAY_INFO_LEN 32
23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
24#define DRM_CONNECTOR_NAME_LEN 32
25#define DRM_DISPLAY_MODE_LEN 32
26#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]27#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]29#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]34#define DRM_MODE_TYPE_USERDEF (1 << 5)
35#define DRM_MODE_TYPE_DRIVER (1 << 6)
36#define DRM_MODE_FLAG_PHSYNC (1 << 0)
37#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39#define DRM_MODE_FLAG_PVSYNC (1 << 2)
40#define DRM_MODE_FLAG_NVSYNC (1 << 3)
41#define DRM_MODE_FLAG_INTERLACE (1 << 4)
42#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44#define DRM_MODE_FLAG_CSYNC (1 << 6)
45#define DRM_MODE_FLAG_PCSYNC (1 << 7)
46#define DRM_MODE_FLAG_NCSYNC (1 << 8)
47#define DRM_MODE_FLAG_HSKEW (1 << 9)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49#define DRM_MODE_FLAG_BCAST (1 << 10)
50#define DRM_MODE_FLAG_PIXMUX (1 << 11)
51#define DRM_MODE_FLAG_DBLCLK (1 << 12)
52#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
55#define DRM_MODE_FLAG_3D_NONE (0 << 14)
56#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
57#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
60#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
61#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
62#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
65#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]66#define DRM_MODE_DPMS_ON 0
67#define DRM_MODE_DPMS_STANDBY 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define DRM_MODE_DPMS_SUSPEND 2
70#define DRM_MODE_DPMS_OFF 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define DRM_MODE_SCALE_NONE 0
72#define DRM_MODE_SCALE_FULLSCREEN 1
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define DRM_MODE_SCALE_CENTER 2
75#define DRM_MODE_SCALE_ASPECT 3
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]76#define DRM_MODE_PICTURE_ASPECT_NONE 0
77#define DRM_MODE_PICTURE_ASPECT_4_3 1
78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
79#define DRM_MODE_PICTURE_ASPECT_16_9 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80#define DRM_MODE_DITHERING_OFF 0
81#define DRM_MODE_DITHERING_ON 1
82#define DRM_MODE_DITHERING_AUTO 2
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85#define DRM_MODE_DIRTY_ON 1
86#define DRM_MODE_DIRTY_ANNOTATE 2
87struct drm_mode_modeinfo {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]89 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]90 __u16 hdisplay;
91 __u16 hsync_start;
92 __u16 hsync_end;
93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
94 __u16 htotal;
95 __u16 hskew;
96 __u16 vdisplay;
97 __u16 vsync_start;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
99 __u16 vsync_end;
100 __u16 vtotal;
101 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102 __u32 vrefresh;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]104 __u32 flags;
105 __u32 type;
106 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 __u64 fb_id_ptr;
111 __u64 crtc_id_ptr;
112 __u64 connector_id_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 __u64 encoder_id_ptr;
115 __u32 count_fbs;
116 __u32 count_crtcs;
117 __u32 count_connectors;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]120 __u32 min_width;
121 __u32 max_width;
122 __u32 min_height;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]124 __u32 max_height;
125};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]127 __u64 set_connectors_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]129 __u32 count_connectors;
130 __u32 crtc_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]131 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]132 __u32 x;
133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
134 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]135 __u32 gamma_size;
136 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]137 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
141#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]142struct drm_mode_set_plane {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 __u32 plane_id;
145 __u32 crtc_id;
146 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]147 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]149 __s32 crtc_x;
150 __s32 crtc_y;
151 __u32 crtc_w;
152 __u32 crtc_h;
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
154 __u32 src_x;
155 __u32 src_y;
156 __u32 src_h;
157 __u32 src_w;
158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]159};
160struct drm_mode_get_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]161 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]162 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]164 __u32 fb_id;
165 __u32 possible_crtcs;
166 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]167 __u32 count_format_types;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]170};
171struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]172 __u64 plane_id_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]175};
176#define DRM_MODE_ENCODER_NONE 0
177#define DRM_MODE_ENCODER_DAC 1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define DRM_MODE_ENCODER_TMDS 2
180#define DRM_MODE_ENCODER_LVDS 3
181#define DRM_MODE_ENCODER_TVDAC 4
182#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]184#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]185#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]186struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]187 __u32 encoder_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]189 __u32 encoder_type;
190 __u32 crtc_id;
191 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]192 __u32 possible_clones;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194};
195#define DRM_MODE_SUBCONNECTOR_Automatic 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]196#define DRM_MODE_SUBCONNECTOR_Unknown 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]197#define DRM_MODE_SUBCONNECTOR_DVID 3
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]199#define DRM_MODE_SUBCONNECTOR_DVIA 4
200#define DRM_MODE_SUBCONNECTOR_Composite 5
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]201#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202#define DRM_MODE_SUBCONNECTOR_Component 8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204#define DRM_MODE_SUBCONNECTOR_SCART 9
205#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]206#define DRM_MODE_CONNECTOR_VGA 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]207#define DRM_MODE_CONNECTOR_DVII 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]209#define DRM_MODE_CONNECTOR_DVID 3
210#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]211#define DRM_MODE_CONNECTOR_Composite 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212#define DRM_MODE_CONNECTOR_SVIDEO 6
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214#define DRM_MODE_CONNECTOR_LVDS 7
215#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]216#define DRM_MODE_CONNECTOR_9PinDIN 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217#define DRM_MODE_CONNECTOR_DisplayPort 10
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219#define DRM_MODE_CONNECTOR_HDMIA 11
220#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]221#define DRM_MODE_CONNECTOR_TV 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222#define DRM_MODE_CONNECTOR_eDP 14
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]225#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]226struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]227 __u64 encoders_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]229 __u64 modes_ptr;
230 __u64 props_ptr;
231 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]232 __u32 count_modes;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234 __u32 count_props;
235 __u32 count_encoders;
236 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]237 __u32 connector_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]239 __u32 connector_type;
240 __u32 connector_type_id;
241 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]242 __u32 mm_width;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]244 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]245 __u32 subpixel;
246 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]247};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]249#define DRM_MODE_PROP_PENDING (1 << 0)
250#define DRM_MODE_PROP_RANGE (1 << 1)
251#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
252#define DRM_MODE_PROP_ENUM (1 << 3)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254#define DRM_MODE_PROP_BLOB (1 << 4)
255#define DRM_MODE_PROP_BITMASK (1 << 5)
256#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]257#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]259#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
260#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
261#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]262#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]264struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]265 __u64 value;
266 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]269struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]270 __u64 values_ptr;
271 __u64 enum_blob_ptr;
272 __u32 prop_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]274 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]275 char name[DRM_PROP_NAME_LEN];
276 __u32 count_values;
277 __u32 count_enum_blobs;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]279};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]280struct drm_mode_connector_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]281 __u64 value;
282 __u32 prop_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]284 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]285};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]286struct drm_mode_obj_get_properties {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]287 __u64 props_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]289 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]290 __u32 count_props;
291 __u32 obj_id;
292 __u32 obj_type;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]294};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]295struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]296 __u64 value;
297 __u32 prop_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]299 __u32 obj_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]300 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]301};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]302struct drm_mode_get_blob {
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]304 __u32 blob_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]305 __u32 length;
306 __u64 data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]307};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]309struct drm_mode_fb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]310 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]311 __u32 width;
312 __u32 height;
313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]314 __u32 pitch;
315 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]316 __u32 depth;
317 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]319};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]320#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]321#define DRM_MODE_FB_MODIFIERS (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]322struct drm_mode_fb_cmd2 {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]324 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]325 __u32 width;
326 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]327 __u32 pixel_format;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]329 __u32 flags;
330 __u32 handles[4];
331 __u32 pitches[4];
332 __u32 offsets[4];
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]334 __u64 modifier[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]335};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]336#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]337#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]339#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]340#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]341struct drm_mode_fb_dirty_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]342 __u32 fb_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]344 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]345 __u32 color;
346 __u32 num_clips;
347 __u64 clips_ptr;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]349};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]350struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]351 __u32 connector_id;
352 struct drm_mode_modeinfo mode;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]354};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]355#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]356#define DRM_MODE_CURSOR_MOVE 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]357#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]359struct drm_mode_cursor {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]360 __u32 flags;
361 __u32 crtc_id;
362 __s32 x;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]364 __s32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]365 __u32 width;
366 __u32 height;
367 __u32 handle;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]369};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]370struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]371 __u32 flags;
372 __u32 crtc_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]374 __s32 x;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375 __s32 y;
376 __u32 width;
377 __u32 height;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]379 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]380 __s32 hot_x;
381 __s32 hot_y;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]382};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]384struct drm_mode_crtc_lut {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]385 __u32 crtc_id;
386 __u32 gamma_size;
387 __u64 red;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]389 __u64 green;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]390 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]391};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]392#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]394#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]395#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]396struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]397 __u32 crtc_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]398/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]399 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]400 __u32 flags;
401 __u32 reserved;
402 __u64 user_data;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]403/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]404};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]405struct drm_mode_create_dumb {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]406 uint32_t height;
407 uint32_t width;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]408/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]409 uint32_t bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]410 uint32_t flags;
411 uint32_t handle;
412 uint32_t pitch;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]413/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]414 uint64_t size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]415};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]416struct drm_mode_map_dumb {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]417 __u32 handle;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]418/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]419 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]420 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]421};
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800[diff] [blame]422struct drm_mode_destroy_dumb {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]423/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]424 uint32_t handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]425};
426#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
427#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
428/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
429#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
430#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
431struct drm_mode_atomic {
432 __u32 flags;
433/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
434 __u32 count_objs;
435 __u64 objs_ptr;
436 __u64 count_props_ptr;
437 __u64 props_ptr;
438/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
439 __u64 prop_values_ptr;
440 __u64 reserved;
441 __u64 user_data;
442};
443/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
444struct drm_mode_create_blob {
445 __u64 data;
446 __u32 length;
447 __u32 blob_id;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]448/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]449};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]450struct drm_mode_destroy_blob {
451 __u32 blob_id;
452};
453/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]454#endif