blob: 06c26e4ba030e62ba273b47e89b11f81ec601291 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#define DRM_DISPLAY_INFO_LEN 32
Ben Cheng655a7c02013-10-16 16:09:24 -070025#define DRM_CONNECTOR_NAME_LEN 32
26#define DRM_DISPLAY_MODE_LEN 32
27#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -080028#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -080029#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -080033#define DRM_MODE_TYPE_USERDEF (1 << 5)
34#define DRM_MODE_TYPE_DRIVER (1 << 6)
Christopher Ferris76a1d452018-06-27 14:12:29 -070035#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)
Tao Baod7db5942015-01-28 10:07:51 -080036#define DRM_MODE_FLAG_PHSYNC (1 << 0)
37#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -080038#define DRM_MODE_FLAG_PVSYNC (1 << 2)
39#define DRM_MODE_FLAG_NVSYNC (1 << 3)
40#define DRM_MODE_FLAG_INTERLACE (1 << 4)
41#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -080042#define DRM_MODE_FLAG_CSYNC (1 << 6)
43#define DRM_MODE_FLAG_PCSYNC (1 << 7)
44#define DRM_MODE_FLAG_NCSYNC (1 << 8)
45#define DRM_MODE_FLAG_HSKEW (1 << 9)
Tao Baod7db5942015-01-28 10:07:51 -080046#define DRM_MODE_FLAG_BCAST (1 << 10)
47#define DRM_MODE_FLAG_PIXMUX (1 << 11)
48#define DRM_MODE_FLAG_DBLCLK (1 << 12)
49#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Tao Baod7db5942015-01-28 10:07:51 -080050#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
51#define DRM_MODE_FLAG_3D_NONE (0 << 14)
52#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
53#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080054#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
55#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
56#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
57#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080058#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
59#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Christopher Ferris82d75042015-01-26 10:57:07 -080060#define DRM_MODE_PICTURE_ASPECT_NONE 0
61#define DRM_MODE_PICTURE_ASPECT_4_3 1
Christopher Ferris82d75042015-01-26 10:57:07 -080062#define DRM_MODE_PICTURE_ASPECT_16_9 2
Christopher Ferris9ce28842018-10-25 12:11:39 -070063#define DRM_MODE_PICTURE_ASPECT_64_27 3
64#define DRM_MODE_PICTURE_ASPECT_256_135 4
65#define DRM_MODE_CONTENT_TYPE_NO_DATA 0
66#define DRM_MODE_CONTENT_TYPE_GRAPHICS 1
67#define DRM_MODE_CONTENT_TYPE_PHOTO 2
68#define DRM_MODE_CONTENT_TYPE_CINEMA 3
69#define DRM_MODE_CONTENT_TYPE_GAME 4
Christopher Ferris48af7cb2017-02-21 12:35:09 -080070#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080071#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
72#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
73#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
Christopher Ferris9ce28842018-10-25 12:11:39 -070074#define DRM_MODE_FLAG_PIC_AR_64_27 (DRM_MODE_PICTURE_ASPECT_64_27 << 19)
75#define DRM_MODE_FLAG_PIC_AR_256_135 (DRM_MODE_PICTURE_ASPECT_256_135 << 19)
Christopher Ferris76a1d452018-06-27 14:12:29 -070076#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080077#define DRM_MODE_DPMS_ON 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080078#define DRM_MODE_DPMS_STANDBY 1
79#define DRM_MODE_DPMS_SUSPEND 2
80#define DRM_MODE_DPMS_OFF 3
81#define DRM_MODE_SCALE_NONE 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080082#define DRM_MODE_SCALE_FULLSCREEN 1
83#define DRM_MODE_SCALE_CENTER 2
84#define DRM_MODE_SCALE_ASPECT 3
Ben Cheng655a7c02013-10-16 16:09:24 -070085#define DRM_MODE_DITHERING_OFF 0
86#define DRM_MODE_DITHERING_ON 1
87#define DRM_MODE_DITHERING_AUTO 2
88#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -070089#define DRM_MODE_DIRTY_ON 1
90#define DRM_MODE_DIRTY_ANNOTATE 2
Christopher Ferris525ce912017-07-26 13:12:53 -070091#define DRM_MODE_LINK_STATUS_GOOD 0
92#define DRM_MODE_LINK_STATUS_BAD 1
Christopher Ferris1308ad32017-11-14 17:32:13 -080093#define DRM_MODE_ROTATE_0 (1 << 0)
94#define DRM_MODE_ROTATE_90 (1 << 1)
95#define DRM_MODE_ROTATE_180 (1 << 2)
96#define DRM_MODE_ROTATE_270 (1 << 3)
97#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
98#define DRM_MODE_REFLECT_X (1 << 4)
99#define DRM_MODE_REFLECT_Y (1 << 5)
100#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
Christopher Ferris76a1d452018-06-27 14:12:29 -0700101#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
102#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
103#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700104struct drm_mode_modeinfo {
Tao Baod7db5942015-01-28 10:07:51 -0800105 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106 __u16 hdisplay;
107 __u16 hsync_start;
108 __u16 hsync_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 __u16 htotal;
110 __u16 hskew;
111 __u16 vdisplay;
112 __u16 vsync_start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113 __u16 vsync_end;
114 __u16 vtotal;
115 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800116 __u32 vrefresh;
Tao Baod7db5942015-01-28 10:07:51 -0800117 __u32 flags;
118 __u32 type;
119 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700120};
121struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800122 __u64 fb_id_ptr;
123 __u64 crtc_id_ptr;
124 __u64 connector_id_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800125 __u64 encoder_id_ptr;
126 __u32 count_fbs;
127 __u32 count_crtcs;
128 __u32 count_connectors;
Tao Baod7db5942015-01-28 10:07:51 -0800129 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130 __u32 min_width;
131 __u32 max_width;
132 __u32 min_height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133 __u32 max_height;
134};
Ben Cheng655a7c02013-10-16 16:09:24 -0700135struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800136 __u64 set_connectors_ptr;
137 __u32 count_connectors;
138 __u32 crtc_id;
Tao Baod7db5942015-01-28 10:07:51 -0800139 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800140 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800142 __u32 gamma_size;
143 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800144 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700145};
Tao Baod7db5942015-01-28 10:07:51 -0800146#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
147#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700148struct drm_mode_set_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800149 __u32 plane_id;
150 __u32 crtc_id;
151 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800152 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800153 __s32 crtc_x;
154 __s32 crtc_y;
155 __u32 crtc_w;
156 __u32 crtc_h;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800157 __u32 src_x;
158 __u32 src_y;
159 __u32 src_h;
160 __u32 src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700161};
162struct drm_mode_get_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800163 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800164 __u32 crtc_id;
165 __u32 fb_id;
166 __u32 possible_crtcs;
167 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800168 __u32 count_format_types;
169 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700170};
171struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800172 __u64 plane_id_ptr;
173 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700174};
175#define DRM_MODE_ENCODER_NONE 0
176#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700177#define DRM_MODE_ENCODER_TMDS 2
178#define DRM_MODE_ENCODER_LVDS 3
179#define DRM_MODE_ENCODER_TVDAC 4
180#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700181#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700182#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700183#define DRM_MODE_ENCODER_DPI 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700184struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800185 __u32 encoder_id;
186 __u32 encoder_type;
187 __u32 crtc_id;
188 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800189 __u32 possible_clones;
Ben Cheng655a7c02013-10-16 16:09:24 -0700190};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800191enum drm_mode_subconnector {
192 DRM_MODE_SUBCONNECTOR_Automatic = 0,
193 DRM_MODE_SUBCONNECTOR_Unknown = 0,
194 DRM_MODE_SUBCONNECTOR_DVID = 3,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800195 DRM_MODE_SUBCONNECTOR_DVIA = 4,
196 DRM_MODE_SUBCONNECTOR_Composite = 5,
197 DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
198 DRM_MODE_SUBCONNECTOR_Component = 8,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800199 DRM_MODE_SUBCONNECTOR_SCART = 9,
200};
Ben Cheng655a7c02013-10-16 16:09:24 -0700201#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700202#define DRM_MODE_CONNECTOR_VGA 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700203#define DRM_MODE_CONNECTOR_DVII 2
204#define DRM_MODE_CONNECTOR_DVID 3
205#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700206#define DRM_MODE_CONNECTOR_Composite 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700207#define DRM_MODE_CONNECTOR_SVIDEO 6
208#define DRM_MODE_CONNECTOR_LVDS 7
209#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700210#define DRM_MODE_CONNECTOR_9PinDIN 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700211#define DRM_MODE_CONNECTOR_DisplayPort 10
212#define DRM_MODE_CONNECTOR_HDMIA 11
213#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700214#define DRM_MODE_CONNECTOR_TV 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700215#define DRM_MODE_CONNECTOR_eDP 14
216#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700217#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700218#define DRM_MODE_CONNECTOR_DPI 17
Christopher Ferris9ce28842018-10-25 12:11:39 -0700219#define DRM_MODE_CONNECTOR_WRITEBACK 18
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700220struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800221 __u64 encoders_ptr;
222 __u64 modes_ptr;
223 __u64 props_ptr;
224 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800225 __u32 count_modes;
226 __u32 count_props;
227 __u32 count_encoders;
228 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800229 __u32 connector_id;
230 __u32 connector_type;
231 __u32 connector_type_id;
232 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800233 __u32 mm_width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800234 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800235 __u32 subpixel;
236 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700237};
Tao Baod7db5942015-01-28 10:07:51 -0800238#define DRM_MODE_PROP_PENDING (1 << 0)
239#define DRM_MODE_PROP_RANGE (1 << 1)
240#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
241#define DRM_MODE_PROP_ENUM (1 << 3)
Tao Baod7db5942015-01-28 10:07:51 -0800242#define DRM_MODE_PROP_BLOB (1 << 4)
243#define DRM_MODE_PROP_BITMASK (1 << 5)
244#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700245#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
246#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
247#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
248#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800249#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800250struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800251 __u64 value;
252 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700253};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800254struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800255 __u64 values_ptr;
256 __u64 enum_blob_ptr;
257 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800258 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800259 char name[DRM_PROP_NAME_LEN];
260 __u32 count_values;
261 __u32 count_enum_blobs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800262};
Ben Cheng655a7c02013-10-16 16:09:24 -0700263struct drm_mode_connector_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800264 __u64 value;
265 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800266 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700267};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700268#define DRM_MODE_OBJECT_CRTC 0xcccccccc
269#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700270#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
271#define DRM_MODE_OBJECT_MODE 0xdededede
272#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
273#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
Christopher Ferris106b3a82016-08-24 12:15:38 -0700274#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
275#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
276#define DRM_MODE_OBJECT_ANY 0
277struct drm_mode_obj_get_properties {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700278 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800279 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800280 __u32 count_props;
281 __u32 obj_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700282 __u32 obj_type;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800283};
Ben Cheng655a7c02013-10-16 16:09:24 -0700284struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800285 __u64 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700286 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800287 __u32 obj_id;
Tao Baod7db5942015-01-28 10:07:51 -0800288 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700289};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700290struct drm_mode_get_blob {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800291 __u32 blob_id;
Tao Baod7db5942015-01-28 10:07:51 -0800292 __u32 length;
293 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700294};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800295struct drm_mode_fb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800296 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800297 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700298 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800299 __u32 pitch;
300 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800301 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700302 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700303};
Tao Baod7db5942015-01-28 10:07:51 -0800304#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800305#define DRM_MODE_FB_MODIFIERS (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700306struct drm_mode_fb_cmd2 {
Tao Baod7db5942015-01-28 10:07:51 -0800307 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800308 __u32 width;
309 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700310 __u32 pixel_format;
Tao Baod7db5942015-01-28 10:07:51 -0800311 __u32 flags;
312 __u32 handles[4];
313 __u32 pitches[4];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700314 __u32 offsets[4];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800315 __u64 modifier[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700316};
Christopher Ferris38062f92014-07-09 15:33:25 -0700317#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700318#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800319#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700320#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700321struct drm_mode_fb_dirty_cmd {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700322 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800323 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800324 __u32 color;
325 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700326 __u64 clips_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800327};
Ben Cheng655a7c02013-10-16 16:09:24 -0700328struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800329 __u32 connector_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700330 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800331};
Ben Cheng655a7c02013-10-16 16:09:24 -0700332#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700333#define DRM_MODE_CURSOR_MOVE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700334#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800335struct drm_mode_cursor {
Tao Baod7db5942015-01-28 10:07:51 -0800336 __u32 flags;
337 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700338 __s32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800339 __s32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800340 __u32 width;
341 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700342 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800343};
Christopher Ferris38062f92014-07-09 15:33:25 -0700344struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800345 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700346 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800347 __s32 x;
Tao Baod7db5942015-01-28 10:07:51 -0800348 __s32 y;
349 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700350 __u32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800351 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800352 __s32 hot_x;
353 __s32 hot_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700354};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800355struct drm_mode_crtc_lut {
Tao Baod7db5942015-01-28 10:07:51 -0800356 __u32 crtc_id;
357 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700358 __u64 red;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800359 __u64 green;
Tao Baod7db5942015-01-28 10:07:51 -0800360 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800361};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700362struct drm_color_ctm {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700363 __u64 matrix[9];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700364};
365struct drm_color_lut {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700366 __u16 red;
367 __u16 green;
368 __u16 blue;
369 __u16 reserved;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700370};
371#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800372#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800373#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800374#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
375#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
376#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
Christopher Ferris38062f92014-07-09 15:33:25 -0700377struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800378 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800379 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800380 __u32 flags;
381 __u32 reserved;
382 __u64 user_data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800383};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800384struct drm_mode_crtc_page_flip_target {
385 __u32 crtc_id;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800386 __u32 fb_id;
387 __u32 flags;
388 __u32 sequence;
389 __u64 user_data;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800390};
Ben Cheng655a7c02013-10-16 16:09:24 -0700391struct drm_mode_create_dumb {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700392 __u32 height;
393 __u32 width;
394 __u32 bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800395 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700396 __u32 handle;
397 __u32 pitch;
398 __u64 size;
399};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700400struct drm_mode_map_dumb {
401 __u32 handle;
402 __u32 pad;
403 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700404};
405struct drm_mode_destroy_dumb {
406 __u32 handle;
407};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700408#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
409#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
410#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
411#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700412struct drm_mode_atomic {
413 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800414 __u32 count_objs;
415 __u64 objs_ptr;
416 __u64 count_props_ptr;
417 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800418 __u64 prop_values_ptr;
419 __u64 reserved;
420 __u64 user_data;
421};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800422struct drm_format_modifier_blob {
423#define FORMAT_BLOB_CURRENT 1
424 __u32 version;
425 __u32 flags;
426 __u32 count_formats;
427 __u32 formats_offset;
428 __u32 count_modifiers;
429 __u32 modifiers_offset;
430};
431struct drm_format_modifier {
432 __u64 formats;
433 __u32 offset;
434 __u32 pad;
435 __u64 modifier;
436};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800437struct drm_mode_create_blob {
438 __u64 data;
439 __u32 length;
440 __u32 blob_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700441};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800442struct drm_mode_destroy_blob {
443 __u32 blob_id;
444};
Christopher Ferris934ec942018-01-31 15:29:16 -0800445struct drm_mode_create_lease {
446 __u64 object_ids;
447 __u32 object_count;
448 __u32 flags;
449 __u32 lessee_id;
450 __u32 fd;
451};
452struct drm_mode_list_lessees {
453 __u32 count_lessees;
454 __u32 pad;
455 __u64 lessees_ptr;
456};
457struct drm_mode_get_lease {
458 __u32 count_objects;
459 __u32 pad;
460 __u64 objects_ptr;
461};
462struct drm_mode_revoke_lease {
463 __u32 lessee_id;
464};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700465#ifdef __cplusplus
466#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700467#endif