blob: b91f1612865b11afc4b1f16861c9a90acf439477 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _DRM_MODE_H
20#define _DRM_MODE_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#define DRM_DISPLAY_INFO_LEN 32
Ben Cheng655a7c02013-10-16 16:09:24 -070025#define DRM_CONNECTOR_NAME_LEN 32
26#define DRM_DISPLAY_MODE_LEN 32
27#define DRM_PROP_NAME_LEN 32
Tao Baod7db5942015-01-28 10:07:51 -080028#define DRM_MODE_TYPE_BUILTIN (1 << 0)
Tao Baod7db5942015-01-28 10:07:51 -080029#define DRM_MODE_TYPE_CLOCK_C ((1 << 1) | DRM_MODE_TYPE_BUILTIN)
30#define DRM_MODE_TYPE_CRTC_C ((1 << 2) | DRM_MODE_TYPE_BUILTIN)
31#define DRM_MODE_TYPE_PREFERRED (1 << 3)
32#define DRM_MODE_TYPE_DEFAULT (1 << 4)
Tao Baod7db5942015-01-28 10:07:51 -080033#define DRM_MODE_TYPE_USERDEF (1 << 5)
34#define DRM_MODE_TYPE_DRIVER (1 << 6)
Christopher Ferris76a1d452018-06-27 14:12:29 -070035#define DRM_MODE_TYPE_ALL (DRM_MODE_TYPE_PREFERRED | DRM_MODE_TYPE_USERDEF | DRM_MODE_TYPE_DRIVER)
Tao Baod7db5942015-01-28 10:07:51 -080036#define DRM_MODE_FLAG_PHSYNC (1 << 0)
37#define DRM_MODE_FLAG_NHSYNC (1 << 1)
Tao Baod7db5942015-01-28 10:07:51 -080038#define DRM_MODE_FLAG_PVSYNC (1 << 2)
39#define DRM_MODE_FLAG_NVSYNC (1 << 3)
40#define DRM_MODE_FLAG_INTERLACE (1 << 4)
41#define DRM_MODE_FLAG_DBLSCAN (1 << 5)
Tao Baod7db5942015-01-28 10:07:51 -080042#define DRM_MODE_FLAG_CSYNC (1 << 6)
43#define DRM_MODE_FLAG_PCSYNC (1 << 7)
44#define DRM_MODE_FLAG_NCSYNC (1 << 8)
45#define DRM_MODE_FLAG_HSKEW (1 << 9)
Tao Baod7db5942015-01-28 10:07:51 -080046#define DRM_MODE_FLAG_BCAST (1 << 10)
47#define DRM_MODE_FLAG_PIXMUX (1 << 11)
48#define DRM_MODE_FLAG_DBLCLK (1 << 12)
49#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
Tao Baod7db5942015-01-28 10:07:51 -080050#define DRM_MODE_FLAG_3D_MASK (0x1f << 14)
51#define DRM_MODE_FLAG_3D_NONE (0 << 14)
52#define DRM_MODE_FLAG_3D_FRAME_PACKING (1 << 14)
53#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080054#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3 << 14)
55#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4 << 14)
56#define DRM_MODE_FLAG_3D_L_DEPTH (5 << 14)
57#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6 << 14)
Tao Baod7db5942015-01-28 10:07:51 -080058#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7 << 14)
59#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8 << 14)
Christopher Ferris82d75042015-01-26 10:57:07 -080060#define DRM_MODE_PICTURE_ASPECT_NONE 0
61#define DRM_MODE_PICTURE_ASPECT_4_3 1
Christopher Ferris82d75042015-01-26 10:57:07 -080062#define DRM_MODE_PICTURE_ASPECT_16_9 2
Christopher Ferris48af7cb2017-02-21 12:35:09 -080063#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F << 19)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080064#define DRM_MODE_FLAG_PIC_AR_NONE (DRM_MODE_PICTURE_ASPECT_NONE << 19)
65#define DRM_MODE_FLAG_PIC_AR_4_3 (DRM_MODE_PICTURE_ASPECT_4_3 << 19)
66#define DRM_MODE_FLAG_PIC_AR_16_9 (DRM_MODE_PICTURE_ASPECT_16_9 << 19)
Christopher Ferris76a1d452018-06-27 14:12:29 -070067#define DRM_MODE_FLAG_ALL (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLSCAN | DRM_MODE_FLAG_CSYNC | DRM_MODE_FLAG_PCSYNC | DRM_MODE_FLAG_NCSYNC | DRM_MODE_FLAG_HSKEW | DRM_MODE_FLAG_DBLCLK | DRM_MODE_FLAG_CLKDIV2 | DRM_MODE_FLAG_3D_MASK)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080068#define DRM_MODE_DPMS_ON 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080069#define DRM_MODE_DPMS_STANDBY 1
70#define DRM_MODE_DPMS_SUSPEND 2
71#define DRM_MODE_DPMS_OFF 3
72#define DRM_MODE_SCALE_NONE 0
Christopher Ferris48af7cb2017-02-21 12:35:09 -080073#define DRM_MODE_SCALE_FULLSCREEN 1
74#define DRM_MODE_SCALE_CENTER 2
75#define DRM_MODE_SCALE_ASPECT 3
Ben Cheng655a7c02013-10-16 16:09:24 -070076#define DRM_MODE_DITHERING_OFF 0
77#define DRM_MODE_DITHERING_ON 1
78#define DRM_MODE_DITHERING_AUTO 2
79#define DRM_MODE_DIRTY_OFF 0
Ben Cheng655a7c02013-10-16 16:09:24 -070080#define DRM_MODE_DIRTY_ON 1
81#define DRM_MODE_DIRTY_ANNOTATE 2
Christopher Ferris525ce912017-07-26 13:12:53 -070082#define DRM_MODE_LINK_STATUS_GOOD 0
83#define DRM_MODE_LINK_STATUS_BAD 1
Christopher Ferris1308ad32017-11-14 17:32:13 -080084#define DRM_MODE_ROTATE_0 (1 << 0)
85#define DRM_MODE_ROTATE_90 (1 << 1)
86#define DRM_MODE_ROTATE_180 (1 << 2)
87#define DRM_MODE_ROTATE_270 (1 << 3)
88#define DRM_MODE_ROTATE_MASK (DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270)
89#define DRM_MODE_REFLECT_X (1 << 4)
90#define DRM_MODE_REFLECT_Y (1 << 5)
91#define DRM_MODE_REFLECT_MASK (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y)
Christopher Ferris76a1d452018-06-27 14:12:29 -070092#define DRM_MODE_CONTENT_PROTECTION_UNDESIRED 0
93#define DRM_MODE_CONTENT_PROTECTION_DESIRED 1
94#define DRM_MODE_CONTENT_PROTECTION_ENABLED 2
Ben Cheng655a7c02013-10-16 16:09:24 -070095struct drm_mode_modeinfo {
Tao Baod7db5942015-01-28 10:07:51 -080096 __u32 clock;
Christopher Ferris05d08e92016-02-04 13:16:38 -080097 __u16 hdisplay;
98 __u16 hsync_start;
99 __u16 hsync_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800100 __u16 htotal;
101 __u16 hskew;
102 __u16 vdisplay;
103 __u16 vsync_start;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800104 __u16 vsync_end;
105 __u16 vtotal;
106 __u16 vscan;
Tao Baod7db5942015-01-28 10:07:51 -0800107 __u32 vrefresh;
Tao Baod7db5942015-01-28 10:07:51 -0800108 __u32 flags;
109 __u32 type;
110 char name[DRM_DISPLAY_MODE_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700111};
112struct drm_mode_card_res {
Tao Baod7db5942015-01-28 10:07:51 -0800113 __u64 fb_id_ptr;
114 __u64 crtc_id_ptr;
115 __u64 connector_id_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800116 __u64 encoder_id_ptr;
117 __u32 count_fbs;
118 __u32 count_crtcs;
119 __u32 count_connectors;
Tao Baod7db5942015-01-28 10:07:51 -0800120 __u32 count_encoders;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800121 __u32 min_width;
122 __u32 max_width;
123 __u32 min_height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800124 __u32 max_height;
125};
Ben Cheng655a7c02013-10-16 16:09:24 -0700126struct drm_mode_crtc {
Tao Baod7db5942015-01-28 10:07:51 -0800127 __u64 set_connectors_ptr;
128 __u32 count_connectors;
129 __u32 crtc_id;
Tao Baod7db5942015-01-28 10:07:51 -0800130 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131 __u32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800132 __u32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800133 __u32 gamma_size;
134 __u32 mode_valid;
Tao Baod7db5942015-01-28 10:07:51 -0800135 struct drm_mode_modeinfo mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700136};
Tao Baod7db5942015-01-28 10:07:51 -0800137#define DRM_MODE_PRESENT_TOP_FIELD (1 << 0)
138#define DRM_MODE_PRESENT_BOTTOM_FIELD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700139struct drm_mode_set_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800140 __u32 plane_id;
141 __u32 crtc_id;
142 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800143 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800144 __s32 crtc_x;
145 __s32 crtc_y;
146 __u32 crtc_w;
147 __u32 crtc_h;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800148 __u32 src_x;
149 __u32 src_y;
150 __u32 src_h;
151 __u32 src_w;
Ben Cheng655a7c02013-10-16 16:09:24 -0700152};
153struct drm_mode_get_plane {
Tao Baod7db5942015-01-28 10:07:51 -0800154 __u32 plane_id;
Tao Baod7db5942015-01-28 10:07:51 -0800155 __u32 crtc_id;
156 __u32 fb_id;
157 __u32 possible_crtcs;
158 __u32 gamma_size;
Tao Baod7db5942015-01-28 10:07:51 -0800159 __u32 count_format_types;
160 __u64 format_type_ptr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700161};
162struct drm_mode_get_plane_res {
Tao Baod7db5942015-01-28 10:07:51 -0800163 __u64 plane_id_ptr;
164 __u32 count_planes;
Ben Cheng655a7c02013-10-16 16:09:24 -0700165};
166#define DRM_MODE_ENCODER_NONE 0
167#define DRM_MODE_ENCODER_DAC 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700168#define DRM_MODE_ENCODER_TMDS 2
169#define DRM_MODE_ENCODER_LVDS 3
170#define DRM_MODE_ENCODER_TVDAC 4
171#define DRM_MODE_ENCODER_VIRTUAL 5
Christopher Ferris38062f92014-07-09 15:33:25 -0700172#define DRM_MODE_ENCODER_DSI 6
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700173#define DRM_MODE_ENCODER_DPMST 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700174#define DRM_MODE_ENCODER_DPI 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700175struct drm_mode_get_encoder {
Tao Baod7db5942015-01-28 10:07:51 -0800176 __u32 encoder_id;
177 __u32 encoder_type;
178 __u32 crtc_id;
179 __u32 possible_crtcs;
Tao Baod7db5942015-01-28 10:07:51 -0800180 __u32 possible_clones;
Ben Cheng655a7c02013-10-16 16:09:24 -0700181};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800182enum drm_mode_subconnector {
183 DRM_MODE_SUBCONNECTOR_Automatic = 0,
184 DRM_MODE_SUBCONNECTOR_Unknown = 0,
185 DRM_MODE_SUBCONNECTOR_DVID = 3,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800186 DRM_MODE_SUBCONNECTOR_DVIA = 4,
187 DRM_MODE_SUBCONNECTOR_Composite = 5,
188 DRM_MODE_SUBCONNECTOR_SVIDEO = 6,
189 DRM_MODE_SUBCONNECTOR_Component = 8,
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800190 DRM_MODE_SUBCONNECTOR_SCART = 9,
191};
Ben Cheng655a7c02013-10-16 16:09:24 -0700192#define DRM_MODE_CONNECTOR_Unknown 0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700193#define DRM_MODE_CONNECTOR_VGA 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700194#define DRM_MODE_CONNECTOR_DVII 2
195#define DRM_MODE_CONNECTOR_DVID 3
196#define DRM_MODE_CONNECTOR_DVIA 4
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700197#define DRM_MODE_CONNECTOR_Composite 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700198#define DRM_MODE_CONNECTOR_SVIDEO 6
199#define DRM_MODE_CONNECTOR_LVDS 7
200#define DRM_MODE_CONNECTOR_Component 8
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700201#define DRM_MODE_CONNECTOR_9PinDIN 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#define DRM_MODE_CONNECTOR_DisplayPort 10
203#define DRM_MODE_CONNECTOR_HDMIA 11
204#define DRM_MODE_CONNECTOR_HDMIB 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700205#define DRM_MODE_CONNECTOR_TV 13
Ben Cheng655a7c02013-10-16 16:09:24 -0700206#define DRM_MODE_CONNECTOR_eDP 14
207#define DRM_MODE_CONNECTOR_VIRTUAL 15
Christopher Ferris38062f92014-07-09 15:33:25 -0700208#define DRM_MODE_CONNECTOR_DSI 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700209#define DRM_MODE_CONNECTOR_DPI 17
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700210struct drm_mode_get_connector {
Tao Baod7db5942015-01-28 10:07:51 -0800211 __u64 encoders_ptr;
212 __u64 modes_ptr;
213 __u64 props_ptr;
214 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800215 __u32 count_modes;
216 __u32 count_props;
217 __u32 count_encoders;
218 __u32 encoder_id;
Tao Baod7db5942015-01-28 10:07:51 -0800219 __u32 connector_id;
220 __u32 connector_type;
221 __u32 connector_type_id;
222 __u32 connection;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800223 __u32 mm_width;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800224 __u32 mm_height;
Tao Baod7db5942015-01-28 10:07:51 -0800225 __u32 subpixel;
226 __u32 pad;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700227};
Tao Baod7db5942015-01-28 10:07:51 -0800228#define DRM_MODE_PROP_PENDING (1 << 0)
229#define DRM_MODE_PROP_RANGE (1 << 1)
230#define DRM_MODE_PROP_IMMUTABLE (1 << 2)
231#define DRM_MODE_PROP_ENUM (1 << 3)
Tao Baod7db5942015-01-28 10:07:51 -0800232#define DRM_MODE_PROP_BLOB (1 << 4)
233#define DRM_MODE_PROP_BITMASK (1 << 5)
234#define DRM_MODE_PROP_LEGACY_TYPE (DRM_MODE_PROP_RANGE | DRM_MODE_PROP_ENUM | DRM_MODE_PROP_BLOB | DRM_MODE_PROP_BITMASK)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700235#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
236#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
237#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
238#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800239#define DRM_MODE_PROP_ATOMIC 0x80000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800240struct drm_mode_property_enum {
Tao Baod7db5942015-01-28 10:07:51 -0800241 __u64 value;
242 char name[DRM_PROP_NAME_LEN];
Ben Cheng655a7c02013-10-16 16:09:24 -0700243};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800244struct drm_mode_get_property {
Tao Baod7db5942015-01-28 10:07:51 -0800245 __u64 values_ptr;
246 __u64 enum_blob_ptr;
247 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800248 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800249 char name[DRM_PROP_NAME_LEN];
250 __u32 count_values;
251 __u32 count_enum_blobs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800252};
Ben Cheng655a7c02013-10-16 16:09:24 -0700253struct drm_mode_connector_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800254 __u64 value;
255 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800256 __u32 connector_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700257};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700258#define DRM_MODE_OBJECT_CRTC 0xcccccccc
259#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700260#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
261#define DRM_MODE_OBJECT_MODE 0xdededede
262#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
263#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
Christopher Ferris106b3a82016-08-24 12:15:38 -0700264#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
265#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
266#define DRM_MODE_OBJECT_ANY 0
267struct drm_mode_obj_get_properties {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700268 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800269 __u64 prop_values_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800270 __u32 count_props;
271 __u32 obj_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700272 __u32 obj_type;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800273};
Ben Cheng655a7c02013-10-16 16:09:24 -0700274struct drm_mode_obj_set_property {
Tao Baod7db5942015-01-28 10:07:51 -0800275 __u64 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700276 __u32 prop_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800277 __u32 obj_id;
Tao Baod7db5942015-01-28 10:07:51 -0800278 __u32 obj_type;
Christopher Ferris38062f92014-07-09 15:33:25 -0700279};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700280struct drm_mode_get_blob {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800281 __u32 blob_id;
Tao Baod7db5942015-01-28 10:07:51 -0800282 __u32 length;
283 __u64 data;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700284};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800285struct drm_mode_fb_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800286 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800287 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700288 __u32 height;
Tao Baod7db5942015-01-28 10:07:51 -0800289 __u32 pitch;
290 __u32 bpp;
Tao Baod7db5942015-01-28 10:07:51 -0800291 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700292 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700293};
Tao Baod7db5942015-01-28 10:07:51 -0800294#define DRM_MODE_FB_INTERLACED (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800295#define DRM_MODE_FB_MODIFIERS (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700296struct drm_mode_fb_cmd2 {
Tao Baod7db5942015-01-28 10:07:51 -0800297 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800298 __u32 width;
299 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700300 __u32 pixel_format;
Tao Baod7db5942015-01-28 10:07:51 -0800301 __u32 flags;
302 __u32 handles[4];
303 __u32 pitches[4];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700304 __u32 offsets[4];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800305 __u64 modifier[4];
Ben Cheng655a7c02013-10-16 16:09:24 -0700306};
Christopher Ferris38062f92014-07-09 15:33:25 -0700307#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700308#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
Christopher Ferris05d08e92016-02-04 13:16:38 -0800309#define DRM_MODE_FB_DIRTY_FLAGS 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700310#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
Christopher Ferris38062f92014-07-09 15:33:25 -0700311struct drm_mode_fb_dirty_cmd {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700312 __u32 fb_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800313 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800314 __u32 color;
315 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700316 __u64 clips_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800317};
Ben Cheng655a7c02013-10-16 16:09:24 -0700318struct drm_mode_mode_cmd {
Tao Baod7db5942015-01-28 10:07:51 -0800319 __u32 connector_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700320 struct drm_mode_modeinfo mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800321};
Ben Cheng655a7c02013-10-16 16:09:24 -0700322#define DRM_MODE_CURSOR_BO 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700323#define DRM_MODE_CURSOR_MOVE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -0700324#define DRM_MODE_CURSOR_FLAGS 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800325struct drm_mode_cursor {
Tao Baod7db5942015-01-28 10:07:51 -0800326 __u32 flags;
327 __u32 crtc_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700328 __s32 x;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800329 __s32 y;
Tao Baod7db5942015-01-28 10:07:51 -0800330 __u32 width;
331 __u32 height;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700332 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800333};
Christopher Ferris38062f92014-07-09 15:33:25 -0700334struct drm_mode_cursor2 {
Tao Baod7db5942015-01-28 10:07:51 -0800335 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700336 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800337 __s32 x;
Tao Baod7db5942015-01-28 10:07:51 -0800338 __s32 y;
339 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700340 __u32 height;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800341 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800342 __s32 hot_x;
343 __s32 hot_y;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700344};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800345struct drm_mode_crtc_lut {
Tao Baod7db5942015-01-28 10:07:51 -0800346 __u32 crtc_id;
347 __u32 gamma_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700348 __u64 red;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800349 __u64 green;
Tao Baod7db5942015-01-28 10:07:51 -0800350 __u64 blue;
Elliott Hughes8cb52b02013-11-21 13:43:23 -0800351};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700352struct drm_color_ctm {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700353 __u64 matrix[9];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700354};
355struct drm_color_lut {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700356 __u16 red;
357 __u16 green;
358 __u16 blue;
359 __u16 reserved;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700360};
361#define DRM_MODE_PAGE_FLIP_EVENT 0x01
Christopher Ferris05d08e92016-02-04 13:16:38 -0800362#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800363#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800364#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
365#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
366#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_PAGE_FLIP_TARGET)
Christopher Ferris38062f92014-07-09 15:33:25 -0700367struct drm_mode_crtc_page_flip {
Tao Baod7db5942015-01-28 10:07:51 -0800368 __u32 crtc_id;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800369 __u32 fb_id;
Tao Baod7db5942015-01-28 10:07:51 -0800370 __u32 flags;
371 __u32 reserved;
372 __u64 user_data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800373};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800374struct drm_mode_crtc_page_flip_target {
375 __u32 crtc_id;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800376 __u32 fb_id;
377 __u32 flags;
378 __u32 sequence;
379 __u64 user_data;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800380};
Ben Cheng655a7c02013-10-16 16:09:24 -0700381struct drm_mode_create_dumb {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700382 __u32 height;
383 __u32 width;
384 __u32 bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800385 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700386 __u32 handle;
387 __u32 pitch;
388 __u64 size;
389};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700390struct drm_mode_map_dumb {
391 __u32 handle;
392 __u32 pad;
393 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700394};
395struct drm_mode_destroy_dumb {
396 __u32 handle;
397};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700398#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
399#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
400#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
401#define DRM_MODE_ATOMIC_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | DRM_MODE_PAGE_FLIP_ASYNC | DRM_MODE_ATOMIC_TEST_ONLY | DRM_MODE_ATOMIC_NONBLOCK | DRM_MODE_ATOMIC_ALLOW_MODESET)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700402struct drm_mode_atomic {
403 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800404 __u32 count_objs;
405 __u64 objs_ptr;
406 __u64 count_props_ptr;
407 __u64 props_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800408 __u64 prop_values_ptr;
409 __u64 reserved;
410 __u64 user_data;
411};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800412struct drm_format_modifier_blob {
413#define FORMAT_BLOB_CURRENT 1
414 __u32 version;
415 __u32 flags;
416 __u32 count_formats;
417 __u32 formats_offset;
418 __u32 count_modifiers;
419 __u32 modifiers_offset;
420};
421struct drm_format_modifier {
422 __u64 formats;
423 __u32 offset;
424 __u32 pad;
425 __u64 modifier;
426};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800427struct drm_mode_create_blob {
428 __u64 data;
429 __u32 length;
430 __u32 blob_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700431};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800432struct drm_mode_destroy_blob {
433 __u32 blob_id;
434};
Christopher Ferris934ec942018-01-31 15:29:16 -0800435struct drm_mode_create_lease {
436 __u64 object_ids;
437 __u32 object_count;
438 __u32 flags;
439 __u32 lessee_id;
440 __u32 fd;
441};
442struct drm_mode_list_lessees {
443 __u32 count_lessees;
444 __u32 pad;
445 __u64 lessees_ptr;
446};
447struct drm_mode_get_lease {
448 __u32 count_objects;
449 __u32 pad;
450 __u64 objects_ptr;
451};
452struct drm_mode_revoke_lease {
453 __u32 lessee_id;
454};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700455#ifdef __cplusplus
456#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700457#endif