blob: 6f55fc62d0af84ba47e9128d763ac9f91c4d76cc [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040021
Sean Paule0c4c3d2015-01-20 16:56:04 -050022#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040023#include <fcntl.h>
Sean Paul5ad302c2015-05-11 10:43:31 -070024#include <list>
Sean Paulef8f1f92015-04-29 16:05:23 -040025#include <pthread.h>
Dan Albertc5255b32015-05-07 23:42:54 -070026#include <stdlib.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050027#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050028#include <sys/resource.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050029#include <xf86drm.h>
30#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050031
Sean Paulef8f1f92015-04-29 16:05:23 -040032#include <cutils/log.h>
33#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050034#include <hardware/hardware.h>
35#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050036#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040037#include <sync/sync.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050038
39#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
40
Sean Paule0c4c3d2015-01-20 16:56:04 -050041#define MAX_NUM_DISPLAYS 3
42#define UM_PER_INCH 25400
43
Sean Paul6a55e9f2015-04-30 15:31:06 -040044namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050045
Sean Paul9aa5ad32015-01-22 15:47:54 -050046struct hwc_worker {
Sean Paulef8f1f92015-04-29 16:05:23 -040047 pthread_t thread;
48 pthread_mutex_t lock;
49 pthread_cond_t cond;
50 bool exit;
Sean Paul9aa5ad32015-01-22 15:47:54 -050051};
52
Sean Paule0c4c3d2015-01-20 16:56:04 -050053struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -040054 struct hwc_context_t *ctx;
55 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -050056
Sean Paul6a55e9f2015-04-30 15:31:06 -040057 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -050058
Sean Paulef8f1f92015-04-29 16:05:23 -040059 struct hwc_worker set_worker;
Sean Paul9aa5ad32015-01-22 15:47:54 -050060
Sean Paulef8f1f92015-04-29 16:05:23 -040061 std::list<struct hwc_drm_bo> buf_queue;
62 struct hwc_drm_bo front;
63 pthread_mutex_t flip_lock;
64 pthread_cond_t flip_cond;
Sean Paulf1dc1912015-01-24 01:34:31 -050065
Sean Paulef8f1f92015-04-29 16:05:23 -040066 int timeline_fd;
67 unsigned timeline_next;
Sean Pauleb9e75c2015-01-25 23:31:30 -050068
Sean Paulef8f1f92015-04-29 16:05:23 -040069 bool enable_vsync_events;
70 unsigned int vsync_sequence;
Sean Paule0c4c3d2015-01-20 16:56:04 -050071};
72
73struct hwc_context_t {
Sean Paulef8f1f92015-04-29 16:05:23 -040074 hwc_composer_device_1_t device;
Sean Paule0c4c3d2015-01-20 16:56:04 -050075
Sean Paulef8f1f92015-04-29 16:05:23 -040076 hwc_procs_t const *procs;
77 struct hwc_import_context *import_ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -050078
Sean Paulef8f1f92015-04-29 16:05:23 -040079 struct hwc_drm_display displays[MAX_NUM_DISPLAYS];
80 int num_displays;
Sean Paul814bddb2015-03-03 17:46:19 -050081
Sean Paulef8f1f92015-04-29 16:05:23 -040082 struct hwc_worker event_worker;
Sean Paul6a55e9f2015-04-30 15:31:06 -040083
84 DrmResources drm;
Sean Paule0c4c3d2015-01-20 16:56:04 -050085};
86
87static int hwc_get_drm_display(struct hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -040088 struct hwc_drm_display **hd) {
89 if (display >= MAX_NUM_DISPLAYS) {
90 ALOGE("Requested display is out-of-bounds %d %d", display,
91 MAX_NUM_DISPLAYS);
92 return -EINVAL;
93 }
94 *hd = &ctx->displays[display];
95 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -050096}
97
Sean Paulef8f1f92015-04-29 16:05:23 -040098static int hwc_prepare_layer(hwc_layer_1_t *layer) {
99 /* TODO: We can't handle background right now, defer to sufaceFlinger */
100 if (layer->compositionType == HWC_BACKGROUND) {
101 layer->compositionType = HWC_FRAMEBUFFER;
102 ALOGV("Can't handle background layers yet");
Sean Paule0c4c3d2015-01-20 16:56:04 -0500103
Sean Paulef8f1f92015-04-29 16:05:23 -0400104 /* TODO: Support sideband compositions */
105 } else if (layer->compositionType == HWC_SIDEBAND) {
106 layer->compositionType = HWC_FRAMEBUFFER;
107 ALOGV("Can't handle sideband content yet");
108 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500109
Sean Paulef8f1f92015-04-29 16:05:23 -0400110 layer->hints = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500111
Sean Paulef8f1f92015-04-29 16:05:23 -0400112 /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */
113 if (layer->flags & HWC_IS_CURSOR_LAYER) {
114 ALOGV("Can't handle async cursors yet");
115 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500116
Sean Paulef8f1f92015-04-29 16:05:23 -0400117 /* TODO: Handle transformations */
118 if (layer->transform) {
119 ALOGV("Can't handle transformations yet");
120 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500121
Sean Paulef8f1f92015-04-29 16:05:23 -0400122 /* TODO: Handle blending & plane alpha*/
123 if (layer->blending == HWC_BLENDING_PREMULT ||
124 layer->blending == HWC_BLENDING_COVERAGE) {
125 ALOGV("Can't handle blending yet");
126 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500127
Sean Paulef8f1f92015-04-29 16:05:23 -0400128 /* TODO: Handle cropping & scaling */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500129
Sean Paulef8f1f92015-04-29 16:05:23 -0400130 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500131}
132
Sean Paulef8f1f92015-04-29 16:05:23 -0400133static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays,
134 hwc_display_contents_1_t **display_contents) {
135 /* TODO: Check flags for HWC_GEOMETRY_CHANGED */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500136
Sean Paulef8f1f92015-04-29 16:05:23 -0400137 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
138 if (!display_contents[i])
139 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500140
Sean Paulef8f1f92015-04-29 16:05:23 -0400141 for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) {
142 int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]);
143 if (ret) {
144 ALOGE("Failed to prepare layer %d:%d", j, i);
145 return ret;
146 }
147 }
148 }
Sean Pauldffca952015-02-04 10:19:55 -0800149
Sean Paulef8f1f92015-04-29 16:05:23 -0400150 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500151}
152
Sean Paulef8f1f92015-04-29 16:05:23 -0400153static int hwc_queue_vblank_event(struct hwc_drm_display *hd) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400154 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
155 if (!crtc) {
156 ALOGE("Failed to get crtc for display");
157 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400158 }
Sean Paul814bddb2015-03-03 17:46:19 -0500159
Sean Paulef8f1f92015-04-29 16:05:23 -0400160 drmVBlank vblank;
161 memset(&vblank, 0, sizeof(vblank));
Sean Paul814bddb2015-03-03 17:46:19 -0500162
Sean Paul6a55e9f2015-04-30 15:31:06 -0400163 uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT);
Sean Paulef8f1f92015-04-29 16:05:23 -0400164 vblank.request.type = (drmVBlankSeqType)(
165 DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT |
166 (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK));
167 vblank.request.signal = (unsigned long)hd;
168 vblank.request.sequence = hd->vsync_sequence + 1;
Sean Paul814bddb2015-03-03 17:46:19 -0500169
Sean Paul6a55e9f2015-04-30 15:31:06 -0400170 int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank);
Sean Paulef8f1f92015-04-29 16:05:23 -0400171 if (ret) {
172 ALOGE("Failed to wait for vblank %d", ret);
173 return ret;
174 }
Sean Paul814bddb2015-03-03 17:46:19 -0500175
Sean Paulef8f1f92015-04-29 16:05:23 -0400176 return 0;
Sean Paul814bddb2015-03-03 17:46:19 -0500177}
178
179static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence,
Sean Paulef8f1f92015-04-29 16:05:23 -0400180 unsigned int tv_sec, unsigned int tv_usec,
181 void *user_data) {
182 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500183
Sean Paulef8f1f92015-04-29 16:05:23 -0400184 if (!hd->enable_vsync_events || !hd->ctx->procs->vsync)
185 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500186
Sean Paulef8f1f92015-04-29 16:05:23 -0400187 /*
188 * Discard duplicate vsync (can happen when enabling vsync events while
189 * already processing vsyncs).
190 */
191 if (sequence <= hd->vsync_sequence)
192 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500193
Sean Paulef8f1f92015-04-29 16:05:23 -0400194 hd->vsync_sequence = sequence;
195 int ret = hwc_queue_vblank_event(hd);
196 if (ret)
197 ALOGE("Failed to queue vblank event ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500198
Sean Paulef8f1f92015-04-29 16:05:23 -0400199 int64_t timestamp =
200 (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000;
201 hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp);
Sean Paul814bddb2015-03-03 17:46:19 -0500202}
203
204static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */,
Sean Paulef8f1f92015-04-29 16:05:23 -0400205 unsigned int /* tv_sec */,
206 unsigned int /* tv_usec */,
207 void *user_data) {
208 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500209
Sean Paulef8f1f92015-04-29 16:05:23 -0400210 int ret = pthread_mutex_lock(&hd->flip_lock);
211 if (ret) {
212 ALOGE("Failed to lock flip lock ret=%d", ret);
213 return;
214 }
Sean Paul814bddb2015-03-03 17:46:19 -0500215
Sean Paulef8f1f92015-04-29 16:05:23 -0400216 ret = pthread_cond_signal(&hd->flip_cond);
217 if (ret)
218 ALOGE("Failed to signal flip condition ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500219
Sean Paulef8f1f92015-04-29 16:05:23 -0400220 ret = pthread_mutex_unlock(&hd->flip_lock);
221 if (ret) {
222 ALOGE("Failed to unlock flip lock ret=%d", ret);
223 return;
224 }
Sean Paul814bddb2015-03-03 17:46:19 -0500225}
226
Sean Paulef8f1f92015-04-29 16:05:23 -0400227static void *hwc_event_worker(void *arg) {
228 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul814bddb2015-03-03 17:46:19 -0500229
Sean Paulef8f1f92015-04-29 16:05:23 -0400230 struct hwc_context_t *ctx = (struct hwc_context_t *)arg;
231 do {
232 fd_set fds;
233 FD_ZERO(&fds);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400234 FD_SET(ctx->drm.fd(), &fds);
Sean Paul814bddb2015-03-03 17:46:19 -0500235
Sean Paulef8f1f92015-04-29 16:05:23 -0400236 drmEventContext event_context;
237 event_context.version = DRM_EVENT_CONTEXT_VERSION;
238 event_context.page_flip_handler = hwc_flip_event_handler;
239 event_context.vblank_handler = hwc_vblank_event_handler;
Sean Paul814bddb2015-03-03 17:46:19 -0500240
Sean Paulef8f1f92015-04-29 16:05:23 -0400241 int ret;
242 do {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400243 ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400244 } while (ret == -1 && errno == EINTR);
Sean Paul814bddb2015-03-03 17:46:19 -0500245
Sean Paulef8f1f92015-04-29 16:05:23 -0400246 if (ret != 1) {
247 ALOGE("Failed waiting for drm event\n");
248 continue;
249 }
Sean Paul814bddb2015-03-03 17:46:19 -0500250
Sean Paul6a55e9f2015-04-30 15:31:06 -0400251 drmHandleEvent(ctx->drm.fd(), &event_context);
Sean Paulef8f1f92015-04-29 16:05:23 -0400252 } while (true);
Sean Paul814bddb2015-03-03 17:46:19 -0500253
Sean Paulef8f1f92015-04-29 16:05:23 -0400254 return NULL;
Sean Paul814bddb2015-03-03 17:46:19 -0500255}
256
Sean Paulef8f1f92015-04-29 16:05:23 -0400257static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) {
258 return a->clock == b->clock && a->hdisplay == b->hdisplay &&
259 a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end &&
260 a->htotal == b->htotal && a->hskew == b->hskew &&
261 a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start &&
262 a->vsync_end == b->vsync_end && a->vtotal == b->vtotal &&
263 a->vscan == b->vscan && a->vrefresh == b->vrefresh &&
264 a->flags == b->flags && a->type == b->type &&
265 !strcmp(a->name, b->name);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500266}
267
Sean Paul6a55e9f2015-04-30 15:31:06 -0400268static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) {
269 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400270 if (!crtc) {
271 ALOGE("Failed to get crtc for display %d", hd->display);
272 return -ENODEV;
273 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800274
Sean Paul6a55e9f2015-04-30 15:31:06 -0400275 DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display);
276 if (!connector) {
277 ALOGE("Failed to get connector for display %d", hd->display);
278 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400279 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400280
281 int ret;
282 if (crtc->requires_modeset()) {
283 drmModeModeInfo drm_mode;
284 connector->active_mode().ToModeModeInfo(&drm_mode);
285 uint32_t connector_id = connector->id();
286 ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0,
287 &connector_id, 1, &drm_mode);
Sean Paulef8f1f92015-04-29 16:05:23 -0400288 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400289 ALOGE("Modeset failed for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400290 return ret;
291 }
292 return 0;
293 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500294
Sean Paul6a55e9f2015-04-30 15:31:06 -0400295 ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id,
Sean Paulef8f1f92015-04-29 16:05:23 -0400296 DRM_MODE_PAGE_FLIP_EVENT, hd);
297 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400298 ALOGE("Failed to flip buffer for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400299 return ret;
300 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500301
Sean Paulef8f1f92015-04-29 16:05:23 -0400302 ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock);
303 if (ret) {
304 ALOGE("Failed to wait on condition %d", ret);
305 return ret;
306 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500307
Sean Paulef8f1f92015-04-29 16:05:23 -0400308 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500309}
310
Sean Paul3bc48e82015-01-23 01:41:13 -0500311static int hwc_wait_and_set(struct hwc_drm_display *hd,
Sean Paulef8f1f92015-04-29 16:05:23 -0400312 struct hwc_drm_bo *buf) {
313 int ret;
314 if (buf->acquire_fence_fd >= 0) {
315 ret = sync_wait(buf->acquire_fence_fd, -1);
316 close(buf->acquire_fence_fd);
317 buf->acquire_fence_fd = -1;
318 if (ret) {
319 ALOGE("Failed to wait for acquire %d", ret);
320 return ret;
321 }
322 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500323
Sean Paulef8f1f92015-04-29 16:05:23 -0400324 ret = hwc_flip(hd, buf);
325 if (ret) {
326 ALOGE("Failed to perform flip\n");
327 return ret;
328 }
Lauri Peltonen132e0102015-02-12 13:54:33 +0200329
Sean Paul6a55e9f2015-04-30 15:31:06 -0400330 if (hwc_import_bo_release(hd->ctx->drm.fd(), hd->ctx->import_ctx,
331 &hd->front)) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400332 struct drm_gem_close args;
333 memset(&args, 0, sizeof(args));
334 for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) {
335 if (!hd->front.gem_handles[i])
336 continue;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500337
Sean Paulef8f1f92015-04-29 16:05:23 -0400338 ret = pthread_mutex_lock(&hd->set_worker.lock);
339 if (ret) {
340 ALOGE("Failed to lock set lock in wait_and_set() %d", ret);
341 continue;
342 }
Allen Martin3d3f70a2015-02-21 21:20:17 -0800343
Sean Paulef8f1f92015-04-29 16:05:23 -0400344 /* check for duplicate handle in buf_queue */
345 bool found = false;
346 for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin();
347 bi != hd->buf_queue.end(); ++bi)
348 for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j)
349 if (hd->front.gem_handles[i] == bi->gem_handles[j])
350 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800351
Sean Paulef8f1f92015-04-29 16:05:23 -0400352 for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j)
353 if (hd->front.gem_handles[i] == buf->gem_handles[j])
354 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800355
Sean Paulef8f1f92015-04-29 16:05:23 -0400356 if (!found) {
357 args.handle = hd->front.gem_handles[i];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400358 drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args);
Sean Paulef8f1f92015-04-29 16:05:23 -0400359 }
360 if (pthread_mutex_unlock(&hd->set_worker.lock))
361 ALOGE("Failed to unlock set lock in wait_and_set() %d", ret);
362 }
363 }
Lauri Peltonen77d6d7a2015-02-23 20:44:16 +0200364
Sean Paulef8f1f92015-04-29 16:05:23 -0400365 hd->front = *buf;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800366
Sean Paulef8f1f92015-04-29 16:05:23 -0400367 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500368}
369
Sean Paulef8f1f92015-04-29 16:05:23 -0400370static void *hwc_set_worker(void *arg) {
371 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500372
Sean Paulef8f1f92015-04-29 16:05:23 -0400373 struct hwc_drm_display *hd = (struct hwc_drm_display *)arg;
374 int ret = pthread_mutex_lock(&hd->flip_lock);
375 if (ret) {
376 ALOGE("Failed to lock flip lock ret=%d", ret);
377 return NULL;
378 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500379
Sean Paulef8f1f92015-04-29 16:05:23 -0400380 do {
381 ret = pthread_mutex_lock(&hd->set_worker.lock);
382 if (ret) {
383 ALOGE("Failed to lock set lock %d", ret);
384 return NULL;
385 }
Sean Paul814bddb2015-03-03 17:46:19 -0500386
Sean Paulef8f1f92015-04-29 16:05:23 -0400387 if (hd->set_worker.exit)
388 break;
Sean Paul3bc48e82015-01-23 01:41:13 -0500389
Sean Paulef8f1f92015-04-29 16:05:23 -0400390 if (hd->buf_queue.empty()) {
391 ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock);
392 if (ret) {
393 ALOGE("Failed to wait on condition %d", ret);
394 break;
395 }
396 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500397
Sean Paulef8f1f92015-04-29 16:05:23 -0400398 struct hwc_drm_bo buf;
399 buf = hd->buf_queue.front();
400 hd->buf_queue.pop_front();
Sean Paul3bc48e82015-01-23 01:41:13 -0500401
Sean Paulef8f1f92015-04-29 16:05:23 -0400402 ret = pthread_mutex_unlock(&hd->set_worker.lock);
403 if (ret) {
404 ALOGE("Failed to unlock set lock %d", ret);
405 return NULL;
406 }
Sean Paul3bc48e82015-01-23 01:41:13 -0500407
Sean Paulef8f1f92015-04-29 16:05:23 -0400408 ret = hwc_wait_and_set(hd, &buf);
409 if (ret)
410 ALOGE("Failed to wait and set %d", ret);
Sean Paul3bc48e82015-01-23 01:41:13 -0500411
Sean Paulef8f1f92015-04-29 16:05:23 -0400412 ret = sw_sync_timeline_inc(hd->timeline_fd, 1);
413 if (ret)
414 ALOGE("Failed to increment sync timeline %d", ret);
415 } while (true);
Sean Paul3bc48e82015-01-23 01:41:13 -0500416
Sean Paulef8f1f92015-04-29 16:05:23 -0400417 ret = pthread_mutex_unlock(&hd->set_worker.lock);
418 if (ret)
419 ALOGE("Failed to unlock set lock while exiting %d", ret);
Sean Paulf1dc1912015-01-24 01:34:31 -0500420
Sean Paulef8f1f92015-04-29 16:05:23 -0400421 ret = pthread_mutex_unlock(&hd->flip_lock);
422 if (ret)
423 ALOGE("Failed to unlock flip lock ret=%d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500424
Sean Paulef8f1f92015-04-29 16:05:23 -0400425 return NULL;
426}
Sean Paul9aa5ad32015-01-22 15:47:54 -0500427
Sean Paulef8f1f92015-04-29 16:05:23 -0400428static void hwc_close_fences(hwc_display_contents_1_t *display_contents) {
429 for (int i = 0; i < (int)display_contents->numHwLayers; ++i) {
430 hwc_layer_1_t *layer = &display_contents->hwLayers[i];
431 if (layer->acquireFenceFd >= 0) {
432 close(layer->acquireFenceFd);
433 layer->acquireFenceFd = -1;
434 }
435 }
436 if (display_contents->outbufAcquireFenceFd >= 0) {
437 close(display_contents->outbufAcquireFenceFd);
438 display_contents->outbufAcquireFenceFd = -1;
439 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500440}
441
Sean Paule0c4c3d2015-01-20 16:56:04 -0500442static int hwc_set_display(hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -0400443 hwc_display_contents_1_t *display_contents) {
444 struct hwc_drm_display *hd = NULL;
445 int ret = hwc_get_drm_display(ctx, display, &hd);
446 if (ret) {
447 hwc_close_fences(display_contents);
448 return ret;
449 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500450
Sean Paul6a55e9f2015-04-30 15:31:06 -0400451 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display);
452 if (!crtc) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400453 ALOGE("There is no active crtc for display %d", display);
454 hwc_close_fences(display_contents);
455 return -ENOENT;
456 }
Sean Paul9b1bb842015-01-23 01:11:58 -0500457
Sean Paulef8f1f92015-04-29 16:05:23 -0400458 /*
459 * TODO: We can only support one hw layer atm, so choose either the
460 * first one or the framebuffer target.
461 */
462 hwc_layer_1_t *layer = NULL;
463 if (!display_contents->numHwLayers) {
464 return 0;
465 } else if (display_contents->numHwLayers == 1) {
466 layer = &display_contents->hwLayers[0];
467 } else {
468 int i;
469 for (i = 0; i < (int)display_contents->numHwLayers; ++i) {
470 layer = &display_contents->hwLayers[i];
471 if (layer->compositionType == HWC_FRAMEBUFFER_TARGET)
472 break;
473 }
474 if (i == (int)display_contents->numHwLayers) {
475 ALOGE("Could not find a suitable layer for display %d", display);
476 }
477 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500478
Sean Paulef8f1f92015-04-29 16:05:23 -0400479 ret = pthread_mutex_lock(&hd->set_worker.lock);
480 if (ret) {
481 ALOGE("Failed to lock set lock in set() %d", ret);
482 hwc_close_fences(display_contents);
483 return ret;
484 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500485
Sean Paulef8f1f92015-04-29 16:05:23 -0400486 struct hwc_drm_bo buf;
487 memset(&buf, 0, sizeof(buf));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400488 ret =
489 hwc_import_bo_create(ctx->drm.fd(), ctx->import_ctx, layer->handle, &buf);
Sean Paulef8f1f92015-04-29 16:05:23 -0400490 if (ret) {
491 ALOGE("Failed to import handle to drm bo %d", ret);
492 hwc_close_fences(display_contents);
493 return ret;
494 }
495 buf.acquire_fence_fd = layer->acquireFenceFd;
496 layer->acquireFenceFd = -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500497
Sean Paulef8f1f92015-04-29 16:05:23 -0400498 /*
499 * TODO: Retire and release can use the same sync point here b/c hwc is
500 * restricted to one layer. Once that is no longer true, this will need
501 * to change
502 */
503 ++hd->timeline_next;
504 display_contents->retireFenceFd = sw_sync_fence_create(
505 hd->timeline_fd, "drm_hwc_retire", hd->timeline_next);
506 layer->releaseFenceFd = sw_sync_fence_create(
507 hd->timeline_fd, "drm_hwc_release", hd->timeline_next);
508 hd->buf_queue.push_back(buf);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800509
Sean Paulef8f1f92015-04-29 16:05:23 -0400510 ret = pthread_cond_signal(&hd->set_worker.cond);
511 if (ret)
512 ALOGE("Failed to signal set worker %d", ret);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800513
Sean Paulef8f1f92015-04-29 16:05:23 -0400514 if (pthread_mutex_unlock(&hd->set_worker.lock))
515 ALOGE("Failed to unlock set lock in set()");
Sean Paul3bc48e82015-01-23 01:41:13 -0500516
Sean Paulef8f1f92015-04-29 16:05:23 -0400517 hwc_close_fences(display_contents);
518 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500519}
520
521static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400522 hwc_display_contents_1_t **display_contents) {
523 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500524
Sean Paulef8f1f92015-04-29 16:05:23 -0400525 int ret = 0;
526 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
527 if (display_contents[i])
528 ret = hwc_set_display(ctx, i, display_contents[i]);
529 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500530
Sean Paulef8f1f92015-04-29 16:05:23 -0400531 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500532}
533
Sean Paulef8f1f92015-04-29 16:05:23 -0400534static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
535 int event, int enabled) {
536 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
537 struct hwc_drm_display *hd = NULL;
538 int ret = hwc_get_drm_display(ctx, display, &hd);
539 if (ret)
540 return ret;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500541
Sean Paulef8f1f92015-04-29 16:05:23 -0400542 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
543 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500544
Sean Paul6a55e9f2015-04-30 15:31:06 -0400545 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display);
546 if (!crtc) {
547 ALOGD("Can't service events for display %d, no crtc", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400548 return -EINVAL;
549 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500550
Sean Paulef8f1f92015-04-29 16:05:23 -0400551 hd->enable_vsync_events = !!enabled;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500552
Sean Paulef8f1f92015-04-29 16:05:23 -0400553 if (!hd->enable_vsync_events)
554 return 0;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500555
Sean Paulef8f1f92015-04-29 16:05:23 -0400556 /*
557 * Note that it's possible that the event worker is already waiting for
558 * a vsync, and this will be a duplicate request. In that event, we'll
559 * end up firing the event handler twice, and it will discard the second
560 * event. Not ideal, but not worth introducing a bunch of additional
561 * logic/locks/state for.
562 */
563 ret = hwc_queue_vblank_event(hd);
564 if (ret) {
565 ALOGE("Failed to queue vblank event ret=%d", ret);
566 return ret;
567 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500568
Sean Paulef8f1f92015-04-29 16:05:23 -0400569 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500570}
571
Sean Paulef8f1f92015-04-29 16:05:23 -0400572static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
573 int mode) {
574 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500575
Sean Paul6a55e9f2015-04-30 15:31:06 -0400576 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400577 switch (mode) {
578 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400579 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400580 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500581
Sean Paulef8f1f92015-04-29 16:05:23 -0400582 /* We can't support dozing right now, so go full on */
583 case HWC_POWER_MODE_DOZE:
584 case HWC_POWER_MODE_DOZE_SUSPEND:
585 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400586 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400587 break;
588 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400589 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500590}
591
Sean Paulef8f1f92015-04-29 16:05:23 -0400592static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
593 int *value) {
594 switch (what) {
595 case HWC_BACKGROUND_LAYER_SUPPORTED:
596 *value = 0; /* TODO: We should do this */
597 break;
598 case HWC_VSYNC_PERIOD:
599 ALOGW("Query for deprecated vsync value, returning 60Hz");
600 *value = 1000 * 1000 * 1000 / 60;
601 break;
602 case HWC_DISPLAY_TYPES_SUPPORTED:
603 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
604 break;
605 }
606 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500607}
608
Sean Paulef8f1f92015-04-29 16:05:23 -0400609static void hwc_register_procs(struct hwc_composer_device_1 *dev,
610 hwc_procs_t const *procs) {
611 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500612
Sean Paulef8f1f92015-04-29 16:05:23 -0400613 ctx->procs = procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500614}
615
Sean Paulef8f1f92015-04-29 16:05:23 -0400616static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
617 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400618 size_t *num_configs) {
619 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400620 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500621
Sean Paulef8f1f92015-04-29 16:05:23 -0400622 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
623 struct hwc_drm_display *hd = NULL;
624 int ret = hwc_get_drm_display(ctx, display, &hd);
625 if (ret)
626 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500627
Sean Paul6a55e9f2015-04-30 15:31:06 -0400628 hd->config_ids.clear();
629
630 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
631 if (!connector) {
632 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400633 return -ENODEV;
634 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500635
Sean Paul6a55e9f2015-04-30 15:31:06 -0400636 ret = connector->UpdateModes();
637 if (ret) {
638 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400639 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400640 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500641
Sean Paul6a55e9f2015-04-30 15:31:06 -0400642 for (DrmConnector::ModeIter iter = connector->begin_modes();
643 iter != connector->end_modes(); ++iter) {
644 size_t idx = hd->config_ids.size();
645 if (idx == *num_configs)
646 break;
647 hd->config_ids.push_back(iter->id());
648 configs[idx] = iter->id();
649 }
650 *num_configs = hd->config_ids.size();
651 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500652}
653
Sean Paulef8f1f92015-04-29 16:05:23 -0400654static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
655 int display, uint32_t config,
656 const uint32_t *attributes,
657 int32_t *values) {
658 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400659 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400660 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400661 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400662 return -ENODEV;
663 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400664 DrmMode mode;
665 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
666 ++iter) {
667 if (iter->id() == config) {
668 mode = *iter;
669 break;
670 }
671 }
672 if (mode.id() == 0) {
673 ALOGE("Failed to find active mode for display %d", display);
674 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400675 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500676
Sean Paul6a55e9f2015-04-30 15:31:06 -0400677 uint32_t mm_width = c->mm_width();
678 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400679 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
680 switch (attributes[i]) {
681 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400682 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400683 break;
684 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400685 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400686 break;
687 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400688 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400689 break;
690 case HWC_DISPLAY_DPI_X:
691 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400692 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400693 break;
694 case HWC_DISPLAY_DPI_Y:
695 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400696 values[i] =
697 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400698 break;
699 }
700 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400701 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500702}
703
Sean Paulef8f1f92015-04-29 16:05:23 -0400704static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
705 int display) {
706 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
707 struct hwc_drm_display *hd = NULL;
708 int ret = hwc_get_drm_display(ctx, display, &hd);
709 if (ret)
710 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500711
Sean Paul6a55e9f2015-04-30 15:31:06 -0400712 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
713 if (!c) {
714 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400715 return -ENODEV;
716 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500717
Sean Paul6a55e9f2015-04-30 15:31:06 -0400718 DrmMode mode = c->active_mode();
719 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
720 if (hd->config_ids[i] == mode.id())
721 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400722 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400723 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500724}
725
Sean Paulef8f1f92015-04-29 16:05:23 -0400726static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
727 int index) {
728 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
729 struct hwc_drm_display *hd = NULL;
730 int ret = hwc_get_drm_display(ctx, display, &hd);
731 if (ret)
732 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500733
Sean Paul6a55e9f2015-04-30 15:31:06 -0400734 if (index >= (int)hd->config_ids.size()) {
735 ALOGE("Invalid config index %d passed in", index);
736 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400737 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500738
Sean Paul6a55e9f2015-04-30 15:31:06 -0400739 ret =
740 ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
741 if (ret) {
742 ALOGE("Failed to set config for display %d", display);
743 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400744 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500745
Sean Paul6a55e9f2015-04-30 15:31:06 -0400746 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500747}
748
Sean Paulef8f1f92015-04-29 16:05:23 -0400749static int hwc_destroy_worker(struct hwc_worker *worker) {
750 int ret = pthread_mutex_lock(&worker->lock);
751 if (ret) {
752 ALOGE("Failed to lock in destroy() %d", ret);
753 return ret;
754 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500755
Sean Paulef8f1f92015-04-29 16:05:23 -0400756 worker->exit = true;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500757
Sean Paulef8f1f92015-04-29 16:05:23 -0400758 ret |= pthread_cond_signal(&worker->cond);
759 if (ret)
760 ALOGE("Failed to signal cond in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500761
Sean Paulef8f1f92015-04-29 16:05:23 -0400762 ret |= pthread_mutex_unlock(&worker->lock);
763 if (ret)
764 ALOGE("Failed to unlock in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500765
Sean Paulef8f1f92015-04-29 16:05:23 -0400766 ret |= pthread_join(worker->thread, NULL);
767 if (ret && ret != ESRCH)
768 ALOGE("Failed to join thread in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500769
Sean Paulef8f1f92015-04-29 16:05:23 -0400770 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500771}
772
Sean Paulef8f1f92015-04-29 16:05:23 -0400773static void hwc_destroy_display(struct hwc_drm_display *hd) {
774 if (hwc_destroy_worker(&hd->set_worker))
775 ALOGE("Destroy set worker failed");
Sean Paul9aa5ad32015-01-22 15:47:54 -0500776}
777
Sean Paulef8f1f92015-04-29 16:05:23 -0400778static int hwc_device_close(struct hw_device_t *dev) {
779 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500780
Sean Paulef8f1f92015-04-29 16:05:23 -0400781 for (int i = 0; i < MAX_NUM_DISPLAYS; ++i)
782 hwc_destroy_display(&ctx->displays[i]);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500783
Sean Paulef8f1f92015-04-29 16:05:23 -0400784 if (hwc_destroy_worker(&ctx->event_worker))
785 ALOGE("Destroy event worker failed");
Sean Paul814bddb2015-03-03 17:46:19 -0500786
Sean Paulef8f1f92015-04-29 16:05:23 -0400787 int ret = hwc_import_destroy(ctx->import_ctx);
788 if (ret)
789 ALOGE("Could not destroy import %d", ret);
Sean Paulcd36a9e2015-01-22 18:01:18 -0500790
Sean Paulef8f1f92015-04-29 16:05:23 -0400791 delete ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500792
Sean Paulef8f1f92015-04-29 16:05:23 -0400793 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500794}
795
Sean Paul814bddb2015-03-03 17:46:19 -0500796static int hwc_initialize_worker(struct hwc_worker *worker,
Sean Paulef8f1f92015-04-29 16:05:23 -0400797 void *(*routine)(void *), void *arg) {
798 int ret = pthread_cond_init(&worker->cond, NULL);
799 if (ret) {
800 ALOGE("Failed to create worker condition %d", ret);
801 return ret;
802 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500803
Sean Paulef8f1f92015-04-29 16:05:23 -0400804 ret = pthread_mutex_init(&worker->lock, NULL);
805 if (ret) {
806 ALOGE("Failed to initialize worker lock %d", ret);
807 pthread_cond_destroy(&worker->cond);
808 return ret;
809 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500810
Sean Paulef8f1f92015-04-29 16:05:23 -0400811 worker->exit = false;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500812
Sean Paulef8f1f92015-04-29 16:05:23 -0400813 ret = pthread_create(&worker->thread, NULL, routine, arg);
814 if (ret) {
815 ALOGE("Could not create worker thread %d", ret);
816 pthread_mutex_destroy(&worker->lock);
817 pthread_cond_destroy(&worker->cond);
818 return ret;
819 }
820 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500821}
822
Sean Paul24a26e32015-02-04 10:34:47 -0800823/*
824 * TODO: This function sets the active config to the first one in the list. This
825 * should be fixed such that it selects the preferred mode for the display, or
826 * some other, saner, method of choosing the config.
827 */
Sean Paulef8f1f92015-04-29 16:05:23 -0400828static int hwc_set_initial_config(struct hwc_drm_display *hd) {
829 uint32_t config;
830 size_t num_configs = 1;
831 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
832 &num_configs);
833 if (ret || !num_configs)
834 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800835
Sean Paulef8f1f92015-04-29 16:05:23 -0400836 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
837 if (ret) {
838 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
839 return ret;
840 }
Sean Paul24a26e32015-02-04 10:34:47 -0800841
Sean Paulef8f1f92015-04-29 16:05:23 -0400842 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800843}
844
Sean Paul6a55e9f2015-04-30 15:31:06 -0400845static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400846 struct hwc_drm_display *hd = NULL;
847 int ret = hwc_get_drm_display(ctx, display, &hd);
848 if (ret)
849 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500850
Sean Paulef8f1f92015-04-29 16:05:23 -0400851 hd->ctx = ctx;
852 hd->display = display;
Sean Paulef8f1f92015-04-29 16:05:23 -0400853 hd->enable_vsync_events = false;
854 hd->vsync_sequence = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500855
Sean Paulef8f1f92015-04-29 16:05:23 -0400856 ret = pthread_mutex_init(&hd->flip_lock, NULL);
857 if (ret) {
858 ALOGE("Failed to initialize flip lock %d", ret);
859 return ret;
860 }
Sean Paul814bddb2015-03-03 17:46:19 -0500861
Sean Paulef8f1f92015-04-29 16:05:23 -0400862 ret = pthread_cond_init(&hd->flip_cond, NULL);
863 if (ret) {
864 ALOGE("Failed to intiialize flip condition %d", ret);
865 pthread_mutex_destroy(&hd->flip_lock);
866 return ret;
867 }
Sean Paul814bddb2015-03-03 17:46:19 -0500868
Sean Paulef8f1f92015-04-29 16:05:23 -0400869 ret = sw_sync_timeline_create();
870 if (ret < 0) {
871 ALOGE("Failed to create sw sync timeline %d", ret);
872 pthread_cond_destroy(&hd->flip_cond);
873 pthread_mutex_destroy(&hd->flip_lock);
874 return ret;
875 }
876 hd->timeline_fd = ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500877
Sean Paulef8f1f92015-04-29 16:05:23 -0400878 /*
879 * Initialize timeline_next to 1, because point 0 will be the very first
880 * set operation. Since we increment every time set() is called,
881 * initializing to 0 would cause an off-by-one error where
882 * surfaceflinger would composite on the front buffer.
883 */
884 hd->timeline_next = 1;
Sean Paule147a2a2015-02-22 17:55:43 -0500885
Sean Paulef8f1f92015-04-29 16:05:23 -0400886 ret = hwc_set_initial_config(hd);
887 if (ret) {
888 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
889 close(hd->timeline_fd);
890 pthread_cond_destroy(&hd->flip_cond);
891 pthread_mutex_destroy(&hd->flip_lock);
892 return ret;
893 }
Sean Paulf1dc1912015-01-24 01:34:31 -0500894
Sean Paulef8f1f92015-04-29 16:05:23 -0400895 ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd);
896 if (ret) {
897 ALOGE("Failed to create set worker %d\n", ret);
898 close(hd->timeline_fd);
899 pthread_cond_destroy(&hd->flip_cond);
900 pthread_mutex_destroy(&hd->flip_lock);
901 return ret;
902 }
Sean Paul24a26e32015-02-04 10:34:47 -0800903
Sean Paulef8f1f92015-04-29 16:05:23 -0400904 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500905}
906
Sean Paulef8f1f92015-04-29 16:05:23 -0400907static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) {
908 for (int i = 0; i < num_conn; ++i) {
909 if (conn_list[i])
910 drmModeFreeConnector(conn_list[i]);
911 }
912 free(conn_list);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500913}
914
Sean Paulef8f1f92015-04-29 16:05:23 -0400915static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400916 int ret;
917 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
918 c != ctx->drm.end_connectors(); ++c) {
919 ret = hwc_initialize_display(ctx, (*c)->display());
920 if (ret) {
921 ALOGE("Failed to initialize display %d", (*c)->display());
922 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400923 }
924 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400925
926 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500927}
928
Sean Paulef8f1f92015-04-29 16:05:23 -0400929static int hwc_device_open(const struct hw_module_t *module, const char *name,
930 struct hw_device_t **dev) {
931 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
932 ALOGE("Invalid module name- %s", name);
933 return -EINVAL;
934 }
935
936 struct hwc_context_t *ctx = new hwc_context_t();
937 if (!ctx) {
938 ALOGE("Failed to allocate hwc context");
939 return -ENOMEM;
940 }
941
Sean Paul6a55e9f2015-04-30 15:31:06 -0400942 int ret = ctx->drm.Init();
943 if (ret) {
944 ALOGE("Can't initialize Drm object %d", ret);
945 delete ctx;
946 return ret;
947 }
948
949 ret = hwc_import_init(&ctx->import_ctx);
Sean Paulef8f1f92015-04-29 16:05:23 -0400950 if (ret) {
951 ALOGE("Failed to initialize import context");
952 delete ctx;
953 return ret;
954 }
955
Sean Paulef8f1f92015-04-29 16:05:23 -0400956 ret = hwc_enumerate_displays(ctx);
957 if (ret) {
958 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400959 delete ctx;
960 return ret;
961 }
962
963 ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx);
964 if (ret) {
965 ALOGE("Failed to create event worker %d\n", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400966 delete ctx;
967 return ret;
968 }
969
970 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
971 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
972 ctx->device.common.module = const_cast<hw_module_t *>(module);
973 ctx->device.common.close = hwc_device_close;
974
975 ctx->device.prepare = hwc_prepare;
976 ctx->device.set = hwc_set;
977 ctx->device.eventControl = hwc_event_control;
978 ctx->device.setPowerMode = hwc_set_power_mode;
979 ctx->device.query = hwc_query;
980 ctx->device.registerProcs = hwc_register_procs;
981 ctx->device.getDisplayConfigs = hwc_get_display_configs;
982 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
983 ctx->device.getActiveConfig = hwc_get_active_config;
984 ctx->device.setActiveConfig = hwc_set_active_config;
985 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
986
987 *dev = &ctx->device.common;
988
989 return 0;
990}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400991}
Sean Paulef8f1f92015-04-29 16:05:23 -0400992
Sean Paul6a55e9f2015-04-30 15:31:06 -0400993static struct hw_module_methods_t hwc_module_methods = {
994 open : android::hwc_device_open
995};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500996
997hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -0400998 common : {
999 tag : HARDWARE_MODULE_TAG,
1000 version_major : 1,
1001 version_minor : 0,
1002 id : HWC_HARDWARE_MODULE_ID,
1003 name : "DRM hwcomposer module",
1004 author : "The Android Open Source Project",
1005 methods : &hwc_module_methods,
1006 dso : NULL,
1007 reserved : {0},
1008 }
Sean Paule0c4c3d2015-01-20 16:56:04 -05001009};