Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2015 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
| 17 | #define LOG_TAG "hwcomposer-drm" |
| 18 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 19 | #include "drm_hwcomposer.h" |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 20 | #include "drmresources.h" |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 21 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 22 | #include <errno.h> |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 23 | #include <fcntl.h> |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 24 | #include <list> |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 25 | #include <pthread.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 26 | #include <sys/param.h> |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 27 | #include <sys/resource.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 28 | #include <xf86drm.h> |
| 29 | #include <xf86drmMode.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 30 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 31 | #include <cutils/log.h> |
| 32 | #include <cutils/properties.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 33 | #include <hardware/hardware.h> |
| 34 | #include <hardware/hwcomposer.h> |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 35 | #include <sw_sync.h> |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 36 | #include <sync/sync.h> |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 37 | |
| 38 | #define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0])) |
| 39 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 40 | #define MAX_NUM_DISPLAYS 3 |
| 41 | #define UM_PER_INCH 25400 |
| 42 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 43 | namespace android { |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 44 | |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 45 | struct hwc_worker { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 46 | pthread_t thread; |
| 47 | pthread_mutex_t lock; |
| 48 | pthread_cond_t cond; |
| 49 | bool exit; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 50 | }; |
| 51 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 52 | struct hwc_drm_display { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 53 | struct hwc_context_t *ctx; |
| 54 | int display; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 55 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 56 | std::vector<uint32_t> config_ids; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 57 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 58 | struct hwc_worker set_worker; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 59 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 60 | std::list<struct hwc_drm_bo> buf_queue; |
| 61 | struct hwc_drm_bo front; |
| 62 | pthread_mutex_t flip_lock; |
| 63 | pthread_cond_t flip_cond; |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 64 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 65 | int timeline_fd; |
| 66 | unsigned timeline_next; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 67 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 68 | bool enable_vsync_events; |
| 69 | unsigned int vsync_sequence; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 70 | }; |
| 71 | |
| 72 | struct hwc_context_t { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 73 | hwc_composer_device_1_t device; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 74 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 75 | hwc_procs_t const *procs; |
| 76 | struct hwc_import_context *import_ctx; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 77 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 78 | struct hwc_drm_display displays[MAX_NUM_DISPLAYS]; |
| 79 | int num_displays; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 80 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 81 | struct hwc_worker event_worker; |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 82 | |
| 83 | DrmResources drm; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 84 | }; |
| 85 | |
| 86 | static int hwc_get_drm_display(struct hwc_context_t *ctx, int display, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 87 | struct hwc_drm_display **hd) { |
| 88 | if (display >= MAX_NUM_DISPLAYS) { |
| 89 | ALOGE("Requested display is out-of-bounds %d %d", display, |
| 90 | MAX_NUM_DISPLAYS); |
| 91 | return -EINVAL; |
| 92 | } |
| 93 | *hd = &ctx->displays[display]; |
| 94 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 95 | } |
| 96 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 97 | static int hwc_prepare_layer(hwc_layer_1_t *layer) { |
| 98 | /* TODO: We can't handle background right now, defer to sufaceFlinger */ |
| 99 | if (layer->compositionType == HWC_BACKGROUND) { |
| 100 | layer->compositionType = HWC_FRAMEBUFFER; |
| 101 | ALOGV("Can't handle background layers yet"); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 102 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 103 | /* TODO: Support sideband compositions */ |
| 104 | } else if (layer->compositionType == HWC_SIDEBAND) { |
| 105 | layer->compositionType = HWC_FRAMEBUFFER; |
| 106 | ALOGV("Can't handle sideband content yet"); |
| 107 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 108 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 109 | layer->hints = 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 110 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 111 | /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */ |
| 112 | if (layer->flags & HWC_IS_CURSOR_LAYER) { |
| 113 | ALOGV("Can't handle async cursors yet"); |
| 114 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 115 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 116 | /* TODO: Handle transformations */ |
| 117 | if (layer->transform) { |
| 118 | ALOGV("Can't handle transformations yet"); |
| 119 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 120 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 121 | /* TODO: Handle blending & plane alpha*/ |
| 122 | if (layer->blending == HWC_BLENDING_PREMULT || |
| 123 | layer->blending == HWC_BLENDING_COVERAGE) { |
| 124 | ALOGV("Can't handle blending yet"); |
| 125 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 126 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 127 | /* TODO: Handle cropping & scaling */ |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 128 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 129 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 130 | } |
| 131 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 132 | static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays, |
| 133 | hwc_display_contents_1_t **display_contents) { |
| 134 | /* TODO: Check flags for HWC_GEOMETRY_CHANGED */ |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 135 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 136 | for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) { |
| 137 | if (!display_contents[i]) |
| 138 | continue; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 139 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 140 | for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) { |
| 141 | int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]); |
| 142 | if (ret) { |
| 143 | ALOGE("Failed to prepare layer %d:%d", j, i); |
| 144 | return ret; |
| 145 | } |
| 146 | } |
| 147 | } |
Sean Paul | dffca95 | 2015-02-04 10:19:55 -0800 | [diff] [blame] | 148 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 149 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 150 | } |
| 151 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 152 | static int hwc_queue_vblank_event(struct hwc_drm_display *hd) { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 153 | DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display); |
| 154 | if (!crtc) { |
| 155 | ALOGE("Failed to get crtc for display"); |
| 156 | return -ENODEV; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 157 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 158 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 159 | drmVBlank vblank; |
| 160 | memset(&vblank, 0, sizeof(vblank)); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 161 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 162 | uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 163 | vblank.request.type = (drmVBlankSeqType)( |
| 164 | DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT | |
| 165 | (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK)); |
| 166 | vblank.request.signal = (unsigned long)hd; |
| 167 | vblank.request.sequence = hd->vsync_sequence + 1; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 168 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 169 | int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 170 | if (ret) { |
| 171 | ALOGE("Failed to wait for vblank %d", ret); |
| 172 | return ret; |
| 173 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 174 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 175 | return 0; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 176 | } |
| 177 | |
| 178 | static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 179 | unsigned int tv_sec, unsigned int tv_usec, |
| 180 | void *user_data) { |
| 181 | struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 182 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 183 | if (!hd->enable_vsync_events || !hd->ctx->procs->vsync) |
| 184 | return; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 185 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 186 | /* |
| 187 | * Discard duplicate vsync (can happen when enabling vsync events while |
| 188 | * already processing vsyncs). |
| 189 | */ |
| 190 | if (sequence <= hd->vsync_sequence) |
| 191 | return; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 192 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 193 | hd->vsync_sequence = sequence; |
| 194 | int ret = hwc_queue_vblank_event(hd); |
| 195 | if (ret) |
| 196 | ALOGE("Failed to queue vblank event ret=%d", ret); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 197 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 198 | int64_t timestamp = |
| 199 | (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000; |
| 200 | hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 201 | } |
| 202 | |
| 203 | static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 204 | unsigned int /* tv_sec */, |
| 205 | unsigned int /* tv_usec */, |
| 206 | void *user_data) { |
| 207 | struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 208 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 209 | int ret = pthread_mutex_lock(&hd->flip_lock); |
| 210 | if (ret) { |
| 211 | ALOGE("Failed to lock flip lock ret=%d", ret); |
| 212 | return; |
| 213 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 214 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 215 | ret = pthread_cond_signal(&hd->flip_cond); |
| 216 | if (ret) |
| 217 | ALOGE("Failed to signal flip condition ret=%d", ret); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 218 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 219 | ret = pthread_mutex_unlock(&hd->flip_lock); |
| 220 | if (ret) { |
| 221 | ALOGE("Failed to unlock flip lock ret=%d", ret); |
| 222 | return; |
| 223 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 224 | } |
| 225 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 226 | static void *hwc_event_worker(void *arg) { |
| 227 | setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 228 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 229 | struct hwc_context_t *ctx = (struct hwc_context_t *)arg; |
| 230 | do { |
| 231 | fd_set fds; |
| 232 | FD_ZERO(&fds); |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 233 | FD_SET(ctx->drm.fd(), &fds); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 234 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 235 | drmEventContext event_context; |
| 236 | event_context.version = DRM_EVENT_CONTEXT_VERSION; |
| 237 | event_context.page_flip_handler = hwc_flip_event_handler; |
| 238 | event_context.vblank_handler = hwc_vblank_event_handler; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 239 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 240 | int ret; |
| 241 | do { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 242 | ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 243 | } while (ret == -1 && errno == EINTR); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 244 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 245 | if (ret != 1) { |
| 246 | ALOGE("Failed waiting for drm event\n"); |
| 247 | continue; |
| 248 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 249 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 250 | drmHandleEvent(ctx->drm.fd(), &event_context); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 251 | } while (true); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 252 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 253 | return NULL; |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 254 | } |
| 255 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 256 | static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) { |
| 257 | return a->clock == b->clock && a->hdisplay == b->hdisplay && |
| 258 | a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end && |
| 259 | a->htotal == b->htotal && a->hskew == b->hskew && |
| 260 | a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start && |
| 261 | a->vsync_end == b->vsync_end && a->vtotal == b->vtotal && |
| 262 | a->vscan == b->vscan && a->vrefresh == b->vrefresh && |
| 263 | a->flags == b->flags && a->type == b->type && |
| 264 | !strcmp(a->name, b->name); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 265 | } |
| 266 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 267 | static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) { |
| 268 | DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 269 | if (!crtc) { |
| 270 | ALOGE("Failed to get crtc for display %d", hd->display); |
| 271 | return -ENODEV; |
| 272 | } |
Sean Paul | efb20cb | 2015-02-04 09:29:15 -0800 | [diff] [blame] | 273 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 274 | DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display); |
| 275 | if (!connector) { |
| 276 | ALOGE("Failed to get connector for display %d", hd->display); |
| 277 | return -ENODEV; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 278 | } |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 279 | |
| 280 | int ret; |
| 281 | if (crtc->requires_modeset()) { |
| 282 | drmModeModeInfo drm_mode; |
| 283 | connector->active_mode().ToModeModeInfo(&drm_mode); |
| 284 | uint32_t connector_id = connector->id(); |
| 285 | ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0, |
| 286 | &connector_id, 1, &drm_mode); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 287 | if (ret) { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 288 | ALOGE("Modeset failed for crtc %d", crtc->id()); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 289 | return ret; |
| 290 | } |
| 291 | return 0; |
| 292 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 293 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 294 | ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 295 | DRM_MODE_PAGE_FLIP_EVENT, hd); |
| 296 | if (ret) { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 297 | ALOGE("Failed to flip buffer for crtc %d", crtc->id()); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 298 | return ret; |
| 299 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 300 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 301 | ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock); |
| 302 | if (ret) { |
| 303 | ALOGE("Failed to wait on condition %d", ret); |
| 304 | return ret; |
| 305 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 306 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 307 | return 0; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 308 | } |
| 309 | |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 310 | static int hwc_wait_and_set(struct hwc_drm_display *hd, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 311 | struct hwc_drm_bo *buf) { |
| 312 | int ret; |
| 313 | if (buf->acquire_fence_fd >= 0) { |
| 314 | ret = sync_wait(buf->acquire_fence_fd, -1); |
| 315 | close(buf->acquire_fence_fd); |
| 316 | buf->acquire_fence_fd = -1; |
| 317 | if (ret) { |
| 318 | ALOGE("Failed to wait for acquire %d", ret); |
| 319 | return ret; |
| 320 | } |
| 321 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 322 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 323 | ret = hwc_flip(hd, buf); |
| 324 | if (ret) { |
| 325 | ALOGE("Failed to perform flip\n"); |
| 326 | return ret; |
| 327 | } |
Lauri Peltonen | 132e010 | 2015-02-12 13:54:33 +0200 | [diff] [blame] | 328 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 329 | if (hwc_import_bo_release(hd->ctx->drm.fd(), hd->ctx->import_ctx, |
| 330 | &hd->front)) { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 331 | struct drm_gem_close args; |
| 332 | memset(&args, 0, sizeof(args)); |
| 333 | for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) { |
| 334 | if (!hd->front.gem_handles[i]) |
| 335 | continue; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 336 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 337 | ret = pthread_mutex_lock(&hd->set_worker.lock); |
| 338 | if (ret) { |
| 339 | ALOGE("Failed to lock set lock in wait_and_set() %d", ret); |
| 340 | continue; |
| 341 | } |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 342 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 343 | /* check for duplicate handle in buf_queue */ |
| 344 | bool found = false; |
| 345 | for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin(); |
| 346 | bi != hd->buf_queue.end(); ++bi) |
| 347 | for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j) |
| 348 | if (hd->front.gem_handles[i] == bi->gem_handles[j]) |
| 349 | found = true; |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 350 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 351 | for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j) |
| 352 | if (hd->front.gem_handles[i] == buf->gem_handles[j]) |
| 353 | found = true; |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 354 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 355 | if (!found) { |
| 356 | args.handle = hd->front.gem_handles[i]; |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 357 | drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 358 | } |
| 359 | if (pthread_mutex_unlock(&hd->set_worker.lock)) |
| 360 | ALOGE("Failed to unlock set lock in wait_and_set() %d", ret); |
| 361 | } |
| 362 | } |
Lauri Peltonen | 77d6d7a | 2015-02-23 20:44:16 +0200 | [diff] [blame] | 363 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 364 | hd->front = *buf; |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 365 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 366 | return ret; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 367 | } |
| 368 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 369 | static void *hwc_set_worker(void *arg) { |
| 370 | setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 371 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 372 | struct hwc_drm_display *hd = (struct hwc_drm_display *)arg; |
| 373 | int ret = pthread_mutex_lock(&hd->flip_lock); |
| 374 | if (ret) { |
| 375 | ALOGE("Failed to lock flip lock ret=%d", ret); |
| 376 | return NULL; |
| 377 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 378 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 379 | do { |
| 380 | ret = pthread_mutex_lock(&hd->set_worker.lock); |
| 381 | if (ret) { |
| 382 | ALOGE("Failed to lock set lock %d", ret); |
| 383 | return NULL; |
| 384 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 385 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 386 | if (hd->set_worker.exit) |
| 387 | break; |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 388 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 389 | if (hd->buf_queue.empty()) { |
| 390 | ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock); |
| 391 | if (ret) { |
| 392 | ALOGE("Failed to wait on condition %d", ret); |
| 393 | break; |
| 394 | } |
| 395 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 396 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 397 | struct hwc_drm_bo buf; |
| 398 | buf = hd->buf_queue.front(); |
| 399 | hd->buf_queue.pop_front(); |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 400 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 401 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
| 402 | if (ret) { |
| 403 | ALOGE("Failed to unlock set lock %d", ret); |
| 404 | return NULL; |
| 405 | } |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 406 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 407 | ret = hwc_wait_and_set(hd, &buf); |
| 408 | if (ret) |
| 409 | ALOGE("Failed to wait and set %d", ret); |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 410 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 411 | ret = sw_sync_timeline_inc(hd->timeline_fd, 1); |
| 412 | if (ret) |
| 413 | ALOGE("Failed to increment sync timeline %d", ret); |
| 414 | } while (true); |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 415 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 416 | ret = pthread_mutex_unlock(&hd->set_worker.lock); |
| 417 | if (ret) |
| 418 | ALOGE("Failed to unlock set lock while exiting %d", ret); |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 419 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 420 | ret = pthread_mutex_unlock(&hd->flip_lock); |
| 421 | if (ret) |
| 422 | ALOGE("Failed to unlock flip lock ret=%d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 423 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 424 | return NULL; |
| 425 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 426 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 427 | static void hwc_close_fences(hwc_display_contents_1_t *display_contents) { |
| 428 | for (int i = 0; i < (int)display_contents->numHwLayers; ++i) { |
| 429 | hwc_layer_1_t *layer = &display_contents->hwLayers[i]; |
| 430 | if (layer->acquireFenceFd >= 0) { |
| 431 | close(layer->acquireFenceFd); |
| 432 | layer->acquireFenceFd = -1; |
| 433 | } |
| 434 | } |
| 435 | if (display_contents->outbufAcquireFenceFd >= 0) { |
| 436 | close(display_contents->outbufAcquireFenceFd); |
| 437 | display_contents->outbufAcquireFenceFd = -1; |
| 438 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 439 | } |
| 440 | |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 441 | static int hwc_set_display(hwc_context_t *ctx, int display, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 442 | hwc_display_contents_1_t *display_contents) { |
| 443 | struct hwc_drm_display *hd = NULL; |
| 444 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 445 | if (ret) { |
| 446 | hwc_close_fences(display_contents); |
| 447 | return ret; |
| 448 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 449 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 450 | DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display); |
| 451 | if (!crtc) { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 452 | ALOGE("There is no active crtc for display %d", display); |
| 453 | hwc_close_fences(display_contents); |
| 454 | return -ENOENT; |
| 455 | } |
Sean Paul | 9b1bb84 | 2015-01-23 01:11:58 -0500 | [diff] [blame] | 456 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 457 | /* |
| 458 | * TODO: We can only support one hw layer atm, so choose either the |
| 459 | * first one or the framebuffer target. |
| 460 | */ |
| 461 | hwc_layer_1_t *layer = NULL; |
| 462 | if (!display_contents->numHwLayers) { |
| 463 | return 0; |
| 464 | } else if (display_contents->numHwLayers == 1) { |
| 465 | layer = &display_contents->hwLayers[0]; |
| 466 | } else { |
| 467 | int i; |
| 468 | for (i = 0; i < (int)display_contents->numHwLayers; ++i) { |
| 469 | layer = &display_contents->hwLayers[i]; |
| 470 | if (layer->compositionType == HWC_FRAMEBUFFER_TARGET) |
| 471 | break; |
| 472 | } |
| 473 | if (i == (int)display_contents->numHwLayers) { |
| 474 | ALOGE("Could not find a suitable layer for display %d", display); |
| 475 | } |
| 476 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 477 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 478 | ret = pthread_mutex_lock(&hd->set_worker.lock); |
| 479 | if (ret) { |
| 480 | ALOGE("Failed to lock set lock in set() %d", ret); |
| 481 | hwc_close_fences(display_contents); |
| 482 | return ret; |
| 483 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 484 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 485 | struct hwc_drm_bo buf; |
| 486 | memset(&buf, 0, sizeof(buf)); |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 487 | ret = |
| 488 | hwc_import_bo_create(ctx->drm.fd(), ctx->import_ctx, layer->handle, &buf); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 489 | if (ret) { |
| 490 | ALOGE("Failed to import handle to drm bo %d", ret); |
| 491 | hwc_close_fences(display_contents); |
| 492 | return ret; |
| 493 | } |
| 494 | buf.acquire_fence_fd = layer->acquireFenceFd; |
| 495 | layer->acquireFenceFd = -1; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 496 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 497 | /* |
| 498 | * TODO: Retire and release can use the same sync point here b/c hwc is |
| 499 | * restricted to one layer. Once that is no longer true, this will need |
| 500 | * to change |
| 501 | */ |
| 502 | ++hd->timeline_next; |
| 503 | display_contents->retireFenceFd = sw_sync_fence_create( |
| 504 | hd->timeline_fd, "drm_hwc_retire", hd->timeline_next); |
| 505 | layer->releaseFenceFd = sw_sync_fence_create( |
| 506 | hd->timeline_fd, "drm_hwc_release", hd->timeline_next); |
| 507 | hd->buf_queue.push_back(buf); |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 508 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 509 | ret = pthread_cond_signal(&hd->set_worker.cond); |
| 510 | if (ret) |
| 511 | ALOGE("Failed to signal set worker %d", ret); |
Allen Martin | 3d3f70a | 2015-02-21 21:20:17 -0800 | [diff] [blame] | 512 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 513 | if (pthread_mutex_unlock(&hd->set_worker.lock)) |
| 514 | ALOGE("Failed to unlock set lock in set()"); |
Sean Paul | 3bc48e8 | 2015-01-23 01:41:13 -0500 | [diff] [blame] | 515 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 516 | hwc_close_fences(display_contents); |
| 517 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 518 | } |
| 519 | |
| 520 | static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 521 | hwc_display_contents_1_t **display_contents) { |
| 522 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 523 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 524 | int ret = 0; |
| 525 | for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) { |
| 526 | if (display_contents[i]) |
| 527 | ret = hwc_set_display(ctx, i, display_contents[i]); |
| 528 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 529 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 530 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 531 | } |
| 532 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 533 | static int hwc_event_control(struct hwc_composer_device_1 *dev, int display, |
| 534 | int event, int enabled) { |
| 535 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 536 | struct hwc_drm_display *hd = NULL; |
| 537 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 538 | if (ret) |
| 539 | return ret; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 540 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 541 | if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1)) |
| 542 | return -EINVAL; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 543 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 544 | DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display); |
| 545 | if (!crtc) { |
| 546 | ALOGD("Can't service events for display %d, no crtc", display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 547 | return -EINVAL; |
| 548 | } |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 549 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 550 | hd->enable_vsync_events = !!enabled; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 551 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 552 | if (!hd->enable_vsync_events) |
| 553 | return 0; |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 554 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 555 | /* |
| 556 | * Note that it's possible that the event worker is already waiting for |
| 557 | * a vsync, and this will be a duplicate request. In that event, we'll |
| 558 | * end up firing the event handler twice, and it will discard the second |
| 559 | * event. Not ideal, but not worth introducing a bunch of additional |
| 560 | * logic/locks/state for. |
| 561 | */ |
| 562 | ret = hwc_queue_vblank_event(hd); |
| 563 | if (ret) { |
| 564 | ALOGE("Failed to queue vblank event ret=%d", ret); |
| 565 | return ret; |
| 566 | } |
Sean Paul | eb9e75c | 2015-01-25 23:31:30 -0500 | [diff] [blame] | 567 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 568 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 569 | } |
| 570 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 571 | static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display, |
| 572 | int mode) { |
| 573 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 574 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 575 | uint64_t dpmsValue = 0; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 576 | switch (mode) { |
| 577 | case HWC_POWER_MODE_OFF: |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 578 | dpmsValue = DRM_MODE_DPMS_OFF; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 579 | break; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 580 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 581 | /* We can't support dozing right now, so go full on */ |
| 582 | case HWC_POWER_MODE_DOZE: |
| 583 | case HWC_POWER_MODE_DOZE_SUSPEND: |
| 584 | case HWC_POWER_MODE_NORMAL: |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 585 | dpmsValue = DRM_MODE_DPMS_ON; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 586 | break; |
| 587 | }; |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 588 | return ctx->drm.SetDpmsMode(display, dpmsValue); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 589 | } |
| 590 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 591 | static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what, |
| 592 | int *value) { |
| 593 | switch (what) { |
| 594 | case HWC_BACKGROUND_LAYER_SUPPORTED: |
| 595 | *value = 0; /* TODO: We should do this */ |
| 596 | break; |
| 597 | case HWC_VSYNC_PERIOD: |
| 598 | ALOGW("Query for deprecated vsync value, returning 60Hz"); |
| 599 | *value = 1000 * 1000 * 1000 / 60; |
| 600 | break; |
| 601 | case HWC_DISPLAY_TYPES_SUPPORTED: |
| 602 | *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL; |
| 603 | break; |
| 604 | } |
| 605 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 606 | } |
| 607 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 608 | static void hwc_register_procs(struct hwc_composer_device_1 *dev, |
| 609 | hwc_procs_t const *procs) { |
| 610 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 611 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 612 | ctx->procs = procs; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 613 | } |
| 614 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 615 | static int hwc_get_display_configs(struct hwc_composer_device_1 *dev, |
| 616 | int display, uint32_t *configs, |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 617 | size_t *num_configs) { |
| 618 | if (!*num_configs) |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 619 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 620 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 621 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 622 | struct hwc_drm_display *hd = NULL; |
| 623 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 624 | if (ret) |
| 625 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 626 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 627 | hd->config_ids.clear(); |
| 628 | |
| 629 | DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display); |
| 630 | if (!connector) { |
| 631 | ALOGE("Failed to get connector for display %d", display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 632 | return -ENODEV; |
| 633 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 634 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 635 | ret = connector->UpdateModes(); |
| 636 | if (ret) { |
| 637 | ALOGE("Failed to update display modes %d", ret); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 638 | return ret; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 639 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 640 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 641 | for (DrmConnector::ModeIter iter = connector->begin_modes(); |
| 642 | iter != connector->end_modes(); ++iter) { |
| 643 | size_t idx = hd->config_ids.size(); |
| 644 | if (idx == *num_configs) |
| 645 | break; |
| 646 | hd->config_ids.push_back(iter->id()); |
| 647 | configs[idx] = iter->id(); |
| 648 | } |
| 649 | *num_configs = hd->config_ids.size(); |
| 650 | return *num_configs == 0 ? -1 : 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 651 | } |
| 652 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 653 | static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev, |
| 654 | int display, uint32_t config, |
| 655 | const uint32_t *attributes, |
| 656 | int32_t *values) { |
| 657 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 658 | DrmConnector *c = ctx->drm.GetConnectorForDisplay(display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 659 | if (!c) { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 660 | ALOGE("Failed to get DrmConnector for display %d", display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 661 | return -ENODEV; |
| 662 | } |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 663 | DrmMode mode; |
| 664 | for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes(); |
| 665 | ++iter) { |
| 666 | if (iter->id() == config) { |
| 667 | mode = *iter; |
| 668 | break; |
| 669 | } |
| 670 | } |
| 671 | if (mode.id() == 0) { |
| 672 | ALOGE("Failed to find active mode for display %d", display); |
| 673 | return -ENOENT; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 674 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 675 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 676 | uint32_t mm_width = c->mm_width(); |
| 677 | uint32_t mm_height = c->mm_height(); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 678 | for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) { |
| 679 | switch (attributes[i]) { |
| 680 | case HWC_DISPLAY_VSYNC_PERIOD: |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 681 | values[i] = 1000 * 1000 * 1000 / mode.v_refresh(); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 682 | break; |
| 683 | case HWC_DISPLAY_WIDTH: |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 684 | values[i] = mode.h_display(); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 685 | break; |
| 686 | case HWC_DISPLAY_HEIGHT: |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 687 | values[i] = mode.v_display(); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 688 | break; |
| 689 | case HWC_DISPLAY_DPI_X: |
| 690 | /* Dots per 1000 inches */ |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 691 | values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 692 | break; |
| 693 | case HWC_DISPLAY_DPI_Y: |
| 694 | /* Dots per 1000 inches */ |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 695 | values[i] = |
| 696 | mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 697 | break; |
| 698 | } |
| 699 | } |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 700 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 701 | } |
| 702 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 703 | static int hwc_get_active_config(struct hwc_composer_device_1 *dev, |
| 704 | int display) { |
| 705 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 706 | struct hwc_drm_display *hd = NULL; |
| 707 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 708 | if (ret) |
| 709 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 710 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 711 | DrmConnector *c = ctx->drm.GetConnectorForDisplay(display); |
| 712 | if (!c) { |
| 713 | ALOGE("Failed to get DrmConnector for display %d", display); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 714 | return -ENODEV; |
| 715 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 716 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 717 | DrmMode mode = c->active_mode(); |
| 718 | for (size_t i = 0; i < hd->config_ids.size(); ++i) { |
| 719 | if (hd->config_ids[i] == mode.id()) |
| 720 | return i; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 721 | } |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 722 | return -1; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 723 | } |
| 724 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 725 | static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display, |
| 726 | int index) { |
| 727 | struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common; |
| 728 | struct hwc_drm_display *hd = NULL; |
| 729 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 730 | if (ret) |
| 731 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 732 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 733 | if (index >= (int)hd->config_ids.size()) { |
| 734 | ALOGE("Invalid config index %d passed in", index); |
| 735 | return -EINVAL; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 736 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 737 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 738 | ret = |
| 739 | ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]); |
| 740 | if (ret) { |
| 741 | ALOGE("Failed to set config for display %d", display); |
| 742 | return ret; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 743 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 744 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 745 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 746 | } |
| 747 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 748 | static int hwc_destroy_worker(struct hwc_worker *worker) { |
| 749 | int ret = pthread_mutex_lock(&worker->lock); |
| 750 | if (ret) { |
| 751 | ALOGE("Failed to lock in destroy() %d", ret); |
| 752 | return ret; |
| 753 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 754 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 755 | worker->exit = true; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 756 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 757 | ret |= pthread_cond_signal(&worker->cond); |
| 758 | if (ret) |
| 759 | ALOGE("Failed to signal cond in destroy() %d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 760 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 761 | ret |= pthread_mutex_unlock(&worker->lock); |
| 762 | if (ret) |
| 763 | ALOGE("Failed to unlock in destroy() %d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 764 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 765 | ret |= pthread_join(worker->thread, NULL); |
| 766 | if (ret && ret != ESRCH) |
| 767 | ALOGE("Failed to join thread in destroy() %d", ret); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 768 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 769 | return ret; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 770 | } |
| 771 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 772 | static void hwc_destroy_display(struct hwc_drm_display *hd) { |
| 773 | if (hwc_destroy_worker(&hd->set_worker)) |
| 774 | ALOGE("Destroy set worker failed"); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 775 | } |
| 776 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 777 | static int hwc_device_close(struct hw_device_t *dev) { |
| 778 | struct hwc_context_t *ctx = (struct hwc_context_t *)dev; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 779 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 780 | for (int i = 0; i < MAX_NUM_DISPLAYS; ++i) |
| 781 | hwc_destroy_display(&ctx->displays[i]); |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 782 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 783 | if (hwc_destroy_worker(&ctx->event_worker)) |
| 784 | ALOGE("Destroy event worker failed"); |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 785 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 786 | int ret = hwc_import_destroy(ctx->import_ctx); |
| 787 | if (ret) |
| 788 | ALOGE("Could not destroy import %d", ret); |
Sean Paul | cd36a9e | 2015-01-22 18:01:18 -0500 | [diff] [blame] | 789 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 790 | delete ctx; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 791 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 792 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 793 | } |
| 794 | |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 795 | static int hwc_initialize_worker(struct hwc_worker *worker, |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 796 | void *(*routine)(void *), void *arg) { |
| 797 | int ret = pthread_cond_init(&worker->cond, NULL); |
| 798 | if (ret) { |
| 799 | ALOGE("Failed to create worker condition %d", ret); |
| 800 | return ret; |
| 801 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 802 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 803 | ret = pthread_mutex_init(&worker->lock, NULL); |
| 804 | if (ret) { |
| 805 | ALOGE("Failed to initialize worker lock %d", ret); |
| 806 | pthread_cond_destroy(&worker->cond); |
| 807 | return ret; |
| 808 | } |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 809 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 810 | worker->exit = false; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 811 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 812 | ret = pthread_create(&worker->thread, NULL, routine, arg); |
| 813 | if (ret) { |
| 814 | ALOGE("Could not create worker thread %d", ret); |
| 815 | pthread_mutex_destroy(&worker->lock); |
| 816 | pthread_cond_destroy(&worker->cond); |
| 817 | return ret; |
| 818 | } |
| 819 | return 0; |
Sean Paul | 9aa5ad3 | 2015-01-22 15:47:54 -0500 | [diff] [blame] | 820 | } |
| 821 | |
Sean Paul | 24a26e3 | 2015-02-04 10:34:47 -0800 | [diff] [blame] | 822 | /* |
| 823 | * TODO: This function sets the active config to the first one in the list. This |
| 824 | * should be fixed such that it selects the preferred mode for the display, or |
| 825 | * some other, saner, method of choosing the config. |
| 826 | */ |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 827 | static int hwc_set_initial_config(struct hwc_drm_display *hd) { |
| 828 | uint32_t config; |
| 829 | size_t num_configs = 1; |
| 830 | int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config, |
| 831 | &num_configs); |
| 832 | if (ret || !num_configs) |
| 833 | return 0; |
Sean Paul | 24a26e3 | 2015-02-04 10:34:47 -0800 | [diff] [blame] | 834 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 835 | ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0); |
| 836 | if (ret) { |
| 837 | ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret); |
| 838 | return ret; |
| 839 | } |
Sean Paul | 24a26e3 | 2015-02-04 10:34:47 -0800 | [diff] [blame] | 840 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 841 | return ret; |
Sean Paul | 24a26e3 | 2015-02-04 10:34:47 -0800 | [diff] [blame] | 842 | } |
| 843 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 844 | static int hwc_initialize_display(struct hwc_context_t *ctx, int display) { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 845 | struct hwc_drm_display *hd = NULL; |
| 846 | int ret = hwc_get_drm_display(ctx, display, &hd); |
| 847 | if (ret) |
| 848 | return ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 849 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 850 | hd->ctx = ctx; |
| 851 | hd->display = display; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 852 | hd->enable_vsync_events = false; |
| 853 | hd->vsync_sequence = 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 854 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 855 | ret = pthread_mutex_init(&hd->flip_lock, NULL); |
| 856 | if (ret) { |
| 857 | ALOGE("Failed to initialize flip lock %d", ret); |
| 858 | return ret; |
| 859 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 860 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 861 | ret = pthread_cond_init(&hd->flip_cond, NULL); |
| 862 | if (ret) { |
| 863 | ALOGE("Failed to intiialize flip condition %d", ret); |
| 864 | pthread_mutex_destroy(&hd->flip_lock); |
| 865 | return ret; |
| 866 | } |
Sean Paul | 814bddb | 2015-03-03 17:46:19 -0500 | [diff] [blame] | 867 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 868 | ret = sw_sync_timeline_create(); |
| 869 | if (ret < 0) { |
| 870 | ALOGE("Failed to create sw sync timeline %d", ret); |
| 871 | pthread_cond_destroy(&hd->flip_cond); |
| 872 | pthread_mutex_destroy(&hd->flip_lock); |
| 873 | return ret; |
| 874 | } |
| 875 | hd->timeline_fd = ret; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 876 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 877 | /* |
| 878 | * Initialize timeline_next to 1, because point 0 will be the very first |
| 879 | * set operation. Since we increment every time set() is called, |
| 880 | * initializing to 0 would cause an off-by-one error where |
| 881 | * surfaceflinger would composite on the front buffer. |
| 882 | */ |
| 883 | hd->timeline_next = 1; |
Sean Paul | e147a2a | 2015-02-22 17:55:43 -0500 | [diff] [blame] | 884 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 885 | ret = hwc_set_initial_config(hd); |
| 886 | if (ret) { |
| 887 | ALOGE("Failed to set initial config for d=%d ret=%d", display, ret); |
| 888 | close(hd->timeline_fd); |
| 889 | pthread_cond_destroy(&hd->flip_cond); |
| 890 | pthread_mutex_destroy(&hd->flip_lock); |
| 891 | return ret; |
| 892 | } |
Sean Paul | f1dc191 | 2015-01-24 01:34:31 -0500 | [diff] [blame] | 893 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 894 | ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd); |
| 895 | if (ret) { |
| 896 | ALOGE("Failed to create set worker %d\n", ret); |
| 897 | close(hd->timeline_fd); |
| 898 | pthread_cond_destroy(&hd->flip_cond); |
| 899 | pthread_mutex_destroy(&hd->flip_lock); |
| 900 | return ret; |
| 901 | } |
Sean Paul | 24a26e3 | 2015-02-04 10:34:47 -0800 | [diff] [blame] | 902 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 903 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 904 | } |
| 905 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 906 | static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) { |
| 907 | for (int i = 0; i < num_conn; ++i) { |
| 908 | if (conn_list[i]) |
| 909 | drmModeFreeConnector(conn_list[i]); |
| 910 | } |
| 911 | free(conn_list); |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 912 | } |
| 913 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 914 | static int hwc_enumerate_displays(struct hwc_context_t *ctx) { |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 915 | int ret; |
| 916 | for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors(); |
| 917 | c != ctx->drm.end_connectors(); ++c) { |
| 918 | ret = hwc_initialize_display(ctx, (*c)->display()); |
| 919 | if (ret) { |
| 920 | ALOGE("Failed to initialize display %d", (*c)->display()); |
| 921 | return ret; |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 922 | } |
| 923 | } |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 924 | |
| 925 | return 0; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 926 | } |
| 927 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 928 | static int hwc_device_open(const struct hw_module_t *module, const char *name, |
| 929 | struct hw_device_t **dev) { |
| 930 | if (strcmp(name, HWC_HARDWARE_COMPOSER)) { |
| 931 | ALOGE("Invalid module name- %s", name); |
| 932 | return -EINVAL; |
| 933 | } |
| 934 | |
| 935 | struct hwc_context_t *ctx = new hwc_context_t(); |
| 936 | if (!ctx) { |
| 937 | ALOGE("Failed to allocate hwc context"); |
| 938 | return -ENOMEM; |
| 939 | } |
| 940 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 941 | int ret = ctx->drm.Init(); |
| 942 | if (ret) { |
| 943 | ALOGE("Can't initialize Drm object %d", ret); |
| 944 | delete ctx; |
| 945 | return ret; |
| 946 | } |
| 947 | |
| 948 | ret = hwc_import_init(&ctx->import_ctx); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 949 | if (ret) { |
| 950 | ALOGE("Failed to initialize import context"); |
| 951 | delete ctx; |
| 952 | return ret; |
| 953 | } |
| 954 | |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 955 | ret = hwc_enumerate_displays(ctx); |
| 956 | if (ret) { |
| 957 | ALOGE("Failed to enumerate displays: %s", strerror(ret)); |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 958 | delete ctx; |
| 959 | return ret; |
| 960 | } |
| 961 | |
| 962 | ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx); |
| 963 | if (ret) { |
| 964 | ALOGE("Failed to create event worker %d\n", ret); |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 965 | delete ctx; |
| 966 | return ret; |
| 967 | } |
| 968 | |
| 969 | ctx->device.common.tag = HARDWARE_DEVICE_TAG; |
| 970 | ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4; |
| 971 | ctx->device.common.module = const_cast<hw_module_t *>(module); |
| 972 | ctx->device.common.close = hwc_device_close; |
| 973 | |
| 974 | ctx->device.prepare = hwc_prepare; |
| 975 | ctx->device.set = hwc_set; |
| 976 | ctx->device.eventControl = hwc_event_control; |
| 977 | ctx->device.setPowerMode = hwc_set_power_mode; |
| 978 | ctx->device.query = hwc_query; |
| 979 | ctx->device.registerProcs = hwc_register_procs; |
| 980 | ctx->device.getDisplayConfigs = hwc_get_display_configs; |
| 981 | ctx->device.getDisplayAttributes = hwc_get_display_attributes; |
| 982 | ctx->device.getActiveConfig = hwc_get_active_config; |
| 983 | ctx->device.setActiveConfig = hwc_set_active_config; |
| 984 | ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */ |
| 985 | |
| 986 | *dev = &ctx->device.common; |
| 987 | |
| 988 | return 0; |
| 989 | } |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 990 | } |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 991 | |
Sean Paul | 6a55e9f | 2015-04-30 15:31:06 -0400 | [diff] [blame^] | 992 | static struct hw_module_methods_t hwc_module_methods = { |
| 993 | open : android::hwc_device_open |
| 994 | }; |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 995 | |
| 996 | hwc_module_t HAL_MODULE_INFO_SYM = { |
Sean Paul | ef8f1f9 | 2015-04-29 16:05:23 -0400 | [diff] [blame] | 997 | common : { |
| 998 | tag : HARDWARE_MODULE_TAG, |
| 999 | version_major : 1, |
| 1000 | version_minor : 0, |
| 1001 | id : HWC_HARDWARE_MODULE_ID, |
| 1002 | name : "DRM hwcomposer module", |
| 1003 | author : "The Android Open Source Project", |
| 1004 | methods : &hwc_module_methods, |
| 1005 | dso : NULL, |
| 1006 | reserved : {0}, |
| 1007 | } |
Sean Paul | e0c4c3d | 2015-01-20 16:56:04 -0500 | [diff] [blame] | 1008 | }; |