blob: 628d343645b1be694f16edb6683d78a9848b7fcd [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040021
Sean Paule0c4c3d2015-01-20 16:56:04 -050022#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040023#include <fcntl.h>
Allen Martin3d3f70a2015-02-21 21:20:17 -080024#include <list>
Sean Paulef8f1f92015-04-29 16:05:23 -040025#include <pthread.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050026#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050027#include <sys/resource.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050028#include <xf86drm.h>
29#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050030
Sean Paulef8f1f92015-04-29 16:05:23 -040031#include <cutils/log.h>
32#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050033#include <hardware/hardware.h>
34#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050035#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040036#include <sync/sync.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050037
38#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
39
Sean Paule0c4c3d2015-01-20 16:56:04 -050040#define MAX_NUM_DISPLAYS 3
41#define UM_PER_INCH 25400
42
Sean Paul6a55e9f2015-04-30 15:31:06 -040043namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050044
Sean Paul9aa5ad32015-01-22 15:47:54 -050045struct hwc_worker {
Sean Paulef8f1f92015-04-29 16:05:23 -040046 pthread_t thread;
47 pthread_mutex_t lock;
48 pthread_cond_t cond;
49 bool exit;
Sean Paul9aa5ad32015-01-22 15:47:54 -050050};
51
Sean Paule0c4c3d2015-01-20 16:56:04 -050052struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -040053 struct hwc_context_t *ctx;
54 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -050055
Sean Paul6a55e9f2015-04-30 15:31:06 -040056 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -050057
Sean Paulef8f1f92015-04-29 16:05:23 -040058 struct hwc_worker set_worker;
Sean Paul9aa5ad32015-01-22 15:47:54 -050059
Sean Paulef8f1f92015-04-29 16:05:23 -040060 std::list<struct hwc_drm_bo> buf_queue;
61 struct hwc_drm_bo front;
62 pthread_mutex_t flip_lock;
63 pthread_cond_t flip_cond;
Sean Paulf1dc1912015-01-24 01:34:31 -050064
Sean Paulef8f1f92015-04-29 16:05:23 -040065 int timeline_fd;
66 unsigned timeline_next;
Sean Pauleb9e75c2015-01-25 23:31:30 -050067
Sean Paulef8f1f92015-04-29 16:05:23 -040068 bool enable_vsync_events;
69 unsigned int vsync_sequence;
Sean Paule0c4c3d2015-01-20 16:56:04 -050070};
71
72struct hwc_context_t {
Sean Paulef8f1f92015-04-29 16:05:23 -040073 hwc_composer_device_1_t device;
Sean Paule0c4c3d2015-01-20 16:56:04 -050074
Sean Paulef8f1f92015-04-29 16:05:23 -040075 hwc_procs_t const *procs;
76 struct hwc_import_context *import_ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -050077
Sean Paulef8f1f92015-04-29 16:05:23 -040078 struct hwc_drm_display displays[MAX_NUM_DISPLAYS];
79 int num_displays;
Sean Paul814bddb2015-03-03 17:46:19 -050080
Sean Paulef8f1f92015-04-29 16:05:23 -040081 struct hwc_worker event_worker;
Sean Paul6a55e9f2015-04-30 15:31:06 -040082
83 DrmResources drm;
Sean Paule0c4c3d2015-01-20 16:56:04 -050084};
85
86static int hwc_get_drm_display(struct hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -040087 struct hwc_drm_display **hd) {
88 if (display >= MAX_NUM_DISPLAYS) {
89 ALOGE("Requested display is out-of-bounds %d %d", display,
90 MAX_NUM_DISPLAYS);
91 return -EINVAL;
92 }
93 *hd = &ctx->displays[display];
94 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -050095}
96
Sean Paulef8f1f92015-04-29 16:05:23 -040097static int hwc_prepare_layer(hwc_layer_1_t *layer) {
98 /* TODO: We can't handle background right now, defer to sufaceFlinger */
99 if (layer->compositionType == HWC_BACKGROUND) {
100 layer->compositionType = HWC_FRAMEBUFFER;
101 ALOGV("Can't handle background layers yet");
Sean Paule0c4c3d2015-01-20 16:56:04 -0500102
Sean Paulef8f1f92015-04-29 16:05:23 -0400103 /* TODO: Support sideband compositions */
104 } else if (layer->compositionType == HWC_SIDEBAND) {
105 layer->compositionType = HWC_FRAMEBUFFER;
106 ALOGV("Can't handle sideband content yet");
107 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500108
Sean Paulef8f1f92015-04-29 16:05:23 -0400109 layer->hints = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500110
Sean Paulef8f1f92015-04-29 16:05:23 -0400111 /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */
112 if (layer->flags & HWC_IS_CURSOR_LAYER) {
113 ALOGV("Can't handle async cursors yet");
114 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500115
Sean Paulef8f1f92015-04-29 16:05:23 -0400116 /* TODO: Handle transformations */
117 if (layer->transform) {
118 ALOGV("Can't handle transformations yet");
119 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500120
Sean Paulef8f1f92015-04-29 16:05:23 -0400121 /* TODO: Handle blending & plane alpha*/
122 if (layer->blending == HWC_BLENDING_PREMULT ||
123 layer->blending == HWC_BLENDING_COVERAGE) {
124 ALOGV("Can't handle blending yet");
125 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500126
Sean Paulef8f1f92015-04-29 16:05:23 -0400127 /* TODO: Handle cropping & scaling */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500128
Sean Paulef8f1f92015-04-29 16:05:23 -0400129 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500130}
131
Sean Paulef8f1f92015-04-29 16:05:23 -0400132static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays,
133 hwc_display_contents_1_t **display_contents) {
134 /* TODO: Check flags for HWC_GEOMETRY_CHANGED */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500135
Sean Paulef8f1f92015-04-29 16:05:23 -0400136 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
137 if (!display_contents[i])
138 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500139
Sean Paulef8f1f92015-04-29 16:05:23 -0400140 for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) {
141 int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]);
142 if (ret) {
143 ALOGE("Failed to prepare layer %d:%d", j, i);
144 return ret;
145 }
146 }
147 }
Sean Pauldffca952015-02-04 10:19:55 -0800148
Sean Paulef8f1f92015-04-29 16:05:23 -0400149 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500150}
151
Sean Paulef8f1f92015-04-29 16:05:23 -0400152static int hwc_queue_vblank_event(struct hwc_drm_display *hd) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400153 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
154 if (!crtc) {
155 ALOGE("Failed to get crtc for display");
156 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400157 }
Sean Paul814bddb2015-03-03 17:46:19 -0500158
Sean Paulef8f1f92015-04-29 16:05:23 -0400159 drmVBlank vblank;
160 memset(&vblank, 0, sizeof(vblank));
Sean Paul814bddb2015-03-03 17:46:19 -0500161
Sean Paul6a55e9f2015-04-30 15:31:06 -0400162 uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT);
Sean Paulef8f1f92015-04-29 16:05:23 -0400163 vblank.request.type = (drmVBlankSeqType)(
164 DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT |
165 (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK));
166 vblank.request.signal = (unsigned long)hd;
167 vblank.request.sequence = hd->vsync_sequence + 1;
Sean Paul814bddb2015-03-03 17:46:19 -0500168
Sean Paul6a55e9f2015-04-30 15:31:06 -0400169 int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank);
Sean Paulef8f1f92015-04-29 16:05:23 -0400170 if (ret) {
171 ALOGE("Failed to wait for vblank %d", ret);
172 return ret;
173 }
Sean Paul814bddb2015-03-03 17:46:19 -0500174
Sean Paulef8f1f92015-04-29 16:05:23 -0400175 return 0;
Sean Paul814bddb2015-03-03 17:46:19 -0500176}
177
178static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence,
Sean Paulef8f1f92015-04-29 16:05:23 -0400179 unsigned int tv_sec, unsigned int tv_usec,
180 void *user_data) {
181 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500182
Sean Paulef8f1f92015-04-29 16:05:23 -0400183 if (!hd->enable_vsync_events || !hd->ctx->procs->vsync)
184 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500185
Sean Paulef8f1f92015-04-29 16:05:23 -0400186 /*
187 * Discard duplicate vsync (can happen when enabling vsync events while
188 * already processing vsyncs).
189 */
190 if (sequence <= hd->vsync_sequence)
191 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500192
Sean Paulef8f1f92015-04-29 16:05:23 -0400193 hd->vsync_sequence = sequence;
194 int ret = hwc_queue_vblank_event(hd);
195 if (ret)
196 ALOGE("Failed to queue vblank event ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500197
Sean Paulef8f1f92015-04-29 16:05:23 -0400198 int64_t timestamp =
199 (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000;
200 hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp);
Sean Paul814bddb2015-03-03 17:46:19 -0500201}
202
203static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */,
Sean Paulef8f1f92015-04-29 16:05:23 -0400204 unsigned int /* tv_sec */,
205 unsigned int /* tv_usec */,
206 void *user_data) {
207 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500208
Sean Paulef8f1f92015-04-29 16:05:23 -0400209 int ret = pthread_mutex_lock(&hd->flip_lock);
210 if (ret) {
211 ALOGE("Failed to lock flip lock ret=%d", ret);
212 return;
213 }
Sean Paul814bddb2015-03-03 17:46:19 -0500214
Sean Paulef8f1f92015-04-29 16:05:23 -0400215 ret = pthread_cond_signal(&hd->flip_cond);
216 if (ret)
217 ALOGE("Failed to signal flip condition ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500218
Sean Paulef8f1f92015-04-29 16:05:23 -0400219 ret = pthread_mutex_unlock(&hd->flip_lock);
220 if (ret) {
221 ALOGE("Failed to unlock flip lock ret=%d", ret);
222 return;
223 }
Sean Paul814bddb2015-03-03 17:46:19 -0500224}
225
Sean Paulef8f1f92015-04-29 16:05:23 -0400226static void *hwc_event_worker(void *arg) {
227 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul814bddb2015-03-03 17:46:19 -0500228
Sean Paulef8f1f92015-04-29 16:05:23 -0400229 struct hwc_context_t *ctx = (struct hwc_context_t *)arg;
230 do {
231 fd_set fds;
232 FD_ZERO(&fds);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400233 FD_SET(ctx->drm.fd(), &fds);
Sean Paul814bddb2015-03-03 17:46:19 -0500234
Sean Paulef8f1f92015-04-29 16:05:23 -0400235 drmEventContext event_context;
236 event_context.version = DRM_EVENT_CONTEXT_VERSION;
237 event_context.page_flip_handler = hwc_flip_event_handler;
238 event_context.vblank_handler = hwc_vblank_event_handler;
Sean Paul814bddb2015-03-03 17:46:19 -0500239
Sean Paulef8f1f92015-04-29 16:05:23 -0400240 int ret;
241 do {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400242 ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400243 } while (ret == -1 && errno == EINTR);
Sean Paul814bddb2015-03-03 17:46:19 -0500244
Sean Paulef8f1f92015-04-29 16:05:23 -0400245 if (ret != 1) {
246 ALOGE("Failed waiting for drm event\n");
247 continue;
248 }
Sean Paul814bddb2015-03-03 17:46:19 -0500249
Sean Paul6a55e9f2015-04-30 15:31:06 -0400250 drmHandleEvent(ctx->drm.fd(), &event_context);
Sean Paulef8f1f92015-04-29 16:05:23 -0400251 } while (true);
Sean Paul814bddb2015-03-03 17:46:19 -0500252
Sean Paulef8f1f92015-04-29 16:05:23 -0400253 return NULL;
Sean Paul814bddb2015-03-03 17:46:19 -0500254}
255
Sean Paulef8f1f92015-04-29 16:05:23 -0400256static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) {
257 return a->clock == b->clock && a->hdisplay == b->hdisplay &&
258 a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end &&
259 a->htotal == b->htotal && a->hskew == b->hskew &&
260 a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start &&
261 a->vsync_end == b->vsync_end && a->vtotal == b->vtotal &&
262 a->vscan == b->vscan && a->vrefresh == b->vrefresh &&
263 a->flags == b->flags && a->type == b->type &&
264 !strcmp(a->name, b->name);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500265}
266
Sean Paul6a55e9f2015-04-30 15:31:06 -0400267static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) {
268 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400269 if (!crtc) {
270 ALOGE("Failed to get crtc for display %d", hd->display);
271 return -ENODEV;
272 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800273
Sean Paul6a55e9f2015-04-30 15:31:06 -0400274 DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display);
275 if (!connector) {
276 ALOGE("Failed to get connector for display %d", hd->display);
277 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400278 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400279
280 int ret;
281 if (crtc->requires_modeset()) {
282 drmModeModeInfo drm_mode;
283 connector->active_mode().ToModeModeInfo(&drm_mode);
284 uint32_t connector_id = connector->id();
285 ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0,
286 &connector_id, 1, &drm_mode);
Sean Paulef8f1f92015-04-29 16:05:23 -0400287 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400288 ALOGE("Modeset failed for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400289 return ret;
290 }
291 return 0;
292 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500293
Sean Paul6a55e9f2015-04-30 15:31:06 -0400294 ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id,
Sean Paulef8f1f92015-04-29 16:05:23 -0400295 DRM_MODE_PAGE_FLIP_EVENT, hd);
296 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400297 ALOGE("Failed to flip buffer for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400298 return ret;
299 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500300
Sean Paulef8f1f92015-04-29 16:05:23 -0400301 ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock);
302 if (ret) {
303 ALOGE("Failed to wait on condition %d", ret);
304 return ret;
305 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500306
Sean Paulef8f1f92015-04-29 16:05:23 -0400307 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500308}
309
Sean Paul3bc48e82015-01-23 01:41:13 -0500310static int hwc_wait_and_set(struct hwc_drm_display *hd,
Sean Paulef8f1f92015-04-29 16:05:23 -0400311 struct hwc_drm_bo *buf) {
312 int ret;
313 if (buf->acquire_fence_fd >= 0) {
314 ret = sync_wait(buf->acquire_fence_fd, -1);
315 close(buf->acquire_fence_fd);
316 buf->acquire_fence_fd = -1;
317 if (ret) {
318 ALOGE("Failed to wait for acquire %d", ret);
319 return ret;
320 }
321 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500322
Sean Paulef8f1f92015-04-29 16:05:23 -0400323 ret = hwc_flip(hd, buf);
324 if (ret) {
325 ALOGE("Failed to perform flip\n");
326 return ret;
327 }
Lauri Peltonen132e0102015-02-12 13:54:33 +0200328
Sean Paul6a55e9f2015-04-30 15:31:06 -0400329 if (hwc_import_bo_release(hd->ctx->drm.fd(), hd->ctx->import_ctx,
330 &hd->front)) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400331 struct drm_gem_close args;
332 memset(&args, 0, sizeof(args));
333 for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) {
334 if (!hd->front.gem_handles[i])
335 continue;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500336
Sean Paulef8f1f92015-04-29 16:05:23 -0400337 ret = pthread_mutex_lock(&hd->set_worker.lock);
338 if (ret) {
339 ALOGE("Failed to lock set lock in wait_and_set() %d", ret);
340 continue;
341 }
Allen Martin3d3f70a2015-02-21 21:20:17 -0800342
Sean Paulef8f1f92015-04-29 16:05:23 -0400343 /* check for duplicate handle in buf_queue */
344 bool found = false;
345 for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin();
346 bi != hd->buf_queue.end(); ++bi)
347 for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j)
348 if (hd->front.gem_handles[i] == bi->gem_handles[j])
349 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800350
Sean Paulef8f1f92015-04-29 16:05:23 -0400351 for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j)
352 if (hd->front.gem_handles[i] == buf->gem_handles[j])
353 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800354
Sean Paulef8f1f92015-04-29 16:05:23 -0400355 if (!found) {
356 args.handle = hd->front.gem_handles[i];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400357 drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args);
Sean Paulef8f1f92015-04-29 16:05:23 -0400358 }
359 if (pthread_mutex_unlock(&hd->set_worker.lock))
360 ALOGE("Failed to unlock set lock in wait_and_set() %d", ret);
361 }
362 }
Lauri Peltonen77d6d7a2015-02-23 20:44:16 +0200363
Sean Paulef8f1f92015-04-29 16:05:23 -0400364 hd->front = *buf;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800365
Sean Paulef8f1f92015-04-29 16:05:23 -0400366 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500367}
368
Sean Paulef8f1f92015-04-29 16:05:23 -0400369static void *hwc_set_worker(void *arg) {
370 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500371
Sean Paulef8f1f92015-04-29 16:05:23 -0400372 struct hwc_drm_display *hd = (struct hwc_drm_display *)arg;
373 int ret = pthread_mutex_lock(&hd->flip_lock);
374 if (ret) {
375 ALOGE("Failed to lock flip lock ret=%d", ret);
376 return NULL;
377 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500378
Sean Paulef8f1f92015-04-29 16:05:23 -0400379 do {
380 ret = pthread_mutex_lock(&hd->set_worker.lock);
381 if (ret) {
382 ALOGE("Failed to lock set lock %d", ret);
383 return NULL;
384 }
Sean Paul814bddb2015-03-03 17:46:19 -0500385
Sean Paulef8f1f92015-04-29 16:05:23 -0400386 if (hd->set_worker.exit)
387 break;
Sean Paul3bc48e82015-01-23 01:41:13 -0500388
Sean Paulef8f1f92015-04-29 16:05:23 -0400389 if (hd->buf_queue.empty()) {
390 ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock);
391 if (ret) {
392 ALOGE("Failed to wait on condition %d", ret);
393 break;
394 }
395 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500396
Sean Paulef8f1f92015-04-29 16:05:23 -0400397 struct hwc_drm_bo buf;
398 buf = hd->buf_queue.front();
399 hd->buf_queue.pop_front();
Sean Paul3bc48e82015-01-23 01:41:13 -0500400
Sean Paulef8f1f92015-04-29 16:05:23 -0400401 ret = pthread_mutex_unlock(&hd->set_worker.lock);
402 if (ret) {
403 ALOGE("Failed to unlock set lock %d", ret);
404 return NULL;
405 }
Sean Paul3bc48e82015-01-23 01:41:13 -0500406
Sean Paulef8f1f92015-04-29 16:05:23 -0400407 ret = hwc_wait_and_set(hd, &buf);
408 if (ret)
409 ALOGE("Failed to wait and set %d", ret);
Sean Paul3bc48e82015-01-23 01:41:13 -0500410
Sean Paulef8f1f92015-04-29 16:05:23 -0400411 ret = sw_sync_timeline_inc(hd->timeline_fd, 1);
412 if (ret)
413 ALOGE("Failed to increment sync timeline %d", ret);
414 } while (true);
Sean Paul3bc48e82015-01-23 01:41:13 -0500415
Sean Paulef8f1f92015-04-29 16:05:23 -0400416 ret = pthread_mutex_unlock(&hd->set_worker.lock);
417 if (ret)
418 ALOGE("Failed to unlock set lock while exiting %d", ret);
Sean Paulf1dc1912015-01-24 01:34:31 -0500419
Sean Paulef8f1f92015-04-29 16:05:23 -0400420 ret = pthread_mutex_unlock(&hd->flip_lock);
421 if (ret)
422 ALOGE("Failed to unlock flip lock ret=%d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500423
Sean Paulef8f1f92015-04-29 16:05:23 -0400424 return NULL;
425}
Sean Paul9aa5ad32015-01-22 15:47:54 -0500426
Sean Paulef8f1f92015-04-29 16:05:23 -0400427static void hwc_close_fences(hwc_display_contents_1_t *display_contents) {
428 for (int i = 0; i < (int)display_contents->numHwLayers; ++i) {
429 hwc_layer_1_t *layer = &display_contents->hwLayers[i];
430 if (layer->acquireFenceFd >= 0) {
431 close(layer->acquireFenceFd);
432 layer->acquireFenceFd = -1;
433 }
434 }
435 if (display_contents->outbufAcquireFenceFd >= 0) {
436 close(display_contents->outbufAcquireFenceFd);
437 display_contents->outbufAcquireFenceFd = -1;
438 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500439}
440
Sean Paule0c4c3d2015-01-20 16:56:04 -0500441static int hwc_set_display(hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -0400442 hwc_display_contents_1_t *display_contents) {
443 struct hwc_drm_display *hd = NULL;
444 int ret = hwc_get_drm_display(ctx, display, &hd);
445 if (ret) {
446 hwc_close_fences(display_contents);
447 return ret;
448 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500449
Sean Paul6a55e9f2015-04-30 15:31:06 -0400450 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display);
451 if (!crtc) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400452 ALOGE("There is no active crtc for display %d", display);
453 hwc_close_fences(display_contents);
454 return -ENOENT;
455 }
Sean Paul9b1bb842015-01-23 01:11:58 -0500456
Sean Paulef8f1f92015-04-29 16:05:23 -0400457 /*
458 * TODO: We can only support one hw layer atm, so choose either the
459 * first one or the framebuffer target.
460 */
461 hwc_layer_1_t *layer = NULL;
462 if (!display_contents->numHwLayers) {
463 return 0;
464 } else if (display_contents->numHwLayers == 1) {
465 layer = &display_contents->hwLayers[0];
466 } else {
467 int i;
468 for (i = 0; i < (int)display_contents->numHwLayers; ++i) {
469 layer = &display_contents->hwLayers[i];
470 if (layer->compositionType == HWC_FRAMEBUFFER_TARGET)
471 break;
472 }
473 if (i == (int)display_contents->numHwLayers) {
474 ALOGE("Could not find a suitable layer for display %d", display);
475 }
476 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500477
Sean Paulef8f1f92015-04-29 16:05:23 -0400478 ret = pthread_mutex_lock(&hd->set_worker.lock);
479 if (ret) {
480 ALOGE("Failed to lock set lock in set() %d", ret);
481 hwc_close_fences(display_contents);
482 return ret;
483 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500484
Sean Paulef8f1f92015-04-29 16:05:23 -0400485 struct hwc_drm_bo buf;
486 memset(&buf, 0, sizeof(buf));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400487 ret =
488 hwc_import_bo_create(ctx->drm.fd(), ctx->import_ctx, layer->handle, &buf);
Sean Paulef8f1f92015-04-29 16:05:23 -0400489 if (ret) {
490 ALOGE("Failed to import handle to drm bo %d", ret);
491 hwc_close_fences(display_contents);
492 return ret;
493 }
494 buf.acquire_fence_fd = layer->acquireFenceFd;
495 layer->acquireFenceFd = -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500496
Sean Paulef8f1f92015-04-29 16:05:23 -0400497 /*
498 * TODO: Retire and release can use the same sync point here b/c hwc is
499 * restricted to one layer. Once that is no longer true, this will need
500 * to change
501 */
502 ++hd->timeline_next;
503 display_contents->retireFenceFd = sw_sync_fence_create(
504 hd->timeline_fd, "drm_hwc_retire", hd->timeline_next);
505 layer->releaseFenceFd = sw_sync_fence_create(
506 hd->timeline_fd, "drm_hwc_release", hd->timeline_next);
507 hd->buf_queue.push_back(buf);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800508
Sean Paulef8f1f92015-04-29 16:05:23 -0400509 ret = pthread_cond_signal(&hd->set_worker.cond);
510 if (ret)
511 ALOGE("Failed to signal set worker %d", ret);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800512
Sean Paulef8f1f92015-04-29 16:05:23 -0400513 if (pthread_mutex_unlock(&hd->set_worker.lock))
514 ALOGE("Failed to unlock set lock in set()");
Sean Paul3bc48e82015-01-23 01:41:13 -0500515
Sean Paulef8f1f92015-04-29 16:05:23 -0400516 hwc_close_fences(display_contents);
517 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500518}
519
520static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400521 hwc_display_contents_1_t **display_contents) {
522 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500523
Sean Paulef8f1f92015-04-29 16:05:23 -0400524 int ret = 0;
525 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
526 if (display_contents[i])
527 ret = hwc_set_display(ctx, i, display_contents[i]);
528 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500529
Sean Paulef8f1f92015-04-29 16:05:23 -0400530 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500531}
532
Sean Paulef8f1f92015-04-29 16:05:23 -0400533static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
534 int event, int enabled) {
535 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
536 struct hwc_drm_display *hd = NULL;
537 int ret = hwc_get_drm_display(ctx, display, &hd);
538 if (ret)
539 return ret;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500540
Sean Paulef8f1f92015-04-29 16:05:23 -0400541 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
542 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500543
Sean Paul6a55e9f2015-04-30 15:31:06 -0400544 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display);
545 if (!crtc) {
546 ALOGD("Can't service events for display %d, no crtc", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400547 return -EINVAL;
548 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500549
Sean Paulef8f1f92015-04-29 16:05:23 -0400550 hd->enable_vsync_events = !!enabled;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500551
Sean Paulef8f1f92015-04-29 16:05:23 -0400552 if (!hd->enable_vsync_events)
553 return 0;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500554
Sean Paulef8f1f92015-04-29 16:05:23 -0400555 /*
556 * Note that it's possible that the event worker is already waiting for
557 * a vsync, and this will be a duplicate request. In that event, we'll
558 * end up firing the event handler twice, and it will discard the second
559 * event. Not ideal, but not worth introducing a bunch of additional
560 * logic/locks/state for.
561 */
562 ret = hwc_queue_vblank_event(hd);
563 if (ret) {
564 ALOGE("Failed to queue vblank event ret=%d", ret);
565 return ret;
566 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500567
Sean Paulef8f1f92015-04-29 16:05:23 -0400568 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500569}
570
Sean Paulef8f1f92015-04-29 16:05:23 -0400571static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
572 int mode) {
573 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500574
Sean Paul6a55e9f2015-04-30 15:31:06 -0400575 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400576 switch (mode) {
577 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400578 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400579 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500580
Sean Paulef8f1f92015-04-29 16:05:23 -0400581 /* We can't support dozing right now, so go full on */
582 case HWC_POWER_MODE_DOZE:
583 case HWC_POWER_MODE_DOZE_SUSPEND:
584 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400585 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400586 break;
587 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400588 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500589}
590
Sean Paulef8f1f92015-04-29 16:05:23 -0400591static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
592 int *value) {
593 switch (what) {
594 case HWC_BACKGROUND_LAYER_SUPPORTED:
595 *value = 0; /* TODO: We should do this */
596 break;
597 case HWC_VSYNC_PERIOD:
598 ALOGW("Query for deprecated vsync value, returning 60Hz");
599 *value = 1000 * 1000 * 1000 / 60;
600 break;
601 case HWC_DISPLAY_TYPES_SUPPORTED:
602 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
603 break;
604 }
605 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500606}
607
Sean Paulef8f1f92015-04-29 16:05:23 -0400608static void hwc_register_procs(struct hwc_composer_device_1 *dev,
609 hwc_procs_t const *procs) {
610 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500611
Sean Paulef8f1f92015-04-29 16:05:23 -0400612 ctx->procs = procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500613}
614
Sean Paulef8f1f92015-04-29 16:05:23 -0400615static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
616 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400617 size_t *num_configs) {
618 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400619 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500620
Sean Paulef8f1f92015-04-29 16:05:23 -0400621 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
622 struct hwc_drm_display *hd = NULL;
623 int ret = hwc_get_drm_display(ctx, display, &hd);
624 if (ret)
625 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500626
Sean Paul6a55e9f2015-04-30 15:31:06 -0400627 hd->config_ids.clear();
628
629 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
630 if (!connector) {
631 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400632 return -ENODEV;
633 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500634
Sean Paul6a55e9f2015-04-30 15:31:06 -0400635 ret = connector->UpdateModes();
636 if (ret) {
637 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400638 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400639 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500640
Sean Paul6a55e9f2015-04-30 15:31:06 -0400641 for (DrmConnector::ModeIter iter = connector->begin_modes();
642 iter != connector->end_modes(); ++iter) {
643 size_t idx = hd->config_ids.size();
644 if (idx == *num_configs)
645 break;
646 hd->config_ids.push_back(iter->id());
647 configs[idx] = iter->id();
648 }
649 *num_configs = hd->config_ids.size();
650 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500651}
652
Sean Paulef8f1f92015-04-29 16:05:23 -0400653static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
654 int display, uint32_t config,
655 const uint32_t *attributes,
656 int32_t *values) {
657 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400658 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400659 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400660 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400661 return -ENODEV;
662 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400663 DrmMode mode;
664 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
665 ++iter) {
666 if (iter->id() == config) {
667 mode = *iter;
668 break;
669 }
670 }
671 if (mode.id() == 0) {
672 ALOGE("Failed to find active mode for display %d", display);
673 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400674 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500675
Sean Paul6a55e9f2015-04-30 15:31:06 -0400676 uint32_t mm_width = c->mm_width();
677 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400678 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
679 switch (attributes[i]) {
680 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400681 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400682 break;
683 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400684 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400685 break;
686 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400687 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400688 break;
689 case HWC_DISPLAY_DPI_X:
690 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400691 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400692 break;
693 case HWC_DISPLAY_DPI_Y:
694 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400695 values[i] =
696 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400697 break;
698 }
699 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400700 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500701}
702
Sean Paulef8f1f92015-04-29 16:05:23 -0400703static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
704 int display) {
705 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
706 struct hwc_drm_display *hd = NULL;
707 int ret = hwc_get_drm_display(ctx, display, &hd);
708 if (ret)
709 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500710
Sean Paul6a55e9f2015-04-30 15:31:06 -0400711 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
712 if (!c) {
713 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400714 return -ENODEV;
715 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500716
Sean Paul6a55e9f2015-04-30 15:31:06 -0400717 DrmMode mode = c->active_mode();
718 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
719 if (hd->config_ids[i] == mode.id())
720 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400721 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400722 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500723}
724
Sean Paulef8f1f92015-04-29 16:05:23 -0400725static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
726 int index) {
727 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
728 struct hwc_drm_display *hd = NULL;
729 int ret = hwc_get_drm_display(ctx, display, &hd);
730 if (ret)
731 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500732
Sean Paul6a55e9f2015-04-30 15:31:06 -0400733 if (index >= (int)hd->config_ids.size()) {
734 ALOGE("Invalid config index %d passed in", index);
735 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400736 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500737
Sean Paul6a55e9f2015-04-30 15:31:06 -0400738 ret =
739 ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
740 if (ret) {
741 ALOGE("Failed to set config for display %d", display);
742 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400743 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500744
Sean Paul6a55e9f2015-04-30 15:31:06 -0400745 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500746}
747
Sean Paulef8f1f92015-04-29 16:05:23 -0400748static int hwc_destroy_worker(struct hwc_worker *worker) {
749 int ret = pthread_mutex_lock(&worker->lock);
750 if (ret) {
751 ALOGE("Failed to lock in destroy() %d", ret);
752 return ret;
753 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500754
Sean Paulef8f1f92015-04-29 16:05:23 -0400755 worker->exit = true;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500756
Sean Paulef8f1f92015-04-29 16:05:23 -0400757 ret |= pthread_cond_signal(&worker->cond);
758 if (ret)
759 ALOGE("Failed to signal cond in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500760
Sean Paulef8f1f92015-04-29 16:05:23 -0400761 ret |= pthread_mutex_unlock(&worker->lock);
762 if (ret)
763 ALOGE("Failed to unlock in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500764
Sean Paulef8f1f92015-04-29 16:05:23 -0400765 ret |= pthread_join(worker->thread, NULL);
766 if (ret && ret != ESRCH)
767 ALOGE("Failed to join thread in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500768
Sean Paulef8f1f92015-04-29 16:05:23 -0400769 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500770}
771
Sean Paulef8f1f92015-04-29 16:05:23 -0400772static void hwc_destroy_display(struct hwc_drm_display *hd) {
773 if (hwc_destroy_worker(&hd->set_worker))
774 ALOGE("Destroy set worker failed");
Sean Paul9aa5ad32015-01-22 15:47:54 -0500775}
776
Sean Paulef8f1f92015-04-29 16:05:23 -0400777static int hwc_device_close(struct hw_device_t *dev) {
778 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500779
Sean Paulef8f1f92015-04-29 16:05:23 -0400780 for (int i = 0; i < MAX_NUM_DISPLAYS; ++i)
781 hwc_destroy_display(&ctx->displays[i]);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500782
Sean Paulef8f1f92015-04-29 16:05:23 -0400783 if (hwc_destroy_worker(&ctx->event_worker))
784 ALOGE("Destroy event worker failed");
Sean Paul814bddb2015-03-03 17:46:19 -0500785
Sean Paulef8f1f92015-04-29 16:05:23 -0400786 int ret = hwc_import_destroy(ctx->import_ctx);
787 if (ret)
788 ALOGE("Could not destroy import %d", ret);
Sean Paulcd36a9e2015-01-22 18:01:18 -0500789
Sean Paulef8f1f92015-04-29 16:05:23 -0400790 delete ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500791
Sean Paulef8f1f92015-04-29 16:05:23 -0400792 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500793}
794
Sean Paul814bddb2015-03-03 17:46:19 -0500795static int hwc_initialize_worker(struct hwc_worker *worker,
Sean Paulef8f1f92015-04-29 16:05:23 -0400796 void *(*routine)(void *), void *arg) {
797 int ret = pthread_cond_init(&worker->cond, NULL);
798 if (ret) {
799 ALOGE("Failed to create worker condition %d", ret);
800 return ret;
801 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500802
Sean Paulef8f1f92015-04-29 16:05:23 -0400803 ret = pthread_mutex_init(&worker->lock, NULL);
804 if (ret) {
805 ALOGE("Failed to initialize worker lock %d", ret);
806 pthread_cond_destroy(&worker->cond);
807 return ret;
808 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500809
Sean Paulef8f1f92015-04-29 16:05:23 -0400810 worker->exit = false;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500811
Sean Paulef8f1f92015-04-29 16:05:23 -0400812 ret = pthread_create(&worker->thread, NULL, routine, arg);
813 if (ret) {
814 ALOGE("Could not create worker thread %d", ret);
815 pthread_mutex_destroy(&worker->lock);
816 pthread_cond_destroy(&worker->cond);
817 return ret;
818 }
819 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500820}
821
Sean Paul24a26e32015-02-04 10:34:47 -0800822/*
823 * TODO: This function sets the active config to the first one in the list. This
824 * should be fixed such that it selects the preferred mode for the display, or
825 * some other, saner, method of choosing the config.
826 */
Sean Paulef8f1f92015-04-29 16:05:23 -0400827static int hwc_set_initial_config(struct hwc_drm_display *hd) {
828 uint32_t config;
829 size_t num_configs = 1;
830 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
831 &num_configs);
832 if (ret || !num_configs)
833 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800834
Sean Paulef8f1f92015-04-29 16:05:23 -0400835 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
836 if (ret) {
837 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
838 return ret;
839 }
Sean Paul24a26e32015-02-04 10:34:47 -0800840
Sean Paulef8f1f92015-04-29 16:05:23 -0400841 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800842}
843
Sean Paul6a55e9f2015-04-30 15:31:06 -0400844static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400845 struct hwc_drm_display *hd = NULL;
846 int ret = hwc_get_drm_display(ctx, display, &hd);
847 if (ret)
848 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500849
Sean Paulef8f1f92015-04-29 16:05:23 -0400850 hd->ctx = ctx;
851 hd->display = display;
Sean Paulef8f1f92015-04-29 16:05:23 -0400852 hd->enable_vsync_events = false;
853 hd->vsync_sequence = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500854
Sean Paulef8f1f92015-04-29 16:05:23 -0400855 ret = pthread_mutex_init(&hd->flip_lock, NULL);
856 if (ret) {
857 ALOGE("Failed to initialize flip lock %d", ret);
858 return ret;
859 }
Sean Paul814bddb2015-03-03 17:46:19 -0500860
Sean Paulef8f1f92015-04-29 16:05:23 -0400861 ret = pthread_cond_init(&hd->flip_cond, NULL);
862 if (ret) {
863 ALOGE("Failed to intiialize flip condition %d", ret);
864 pthread_mutex_destroy(&hd->flip_lock);
865 return ret;
866 }
Sean Paul814bddb2015-03-03 17:46:19 -0500867
Sean Paulef8f1f92015-04-29 16:05:23 -0400868 ret = sw_sync_timeline_create();
869 if (ret < 0) {
870 ALOGE("Failed to create sw sync timeline %d", ret);
871 pthread_cond_destroy(&hd->flip_cond);
872 pthread_mutex_destroy(&hd->flip_lock);
873 return ret;
874 }
875 hd->timeline_fd = ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500876
Sean Paulef8f1f92015-04-29 16:05:23 -0400877 /*
878 * Initialize timeline_next to 1, because point 0 will be the very first
879 * set operation. Since we increment every time set() is called,
880 * initializing to 0 would cause an off-by-one error where
881 * surfaceflinger would composite on the front buffer.
882 */
883 hd->timeline_next = 1;
Sean Paule147a2a2015-02-22 17:55:43 -0500884
Sean Paulef8f1f92015-04-29 16:05:23 -0400885 ret = hwc_set_initial_config(hd);
886 if (ret) {
887 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
888 close(hd->timeline_fd);
889 pthread_cond_destroy(&hd->flip_cond);
890 pthread_mutex_destroy(&hd->flip_lock);
891 return ret;
892 }
Sean Paulf1dc1912015-01-24 01:34:31 -0500893
Sean Paulef8f1f92015-04-29 16:05:23 -0400894 ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd);
895 if (ret) {
896 ALOGE("Failed to create set worker %d\n", ret);
897 close(hd->timeline_fd);
898 pthread_cond_destroy(&hd->flip_cond);
899 pthread_mutex_destroy(&hd->flip_lock);
900 return ret;
901 }
Sean Paul24a26e32015-02-04 10:34:47 -0800902
Sean Paulef8f1f92015-04-29 16:05:23 -0400903 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500904}
905
Sean Paulef8f1f92015-04-29 16:05:23 -0400906static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) {
907 for (int i = 0; i < num_conn; ++i) {
908 if (conn_list[i])
909 drmModeFreeConnector(conn_list[i]);
910 }
911 free(conn_list);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500912}
913
Sean Paulef8f1f92015-04-29 16:05:23 -0400914static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400915 int ret;
916 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
917 c != ctx->drm.end_connectors(); ++c) {
918 ret = hwc_initialize_display(ctx, (*c)->display());
919 if (ret) {
920 ALOGE("Failed to initialize display %d", (*c)->display());
921 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400922 }
923 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400924
925 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500926}
927
Sean Paulef8f1f92015-04-29 16:05:23 -0400928static int hwc_device_open(const struct hw_module_t *module, const char *name,
929 struct hw_device_t **dev) {
930 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
931 ALOGE("Invalid module name- %s", name);
932 return -EINVAL;
933 }
934
935 struct hwc_context_t *ctx = new hwc_context_t();
936 if (!ctx) {
937 ALOGE("Failed to allocate hwc context");
938 return -ENOMEM;
939 }
940
Sean Paul6a55e9f2015-04-30 15:31:06 -0400941 int ret = ctx->drm.Init();
942 if (ret) {
943 ALOGE("Can't initialize Drm object %d", ret);
944 delete ctx;
945 return ret;
946 }
947
948 ret = hwc_import_init(&ctx->import_ctx);
Sean Paulef8f1f92015-04-29 16:05:23 -0400949 if (ret) {
950 ALOGE("Failed to initialize import context");
951 delete ctx;
952 return ret;
953 }
954
Sean Paulef8f1f92015-04-29 16:05:23 -0400955 ret = hwc_enumerate_displays(ctx);
956 if (ret) {
957 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400958 delete ctx;
959 return ret;
960 }
961
962 ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx);
963 if (ret) {
964 ALOGE("Failed to create event worker %d\n", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400965 delete ctx;
966 return ret;
967 }
968
969 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
970 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
971 ctx->device.common.module = const_cast<hw_module_t *>(module);
972 ctx->device.common.close = hwc_device_close;
973
974 ctx->device.prepare = hwc_prepare;
975 ctx->device.set = hwc_set;
976 ctx->device.eventControl = hwc_event_control;
977 ctx->device.setPowerMode = hwc_set_power_mode;
978 ctx->device.query = hwc_query;
979 ctx->device.registerProcs = hwc_register_procs;
980 ctx->device.getDisplayConfigs = hwc_get_display_configs;
981 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
982 ctx->device.getActiveConfig = hwc_get_active_config;
983 ctx->device.setActiveConfig = hwc_set_active_config;
984 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
985
986 *dev = &ctx->device.common;
987
988 return 0;
989}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400990}
Sean Paulef8f1f92015-04-29 16:05:23 -0400991
Sean Paul6a55e9f2015-04-30 15:31:06 -0400992static struct hw_module_methods_t hwc_module_methods = {
993 open : android::hwc_device_open
994};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500995
996hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -0400997 common : {
998 tag : HARDWARE_MODULE_TAG,
999 version_major : 1,
1000 version_minor : 0,
1001 id : HWC_HARDWARE_MODULE_ID,
1002 name : "DRM hwcomposer module",
1003 author : "The Android Open Source Project",
1004 methods : &hwc_module_methods,
1005 dso : NULL,
1006 reserved : {0},
1007 }
Sean Paule0c4c3d2015-01-20 16:56:04 -05001008};