blob: b91323fbf3e36c1dbe8a0391a528f69baae9805a [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040021
Sean Paule0c4c3d2015-01-20 16:56:04 -050022#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040023#include <fcntl.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040024#include <pthread.h>
Dan Albertc5255b32015-05-07 23:42:54 -070025#include <stdlib.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050026#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050027#include <sys/resource.h>
Dan Albertc5255b32015-05-07 23:42:54 -070028
29#include <list>
30
Sean Paule0c4c3d2015-01-20 16:56:04 -050031#include <xf86drm.h>
32#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050033
Sean Paulef8f1f92015-04-29 16:05:23 -040034#include <cutils/log.h>
35#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050036#include <hardware/hardware.h>
37#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050038#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040039#include <sync/sync.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050040
41#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
42
Sean Paule0c4c3d2015-01-20 16:56:04 -050043#define MAX_NUM_DISPLAYS 3
44#define UM_PER_INCH 25400
45
Sean Paul6a55e9f2015-04-30 15:31:06 -040046namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050047
Sean Paul9aa5ad32015-01-22 15:47:54 -050048struct hwc_worker {
Sean Paulef8f1f92015-04-29 16:05:23 -040049 pthread_t thread;
50 pthread_mutex_t lock;
51 pthread_cond_t cond;
52 bool exit;
Sean Paul9aa5ad32015-01-22 15:47:54 -050053};
54
Sean Paule0c4c3d2015-01-20 16:56:04 -050055struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -040056 struct hwc_context_t *ctx;
57 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -050058
Sean Paul6a55e9f2015-04-30 15:31:06 -040059 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -050060
Sean Paulef8f1f92015-04-29 16:05:23 -040061 struct hwc_worker set_worker;
Sean Paul9aa5ad32015-01-22 15:47:54 -050062
Sean Paulef8f1f92015-04-29 16:05:23 -040063 std::list<struct hwc_drm_bo> buf_queue;
64 struct hwc_drm_bo front;
65 pthread_mutex_t flip_lock;
66 pthread_cond_t flip_cond;
Sean Paulf1dc1912015-01-24 01:34:31 -050067
Sean Paulef8f1f92015-04-29 16:05:23 -040068 int timeline_fd;
69 unsigned timeline_next;
Sean Pauleb9e75c2015-01-25 23:31:30 -050070
Sean Paulef8f1f92015-04-29 16:05:23 -040071 bool enable_vsync_events;
72 unsigned int vsync_sequence;
Sean Paule0c4c3d2015-01-20 16:56:04 -050073};
74
75struct hwc_context_t {
Sean Paulef8f1f92015-04-29 16:05:23 -040076 hwc_composer_device_1_t device;
Sean Paule0c4c3d2015-01-20 16:56:04 -050077
Sean Paulef8f1f92015-04-29 16:05:23 -040078 hwc_procs_t const *procs;
79 struct hwc_import_context *import_ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -050080
Sean Paulef8f1f92015-04-29 16:05:23 -040081 struct hwc_drm_display displays[MAX_NUM_DISPLAYS];
82 int num_displays;
Sean Paul814bddb2015-03-03 17:46:19 -050083
Sean Paulef8f1f92015-04-29 16:05:23 -040084 struct hwc_worker event_worker;
Sean Paul6a55e9f2015-04-30 15:31:06 -040085
86 DrmResources drm;
Sean Paule0c4c3d2015-01-20 16:56:04 -050087};
88
89static int hwc_get_drm_display(struct hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -040090 struct hwc_drm_display **hd) {
91 if (display >= MAX_NUM_DISPLAYS) {
92 ALOGE("Requested display is out-of-bounds %d %d", display,
93 MAX_NUM_DISPLAYS);
94 return -EINVAL;
95 }
96 *hd = &ctx->displays[display];
97 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -050098}
99
Sean Paulef8f1f92015-04-29 16:05:23 -0400100static int hwc_prepare_layer(hwc_layer_1_t *layer) {
101 /* TODO: We can't handle background right now, defer to sufaceFlinger */
102 if (layer->compositionType == HWC_BACKGROUND) {
103 layer->compositionType = HWC_FRAMEBUFFER;
104 ALOGV("Can't handle background layers yet");
Sean Paule0c4c3d2015-01-20 16:56:04 -0500105
Sean Paulef8f1f92015-04-29 16:05:23 -0400106 /* TODO: Support sideband compositions */
107 } else if (layer->compositionType == HWC_SIDEBAND) {
108 layer->compositionType = HWC_FRAMEBUFFER;
109 ALOGV("Can't handle sideband content yet");
110 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500111
Sean Paulef8f1f92015-04-29 16:05:23 -0400112 layer->hints = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500113
Sean Paulef8f1f92015-04-29 16:05:23 -0400114 /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */
115 if (layer->flags & HWC_IS_CURSOR_LAYER) {
116 ALOGV("Can't handle async cursors yet");
117 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500118
Sean Paulef8f1f92015-04-29 16:05:23 -0400119 /* TODO: Handle transformations */
120 if (layer->transform) {
121 ALOGV("Can't handle transformations yet");
122 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500123
Sean Paulef8f1f92015-04-29 16:05:23 -0400124 /* TODO: Handle blending & plane alpha*/
125 if (layer->blending == HWC_BLENDING_PREMULT ||
126 layer->blending == HWC_BLENDING_COVERAGE) {
127 ALOGV("Can't handle blending yet");
128 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500129
Sean Paulef8f1f92015-04-29 16:05:23 -0400130 /* TODO: Handle cropping & scaling */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500131
Sean Paulef8f1f92015-04-29 16:05:23 -0400132 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500133}
134
Sean Paulef8f1f92015-04-29 16:05:23 -0400135static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays,
136 hwc_display_contents_1_t **display_contents) {
137 /* TODO: Check flags for HWC_GEOMETRY_CHANGED */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500138
Sean Paulef8f1f92015-04-29 16:05:23 -0400139 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
140 if (!display_contents[i])
141 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500142
Sean Paulef8f1f92015-04-29 16:05:23 -0400143 for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) {
144 int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]);
145 if (ret) {
146 ALOGE("Failed to prepare layer %d:%d", j, i);
147 return ret;
148 }
149 }
150 }
Sean Pauldffca952015-02-04 10:19:55 -0800151
Sean Paulef8f1f92015-04-29 16:05:23 -0400152 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500153}
154
Sean Paulef8f1f92015-04-29 16:05:23 -0400155static int hwc_queue_vblank_event(struct hwc_drm_display *hd) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400156 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
157 if (!crtc) {
158 ALOGE("Failed to get crtc for display");
159 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400160 }
Sean Paul814bddb2015-03-03 17:46:19 -0500161
Sean Paulef8f1f92015-04-29 16:05:23 -0400162 drmVBlank vblank;
163 memset(&vblank, 0, sizeof(vblank));
Sean Paul814bddb2015-03-03 17:46:19 -0500164
Sean Paul6a55e9f2015-04-30 15:31:06 -0400165 uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT);
Sean Paulef8f1f92015-04-29 16:05:23 -0400166 vblank.request.type = (drmVBlankSeqType)(
167 DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT |
168 (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK));
169 vblank.request.signal = (unsigned long)hd;
170 vblank.request.sequence = hd->vsync_sequence + 1;
Sean Paul814bddb2015-03-03 17:46:19 -0500171
Sean Paul6a55e9f2015-04-30 15:31:06 -0400172 int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank);
Sean Paulef8f1f92015-04-29 16:05:23 -0400173 if (ret) {
174 ALOGE("Failed to wait for vblank %d", ret);
175 return ret;
176 }
Sean Paul814bddb2015-03-03 17:46:19 -0500177
Sean Paulef8f1f92015-04-29 16:05:23 -0400178 return 0;
Sean Paul814bddb2015-03-03 17:46:19 -0500179}
180
181static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence,
Sean Paulef8f1f92015-04-29 16:05:23 -0400182 unsigned int tv_sec, unsigned int tv_usec,
183 void *user_data) {
184 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500185
Sean Paulef8f1f92015-04-29 16:05:23 -0400186 if (!hd->enable_vsync_events || !hd->ctx->procs->vsync)
187 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500188
Sean Paulef8f1f92015-04-29 16:05:23 -0400189 /*
190 * Discard duplicate vsync (can happen when enabling vsync events while
191 * already processing vsyncs).
192 */
193 if (sequence <= hd->vsync_sequence)
194 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500195
Sean Paulef8f1f92015-04-29 16:05:23 -0400196 hd->vsync_sequence = sequence;
197 int ret = hwc_queue_vblank_event(hd);
198 if (ret)
199 ALOGE("Failed to queue vblank event ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500200
Sean Paulef8f1f92015-04-29 16:05:23 -0400201 int64_t timestamp =
202 (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000;
203 hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp);
Sean Paul814bddb2015-03-03 17:46:19 -0500204}
205
206static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */,
Sean Paulef8f1f92015-04-29 16:05:23 -0400207 unsigned int /* tv_sec */,
208 unsigned int /* tv_usec */,
209 void *user_data) {
210 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500211
Sean Paulef8f1f92015-04-29 16:05:23 -0400212 int ret = pthread_mutex_lock(&hd->flip_lock);
213 if (ret) {
214 ALOGE("Failed to lock flip lock ret=%d", ret);
215 return;
216 }
Sean Paul814bddb2015-03-03 17:46:19 -0500217
Sean Paulef8f1f92015-04-29 16:05:23 -0400218 ret = pthread_cond_signal(&hd->flip_cond);
219 if (ret)
220 ALOGE("Failed to signal flip condition ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500221
Sean Paulef8f1f92015-04-29 16:05:23 -0400222 ret = pthread_mutex_unlock(&hd->flip_lock);
223 if (ret) {
224 ALOGE("Failed to unlock flip lock ret=%d", ret);
225 return;
226 }
Sean Paul814bddb2015-03-03 17:46:19 -0500227}
228
Sean Paulef8f1f92015-04-29 16:05:23 -0400229static void *hwc_event_worker(void *arg) {
230 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul814bddb2015-03-03 17:46:19 -0500231
Sean Paulef8f1f92015-04-29 16:05:23 -0400232 struct hwc_context_t *ctx = (struct hwc_context_t *)arg;
233 do {
234 fd_set fds;
235 FD_ZERO(&fds);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400236 FD_SET(ctx->drm.fd(), &fds);
Sean Paul814bddb2015-03-03 17:46:19 -0500237
Sean Paulef8f1f92015-04-29 16:05:23 -0400238 drmEventContext event_context;
239 event_context.version = DRM_EVENT_CONTEXT_VERSION;
240 event_context.page_flip_handler = hwc_flip_event_handler;
241 event_context.vblank_handler = hwc_vblank_event_handler;
Sean Paul814bddb2015-03-03 17:46:19 -0500242
Sean Paulef8f1f92015-04-29 16:05:23 -0400243 int ret;
244 do {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400245 ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400246 } while (ret == -1 && errno == EINTR);
Sean Paul814bddb2015-03-03 17:46:19 -0500247
Sean Paulef8f1f92015-04-29 16:05:23 -0400248 if (ret != 1) {
249 ALOGE("Failed waiting for drm event\n");
250 continue;
251 }
Sean Paul814bddb2015-03-03 17:46:19 -0500252
Sean Paul6a55e9f2015-04-30 15:31:06 -0400253 drmHandleEvent(ctx->drm.fd(), &event_context);
Sean Paulef8f1f92015-04-29 16:05:23 -0400254 } while (true);
Sean Paul814bddb2015-03-03 17:46:19 -0500255
Sean Paulef8f1f92015-04-29 16:05:23 -0400256 return NULL;
Sean Paul814bddb2015-03-03 17:46:19 -0500257}
258
Sean Paulef8f1f92015-04-29 16:05:23 -0400259static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) {
260 return a->clock == b->clock && a->hdisplay == b->hdisplay &&
261 a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end &&
262 a->htotal == b->htotal && a->hskew == b->hskew &&
263 a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start &&
264 a->vsync_end == b->vsync_end && a->vtotal == b->vtotal &&
265 a->vscan == b->vscan && a->vrefresh == b->vrefresh &&
266 a->flags == b->flags && a->type == b->type &&
267 !strcmp(a->name, b->name);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500268}
269
Sean Paul6a55e9f2015-04-30 15:31:06 -0400270static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) {
271 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400272 if (!crtc) {
273 ALOGE("Failed to get crtc for display %d", hd->display);
274 return -ENODEV;
275 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800276
Sean Paul6a55e9f2015-04-30 15:31:06 -0400277 DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display);
278 if (!connector) {
279 ALOGE("Failed to get connector for display %d", hd->display);
280 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400281 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400282
283 int ret;
284 if (crtc->requires_modeset()) {
285 drmModeModeInfo drm_mode;
286 connector->active_mode().ToModeModeInfo(&drm_mode);
287 uint32_t connector_id = connector->id();
288 ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0,
289 &connector_id, 1, &drm_mode);
Sean Paulef8f1f92015-04-29 16:05:23 -0400290 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400291 ALOGE("Modeset failed for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400292 return ret;
293 }
294 return 0;
295 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500296
Sean Paul6a55e9f2015-04-30 15:31:06 -0400297 ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id,
Sean Paulef8f1f92015-04-29 16:05:23 -0400298 DRM_MODE_PAGE_FLIP_EVENT, hd);
299 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400300 ALOGE("Failed to flip buffer for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400301 return ret;
302 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500303
Sean Paulef8f1f92015-04-29 16:05:23 -0400304 ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock);
305 if (ret) {
306 ALOGE("Failed to wait on condition %d", ret);
307 return ret;
308 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500309
Sean Paulef8f1f92015-04-29 16:05:23 -0400310 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500311}
312
Sean Paul3bc48e82015-01-23 01:41:13 -0500313static int hwc_wait_and_set(struct hwc_drm_display *hd,
Sean Paulef8f1f92015-04-29 16:05:23 -0400314 struct hwc_drm_bo *buf) {
315 int ret;
316 if (buf->acquire_fence_fd >= 0) {
317 ret = sync_wait(buf->acquire_fence_fd, -1);
318 close(buf->acquire_fence_fd);
319 buf->acquire_fence_fd = -1;
320 if (ret) {
321 ALOGE("Failed to wait for acquire %d", ret);
322 return ret;
323 }
324 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500325
Sean Paulef8f1f92015-04-29 16:05:23 -0400326 ret = hwc_flip(hd, buf);
327 if (ret) {
328 ALOGE("Failed to perform flip\n");
329 return ret;
330 }
Lauri Peltonen132e0102015-02-12 13:54:33 +0200331
Sean Paul6a55e9f2015-04-30 15:31:06 -0400332 if (hwc_import_bo_release(hd->ctx->drm.fd(), hd->ctx->import_ctx,
333 &hd->front)) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400334 struct drm_gem_close args;
335 memset(&args, 0, sizeof(args));
336 for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) {
337 if (!hd->front.gem_handles[i])
338 continue;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500339
Sean Paulef8f1f92015-04-29 16:05:23 -0400340 ret = pthread_mutex_lock(&hd->set_worker.lock);
341 if (ret) {
342 ALOGE("Failed to lock set lock in wait_and_set() %d", ret);
343 continue;
344 }
Allen Martin3d3f70a2015-02-21 21:20:17 -0800345
Sean Paulef8f1f92015-04-29 16:05:23 -0400346 /* check for duplicate handle in buf_queue */
347 bool found = false;
348 for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin();
349 bi != hd->buf_queue.end(); ++bi)
350 for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j)
351 if (hd->front.gem_handles[i] == bi->gem_handles[j])
352 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800353
Sean Paulef8f1f92015-04-29 16:05:23 -0400354 for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j)
355 if (hd->front.gem_handles[i] == buf->gem_handles[j])
356 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800357
Sean Paulef8f1f92015-04-29 16:05:23 -0400358 if (!found) {
359 args.handle = hd->front.gem_handles[i];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400360 drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args);
Sean Paulef8f1f92015-04-29 16:05:23 -0400361 }
362 if (pthread_mutex_unlock(&hd->set_worker.lock))
363 ALOGE("Failed to unlock set lock in wait_and_set() %d", ret);
364 }
365 }
Lauri Peltonen77d6d7a2015-02-23 20:44:16 +0200366
Sean Paulef8f1f92015-04-29 16:05:23 -0400367 hd->front = *buf;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800368
Sean Paulef8f1f92015-04-29 16:05:23 -0400369 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500370}
371
Sean Paulef8f1f92015-04-29 16:05:23 -0400372static void *hwc_set_worker(void *arg) {
373 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500374
Sean Paulef8f1f92015-04-29 16:05:23 -0400375 struct hwc_drm_display *hd = (struct hwc_drm_display *)arg;
376 int ret = pthread_mutex_lock(&hd->flip_lock);
377 if (ret) {
378 ALOGE("Failed to lock flip lock ret=%d", ret);
379 return NULL;
380 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500381
Sean Paulef8f1f92015-04-29 16:05:23 -0400382 do {
383 ret = pthread_mutex_lock(&hd->set_worker.lock);
384 if (ret) {
385 ALOGE("Failed to lock set lock %d", ret);
386 return NULL;
387 }
Sean Paul814bddb2015-03-03 17:46:19 -0500388
Sean Paulef8f1f92015-04-29 16:05:23 -0400389 if (hd->set_worker.exit)
390 break;
Sean Paul3bc48e82015-01-23 01:41:13 -0500391
Sean Paulef8f1f92015-04-29 16:05:23 -0400392 if (hd->buf_queue.empty()) {
393 ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock);
394 if (ret) {
395 ALOGE("Failed to wait on condition %d", ret);
396 break;
397 }
398 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500399
Sean Paulef8f1f92015-04-29 16:05:23 -0400400 struct hwc_drm_bo buf;
401 buf = hd->buf_queue.front();
402 hd->buf_queue.pop_front();
Sean Paul3bc48e82015-01-23 01:41:13 -0500403
Sean Paulef8f1f92015-04-29 16:05:23 -0400404 ret = pthread_mutex_unlock(&hd->set_worker.lock);
405 if (ret) {
406 ALOGE("Failed to unlock set lock %d", ret);
407 return NULL;
408 }
Sean Paul3bc48e82015-01-23 01:41:13 -0500409
Sean Paulef8f1f92015-04-29 16:05:23 -0400410 ret = hwc_wait_and_set(hd, &buf);
411 if (ret)
412 ALOGE("Failed to wait and set %d", ret);
Sean Paul3bc48e82015-01-23 01:41:13 -0500413
Sean Paulef8f1f92015-04-29 16:05:23 -0400414 ret = sw_sync_timeline_inc(hd->timeline_fd, 1);
415 if (ret)
416 ALOGE("Failed to increment sync timeline %d", ret);
417 } while (true);
Sean Paul3bc48e82015-01-23 01:41:13 -0500418
Sean Paulef8f1f92015-04-29 16:05:23 -0400419 ret = pthread_mutex_unlock(&hd->set_worker.lock);
420 if (ret)
421 ALOGE("Failed to unlock set lock while exiting %d", ret);
Sean Paulf1dc1912015-01-24 01:34:31 -0500422
Sean Paulef8f1f92015-04-29 16:05:23 -0400423 ret = pthread_mutex_unlock(&hd->flip_lock);
424 if (ret)
425 ALOGE("Failed to unlock flip lock ret=%d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500426
Sean Paulef8f1f92015-04-29 16:05:23 -0400427 return NULL;
428}
Sean Paul9aa5ad32015-01-22 15:47:54 -0500429
Sean Paulef8f1f92015-04-29 16:05:23 -0400430static void hwc_close_fences(hwc_display_contents_1_t *display_contents) {
431 for (int i = 0; i < (int)display_contents->numHwLayers; ++i) {
432 hwc_layer_1_t *layer = &display_contents->hwLayers[i];
433 if (layer->acquireFenceFd >= 0) {
434 close(layer->acquireFenceFd);
435 layer->acquireFenceFd = -1;
436 }
437 }
438 if (display_contents->outbufAcquireFenceFd >= 0) {
439 close(display_contents->outbufAcquireFenceFd);
440 display_contents->outbufAcquireFenceFd = -1;
441 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500442}
443
Sean Paule0c4c3d2015-01-20 16:56:04 -0500444static int hwc_set_display(hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -0400445 hwc_display_contents_1_t *display_contents) {
446 struct hwc_drm_display *hd = NULL;
447 int ret = hwc_get_drm_display(ctx, display, &hd);
448 if (ret) {
449 hwc_close_fences(display_contents);
450 return ret;
451 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500452
Sean Paul6a55e9f2015-04-30 15:31:06 -0400453 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display);
454 if (!crtc) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400455 ALOGE("There is no active crtc for display %d", display);
456 hwc_close_fences(display_contents);
457 return -ENOENT;
458 }
Sean Paul9b1bb842015-01-23 01:11:58 -0500459
Sean Paulef8f1f92015-04-29 16:05:23 -0400460 /*
461 * TODO: We can only support one hw layer atm, so choose either the
462 * first one or the framebuffer target.
463 */
464 hwc_layer_1_t *layer = NULL;
465 if (!display_contents->numHwLayers) {
466 return 0;
467 } else if (display_contents->numHwLayers == 1) {
468 layer = &display_contents->hwLayers[0];
469 } else {
470 int i;
471 for (i = 0; i < (int)display_contents->numHwLayers; ++i) {
472 layer = &display_contents->hwLayers[i];
473 if (layer->compositionType == HWC_FRAMEBUFFER_TARGET)
474 break;
475 }
476 if (i == (int)display_contents->numHwLayers) {
477 ALOGE("Could not find a suitable layer for display %d", display);
478 }
479 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500480
Sean Paulef8f1f92015-04-29 16:05:23 -0400481 ret = pthread_mutex_lock(&hd->set_worker.lock);
482 if (ret) {
483 ALOGE("Failed to lock set lock in set() %d", ret);
484 hwc_close_fences(display_contents);
485 return ret;
486 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500487
Sean Paulef8f1f92015-04-29 16:05:23 -0400488 struct hwc_drm_bo buf;
489 memset(&buf, 0, sizeof(buf));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400490 ret =
491 hwc_import_bo_create(ctx->drm.fd(), ctx->import_ctx, layer->handle, &buf);
Sean Paulef8f1f92015-04-29 16:05:23 -0400492 if (ret) {
493 ALOGE("Failed to import handle to drm bo %d", ret);
494 hwc_close_fences(display_contents);
495 return ret;
496 }
497 buf.acquire_fence_fd = layer->acquireFenceFd;
498 layer->acquireFenceFd = -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500499
Sean Paulef8f1f92015-04-29 16:05:23 -0400500 /*
501 * TODO: Retire and release can use the same sync point here b/c hwc is
502 * restricted to one layer. Once that is no longer true, this will need
503 * to change
504 */
505 ++hd->timeline_next;
506 display_contents->retireFenceFd = sw_sync_fence_create(
507 hd->timeline_fd, "drm_hwc_retire", hd->timeline_next);
508 layer->releaseFenceFd = sw_sync_fence_create(
509 hd->timeline_fd, "drm_hwc_release", hd->timeline_next);
510 hd->buf_queue.push_back(buf);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800511
Sean Paulef8f1f92015-04-29 16:05:23 -0400512 ret = pthread_cond_signal(&hd->set_worker.cond);
513 if (ret)
514 ALOGE("Failed to signal set worker %d", ret);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800515
Sean Paulef8f1f92015-04-29 16:05:23 -0400516 if (pthread_mutex_unlock(&hd->set_worker.lock))
517 ALOGE("Failed to unlock set lock in set()");
Sean Paul3bc48e82015-01-23 01:41:13 -0500518
Sean Paulef8f1f92015-04-29 16:05:23 -0400519 hwc_close_fences(display_contents);
520 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500521}
522
523static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400524 hwc_display_contents_1_t **display_contents) {
525 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500526
Sean Paulef8f1f92015-04-29 16:05:23 -0400527 int ret = 0;
528 for (int i = 0; i < (int)num_displays && i < MAX_NUM_DISPLAYS; ++i) {
529 if (display_contents[i])
530 ret = hwc_set_display(ctx, i, display_contents[i]);
531 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500532
Sean Paulef8f1f92015-04-29 16:05:23 -0400533 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500534}
535
Sean Paulef8f1f92015-04-29 16:05:23 -0400536static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
537 int event, int enabled) {
538 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
539 struct hwc_drm_display *hd = NULL;
540 int ret = hwc_get_drm_display(ctx, display, &hd);
541 if (ret)
542 return ret;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500543
Sean Paulef8f1f92015-04-29 16:05:23 -0400544 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
545 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500546
Sean Paul6a55e9f2015-04-30 15:31:06 -0400547 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display);
548 if (!crtc) {
549 ALOGD("Can't service events for display %d, no crtc", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400550 return -EINVAL;
551 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500552
Sean Paulef8f1f92015-04-29 16:05:23 -0400553 hd->enable_vsync_events = !!enabled;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500554
Sean Paulef8f1f92015-04-29 16:05:23 -0400555 if (!hd->enable_vsync_events)
556 return 0;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500557
Sean Paulef8f1f92015-04-29 16:05:23 -0400558 /*
559 * Note that it's possible that the event worker is already waiting for
560 * a vsync, and this will be a duplicate request. In that event, we'll
561 * end up firing the event handler twice, and it will discard the second
562 * event. Not ideal, but not worth introducing a bunch of additional
563 * logic/locks/state for.
564 */
565 ret = hwc_queue_vblank_event(hd);
566 if (ret) {
567 ALOGE("Failed to queue vblank event ret=%d", ret);
568 return ret;
569 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500570
Sean Paulef8f1f92015-04-29 16:05:23 -0400571 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500572}
573
Sean Paulef8f1f92015-04-29 16:05:23 -0400574static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
575 int mode) {
576 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500577
Sean Paul6a55e9f2015-04-30 15:31:06 -0400578 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400579 switch (mode) {
580 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400581 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400582 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500583
Sean Paulef8f1f92015-04-29 16:05:23 -0400584 /* We can't support dozing right now, so go full on */
585 case HWC_POWER_MODE_DOZE:
586 case HWC_POWER_MODE_DOZE_SUSPEND:
587 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400588 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400589 break;
590 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400591 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500592}
593
Sean Paulef8f1f92015-04-29 16:05:23 -0400594static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
595 int *value) {
596 switch (what) {
597 case HWC_BACKGROUND_LAYER_SUPPORTED:
598 *value = 0; /* TODO: We should do this */
599 break;
600 case HWC_VSYNC_PERIOD:
601 ALOGW("Query for deprecated vsync value, returning 60Hz");
602 *value = 1000 * 1000 * 1000 / 60;
603 break;
604 case HWC_DISPLAY_TYPES_SUPPORTED:
605 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
606 break;
607 }
608 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500609}
610
Sean Paulef8f1f92015-04-29 16:05:23 -0400611static void hwc_register_procs(struct hwc_composer_device_1 *dev,
612 hwc_procs_t const *procs) {
613 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500614
Sean Paulef8f1f92015-04-29 16:05:23 -0400615 ctx->procs = procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500616}
617
Sean Paulef8f1f92015-04-29 16:05:23 -0400618static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
619 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400620 size_t *num_configs) {
621 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400622 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500623
Sean Paulef8f1f92015-04-29 16:05:23 -0400624 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
625 struct hwc_drm_display *hd = NULL;
626 int ret = hwc_get_drm_display(ctx, display, &hd);
627 if (ret)
628 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500629
Sean Paul6a55e9f2015-04-30 15:31:06 -0400630 hd->config_ids.clear();
631
632 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
633 if (!connector) {
634 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400635 return -ENODEV;
636 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500637
Sean Paul6a55e9f2015-04-30 15:31:06 -0400638 ret = connector->UpdateModes();
639 if (ret) {
640 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400641 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400642 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500643
Sean Paul6a55e9f2015-04-30 15:31:06 -0400644 for (DrmConnector::ModeIter iter = connector->begin_modes();
645 iter != connector->end_modes(); ++iter) {
646 size_t idx = hd->config_ids.size();
647 if (idx == *num_configs)
648 break;
649 hd->config_ids.push_back(iter->id());
650 configs[idx] = iter->id();
651 }
652 *num_configs = hd->config_ids.size();
653 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500654}
655
Sean Paulef8f1f92015-04-29 16:05:23 -0400656static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
657 int display, uint32_t config,
658 const uint32_t *attributes,
659 int32_t *values) {
660 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400661 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400662 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400663 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400664 return -ENODEV;
665 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400666 DrmMode mode;
667 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
668 ++iter) {
669 if (iter->id() == config) {
670 mode = *iter;
671 break;
672 }
673 }
674 if (mode.id() == 0) {
675 ALOGE("Failed to find active mode for display %d", display);
676 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400677 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500678
Sean Paul6a55e9f2015-04-30 15:31:06 -0400679 uint32_t mm_width = c->mm_width();
680 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400681 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
682 switch (attributes[i]) {
683 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400684 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400685 break;
686 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400687 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400688 break;
689 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400690 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400691 break;
692 case HWC_DISPLAY_DPI_X:
693 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400694 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400695 break;
696 case HWC_DISPLAY_DPI_Y:
697 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400698 values[i] =
699 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400700 break;
701 }
702 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400703 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500704}
705
Sean Paulef8f1f92015-04-29 16:05:23 -0400706static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
707 int display) {
708 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
709 struct hwc_drm_display *hd = NULL;
710 int ret = hwc_get_drm_display(ctx, display, &hd);
711 if (ret)
712 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500713
Sean Paul6a55e9f2015-04-30 15:31:06 -0400714 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
715 if (!c) {
716 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400717 return -ENODEV;
718 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500719
Sean Paul6a55e9f2015-04-30 15:31:06 -0400720 DrmMode mode = c->active_mode();
721 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
722 if (hd->config_ids[i] == mode.id())
723 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400724 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400725 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500726}
727
Sean Paulef8f1f92015-04-29 16:05:23 -0400728static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
729 int index) {
730 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
731 struct hwc_drm_display *hd = NULL;
732 int ret = hwc_get_drm_display(ctx, display, &hd);
733 if (ret)
734 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500735
Sean Paul6a55e9f2015-04-30 15:31:06 -0400736 if (index >= (int)hd->config_ids.size()) {
737 ALOGE("Invalid config index %d passed in", index);
738 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400739 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500740
Sean Paul6a55e9f2015-04-30 15:31:06 -0400741 ret =
742 ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
743 if (ret) {
744 ALOGE("Failed to set config for display %d", display);
745 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400746 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500747
Sean Paul6a55e9f2015-04-30 15:31:06 -0400748 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500749}
750
Sean Paulef8f1f92015-04-29 16:05:23 -0400751static int hwc_destroy_worker(struct hwc_worker *worker) {
752 int ret = pthread_mutex_lock(&worker->lock);
753 if (ret) {
754 ALOGE("Failed to lock in destroy() %d", ret);
755 return ret;
756 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500757
Sean Paulef8f1f92015-04-29 16:05:23 -0400758 worker->exit = true;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500759
Sean Paulef8f1f92015-04-29 16:05:23 -0400760 ret |= pthread_cond_signal(&worker->cond);
761 if (ret)
762 ALOGE("Failed to signal cond in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500763
Sean Paulef8f1f92015-04-29 16:05:23 -0400764 ret |= pthread_mutex_unlock(&worker->lock);
765 if (ret)
766 ALOGE("Failed to unlock in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500767
Sean Paulef8f1f92015-04-29 16:05:23 -0400768 ret |= pthread_join(worker->thread, NULL);
769 if (ret && ret != ESRCH)
770 ALOGE("Failed to join thread in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500771
Sean Paulef8f1f92015-04-29 16:05:23 -0400772 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500773}
774
Sean Paulef8f1f92015-04-29 16:05:23 -0400775static void hwc_destroy_display(struct hwc_drm_display *hd) {
776 if (hwc_destroy_worker(&hd->set_worker))
777 ALOGE("Destroy set worker failed");
Sean Paul9aa5ad32015-01-22 15:47:54 -0500778}
779
Sean Paulef8f1f92015-04-29 16:05:23 -0400780static int hwc_device_close(struct hw_device_t *dev) {
781 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500782
Sean Paulef8f1f92015-04-29 16:05:23 -0400783 for (int i = 0; i < MAX_NUM_DISPLAYS; ++i)
784 hwc_destroy_display(&ctx->displays[i]);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500785
Sean Paulef8f1f92015-04-29 16:05:23 -0400786 if (hwc_destroy_worker(&ctx->event_worker))
787 ALOGE("Destroy event worker failed");
Sean Paul814bddb2015-03-03 17:46:19 -0500788
Sean Paulef8f1f92015-04-29 16:05:23 -0400789 int ret = hwc_import_destroy(ctx->import_ctx);
790 if (ret)
791 ALOGE("Could not destroy import %d", ret);
Sean Paulcd36a9e2015-01-22 18:01:18 -0500792
Sean Paulef8f1f92015-04-29 16:05:23 -0400793 delete ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500794
Sean Paulef8f1f92015-04-29 16:05:23 -0400795 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500796}
797
Sean Paul814bddb2015-03-03 17:46:19 -0500798static int hwc_initialize_worker(struct hwc_worker *worker,
Sean Paulef8f1f92015-04-29 16:05:23 -0400799 void *(*routine)(void *), void *arg) {
800 int ret = pthread_cond_init(&worker->cond, NULL);
801 if (ret) {
802 ALOGE("Failed to create worker condition %d", ret);
803 return ret;
804 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500805
Sean Paulef8f1f92015-04-29 16:05:23 -0400806 ret = pthread_mutex_init(&worker->lock, NULL);
807 if (ret) {
808 ALOGE("Failed to initialize worker lock %d", ret);
809 pthread_cond_destroy(&worker->cond);
810 return ret;
811 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500812
Sean Paulef8f1f92015-04-29 16:05:23 -0400813 worker->exit = false;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500814
Sean Paulef8f1f92015-04-29 16:05:23 -0400815 ret = pthread_create(&worker->thread, NULL, routine, arg);
816 if (ret) {
817 ALOGE("Could not create worker thread %d", ret);
818 pthread_mutex_destroy(&worker->lock);
819 pthread_cond_destroy(&worker->cond);
820 return ret;
821 }
822 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500823}
824
Sean Paul24a26e32015-02-04 10:34:47 -0800825/*
826 * TODO: This function sets the active config to the first one in the list. This
827 * should be fixed such that it selects the preferred mode for the display, or
828 * some other, saner, method of choosing the config.
829 */
Sean Paulef8f1f92015-04-29 16:05:23 -0400830static int hwc_set_initial_config(struct hwc_drm_display *hd) {
831 uint32_t config;
832 size_t num_configs = 1;
833 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
834 &num_configs);
835 if (ret || !num_configs)
836 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800837
Sean Paulef8f1f92015-04-29 16:05:23 -0400838 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
839 if (ret) {
840 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
841 return ret;
842 }
Sean Paul24a26e32015-02-04 10:34:47 -0800843
Sean Paulef8f1f92015-04-29 16:05:23 -0400844 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800845}
846
Sean Paul6a55e9f2015-04-30 15:31:06 -0400847static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400848 struct hwc_drm_display *hd = NULL;
849 int ret = hwc_get_drm_display(ctx, display, &hd);
850 if (ret)
851 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500852
Sean Paulef8f1f92015-04-29 16:05:23 -0400853 hd->ctx = ctx;
854 hd->display = display;
Sean Paulef8f1f92015-04-29 16:05:23 -0400855 hd->enable_vsync_events = false;
856 hd->vsync_sequence = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500857
Sean Paulef8f1f92015-04-29 16:05:23 -0400858 ret = pthread_mutex_init(&hd->flip_lock, NULL);
859 if (ret) {
860 ALOGE("Failed to initialize flip lock %d", ret);
861 return ret;
862 }
Sean Paul814bddb2015-03-03 17:46:19 -0500863
Sean Paulef8f1f92015-04-29 16:05:23 -0400864 ret = pthread_cond_init(&hd->flip_cond, NULL);
865 if (ret) {
866 ALOGE("Failed to intiialize flip condition %d", ret);
867 pthread_mutex_destroy(&hd->flip_lock);
868 return ret;
869 }
Sean Paul814bddb2015-03-03 17:46:19 -0500870
Sean Paulef8f1f92015-04-29 16:05:23 -0400871 ret = sw_sync_timeline_create();
872 if (ret < 0) {
873 ALOGE("Failed to create sw sync timeline %d", ret);
874 pthread_cond_destroy(&hd->flip_cond);
875 pthread_mutex_destroy(&hd->flip_lock);
876 return ret;
877 }
878 hd->timeline_fd = ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500879
Sean Paulef8f1f92015-04-29 16:05:23 -0400880 /*
881 * Initialize timeline_next to 1, because point 0 will be the very first
882 * set operation. Since we increment every time set() is called,
883 * initializing to 0 would cause an off-by-one error where
884 * surfaceflinger would composite on the front buffer.
885 */
886 hd->timeline_next = 1;
Sean Paule147a2a2015-02-22 17:55:43 -0500887
Sean Paulef8f1f92015-04-29 16:05:23 -0400888 ret = hwc_set_initial_config(hd);
889 if (ret) {
890 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
891 close(hd->timeline_fd);
892 pthread_cond_destroy(&hd->flip_cond);
893 pthread_mutex_destroy(&hd->flip_lock);
894 return ret;
895 }
Sean Paulf1dc1912015-01-24 01:34:31 -0500896
Sean Paulef8f1f92015-04-29 16:05:23 -0400897 ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd);
898 if (ret) {
899 ALOGE("Failed to create set worker %d\n", ret);
900 close(hd->timeline_fd);
901 pthread_cond_destroy(&hd->flip_cond);
902 pthread_mutex_destroy(&hd->flip_lock);
903 return ret;
904 }
Sean Paul24a26e32015-02-04 10:34:47 -0800905
Sean Paulef8f1f92015-04-29 16:05:23 -0400906 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500907}
908
Sean Paulef8f1f92015-04-29 16:05:23 -0400909static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) {
910 for (int i = 0; i < num_conn; ++i) {
911 if (conn_list[i])
912 drmModeFreeConnector(conn_list[i]);
913 }
914 free(conn_list);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500915}
916
Sean Paulef8f1f92015-04-29 16:05:23 -0400917static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400918 int ret;
919 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
920 c != ctx->drm.end_connectors(); ++c) {
921 ret = hwc_initialize_display(ctx, (*c)->display());
922 if (ret) {
923 ALOGE("Failed to initialize display %d", (*c)->display());
924 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400925 }
926 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400927
928 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500929}
930
Sean Paulef8f1f92015-04-29 16:05:23 -0400931static int hwc_device_open(const struct hw_module_t *module, const char *name,
932 struct hw_device_t **dev) {
933 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
934 ALOGE("Invalid module name- %s", name);
935 return -EINVAL;
936 }
937
938 struct hwc_context_t *ctx = new hwc_context_t();
939 if (!ctx) {
940 ALOGE("Failed to allocate hwc context");
941 return -ENOMEM;
942 }
943
Sean Paul6a55e9f2015-04-30 15:31:06 -0400944 int ret = ctx->drm.Init();
945 if (ret) {
946 ALOGE("Can't initialize Drm object %d", ret);
947 delete ctx;
948 return ret;
949 }
950
951 ret = hwc_import_init(&ctx->import_ctx);
Sean Paulef8f1f92015-04-29 16:05:23 -0400952 if (ret) {
953 ALOGE("Failed to initialize import context");
954 delete ctx;
955 return ret;
956 }
957
Sean Paulef8f1f92015-04-29 16:05:23 -0400958 ret = hwc_enumerate_displays(ctx);
959 if (ret) {
960 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400961 delete ctx;
962 return ret;
963 }
964
965 ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx);
966 if (ret) {
967 ALOGE("Failed to create event worker %d\n", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400968 delete ctx;
969 return ret;
970 }
971
972 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
973 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
974 ctx->device.common.module = const_cast<hw_module_t *>(module);
975 ctx->device.common.close = hwc_device_close;
976
977 ctx->device.prepare = hwc_prepare;
978 ctx->device.set = hwc_set;
979 ctx->device.eventControl = hwc_event_control;
980 ctx->device.setPowerMode = hwc_set_power_mode;
981 ctx->device.query = hwc_query;
982 ctx->device.registerProcs = hwc_register_procs;
983 ctx->device.getDisplayConfigs = hwc_get_display_configs;
984 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
985 ctx->device.getActiveConfig = hwc_get_active_config;
986 ctx->device.setActiveConfig = hwc_set_active_config;
987 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
988
989 *dev = &ctx->device.common;
990
991 return 0;
992}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400993}
Sean Paulef8f1f92015-04-29 16:05:23 -0400994
Sean Paul6a55e9f2015-04-30 15:31:06 -0400995static struct hw_module_methods_t hwc_module_methods = {
996 open : android::hwc_device_open
997};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500998
999hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -04001000 common : {
1001 tag : HARDWARE_MODULE_TAG,
1002 version_major : 1,
1003 version_minor : 0,
1004 id : HWC_HARDWARE_MODULE_ID,
1005 name : "DRM hwcomposer module",
1006 author : "The Android Open Source Project",
1007 methods : &hwc_module_methods,
1008 dso : NULL,
1009 reserved : {0},
1010 }
Sean Paule0c4c3d2015-01-20 16:56:04 -05001011};