blob: c9452b63fc07b249cdd7b11de7ca83a29278c6f5 [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040021
Sean Paule0c4c3d2015-01-20 16:56:04 -050022#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040023#include <fcntl.h>
Sean Paul5ad302c2015-05-11 10:43:31 -070024#include <list>
Sean Paule42febf2015-05-07 11:35:29 -070025#include <map>
Sean Paulef8f1f92015-04-29 16:05:23 -040026#include <pthread.h>
Dan Albertc5255b32015-05-07 23:42:54 -070027#include <stdlib.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050028#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050029#include <sys/resource.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050030#include <xf86drm.h>
31#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050032
Sean Paulef8f1f92015-04-29 16:05:23 -040033#include <cutils/log.h>
34#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050035#include <hardware/hardware.h>
36#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050037#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040038#include <sync/sync.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050039
40#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
41
Sean Paule0c4c3d2015-01-20 16:56:04 -050042#define UM_PER_INCH 25400
43
Sean Paul6a55e9f2015-04-30 15:31:06 -040044namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050045
Sean Paul9aa5ad32015-01-22 15:47:54 -050046struct hwc_worker {
Sean Paulef8f1f92015-04-29 16:05:23 -040047 pthread_t thread;
48 pthread_mutex_t lock;
49 pthread_cond_t cond;
50 bool exit;
Sean Paul9aa5ad32015-01-22 15:47:54 -050051};
52
Sean Paule42febf2015-05-07 11:35:29 -070053typedef struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -040054 struct hwc_context_t *ctx;
55 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -050056
Sean Paul6a55e9f2015-04-30 15:31:06 -040057 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -050058
Sean Paulef8f1f92015-04-29 16:05:23 -040059 struct hwc_worker set_worker;
Sean Paul9aa5ad32015-01-22 15:47:54 -050060
Sean Paulef8f1f92015-04-29 16:05:23 -040061 std::list<struct hwc_drm_bo> buf_queue;
62 struct hwc_drm_bo front;
63 pthread_mutex_t flip_lock;
64 pthread_cond_t flip_cond;
Sean Paulf1dc1912015-01-24 01:34:31 -050065
Sean Paulef8f1f92015-04-29 16:05:23 -040066 int timeline_fd;
67 unsigned timeline_next;
Sean Pauleb9e75c2015-01-25 23:31:30 -050068
Sean Paulef8f1f92015-04-29 16:05:23 -040069 bool enable_vsync_events;
70 unsigned int vsync_sequence;
Sean Paule42febf2015-05-07 11:35:29 -070071} hwc_drm_display_t;
Sean Paule0c4c3d2015-01-20 16:56:04 -050072
73struct hwc_context_t {
Sean Paule42febf2015-05-07 11:35:29 -070074 // map of display:hwc_drm_display_t
75 typedef std::map<int, hwc_drm_display_t> DisplayMap;
76 typedef DisplayMap::iterator DisplayMapIter;
Sean Paule0c4c3d2015-01-20 16:56:04 -050077
Sean Paule42febf2015-05-07 11:35:29 -070078 hwc_composer_device_1_t device;
Sean Paulef8f1f92015-04-29 16:05:23 -040079 hwc_procs_t const *procs;
80 struct hwc_import_context *import_ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -050081
Sean Paulef8f1f92015-04-29 16:05:23 -040082 struct hwc_worker event_worker;
Sean Paul6a55e9f2015-04-30 15:31:06 -040083
Sean Paule42febf2015-05-07 11:35:29 -070084 DisplayMap displays;
Sean Paul6a55e9f2015-04-30 15:31:06 -040085 DrmResources drm;
Sean Paule0c4c3d2015-01-20 16:56:04 -050086};
87
Sean Paulef8f1f92015-04-29 16:05:23 -040088static int hwc_prepare_layer(hwc_layer_1_t *layer) {
89 /* TODO: We can't handle background right now, defer to sufaceFlinger */
90 if (layer->compositionType == HWC_BACKGROUND) {
91 layer->compositionType = HWC_FRAMEBUFFER;
92 ALOGV("Can't handle background layers yet");
Sean Paule0c4c3d2015-01-20 16:56:04 -050093
Sean Paulef8f1f92015-04-29 16:05:23 -040094 /* TODO: Support sideband compositions */
95 } else if (layer->compositionType == HWC_SIDEBAND) {
96 layer->compositionType = HWC_FRAMEBUFFER;
97 ALOGV("Can't handle sideband content yet");
98 }
Sean Paule0c4c3d2015-01-20 16:56:04 -050099
Sean Paulef8f1f92015-04-29 16:05:23 -0400100 layer->hints = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500101
Sean Paulef8f1f92015-04-29 16:05:23 -0400102 /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */
103 if (layer->flags & HWC_IS_CURSOR_LAYER) {
104 ALOGV("Can't handle async cursors yet");
105 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500106
Sean Paulef8f1f92015-04-29 16:05:23 -0400107 /* TODO: Handle transformations */
108 if (layer->transform) {
109 ALOGV("Can't handle transformations yet");
110 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500111
Sean Paulef8f1f92015-04-29 16:05:23 -0400112 /* TODO: Handle blending & plane alpha*/
113 if (layer->blending == HWC_BLENDING_PREMULT ||
114 layer->blending == HWC_BLENDING_COVERAGE) {
115 ALOGV("Can't handle blending yet");
116 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500117
Sean Paulef8f1f92015-04-29 16:05:23 -0400118 /* TODO: Handle cropping & scaling */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500119
Sean Paulef8f1f92015-04-29 16:05:23 -0400120 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500121}
122
Sean Paulef8f1f92015-04-29 16:05:23 -0400123static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays,
124 hwc_display_contents_1_t **display_contents) {
125 /* TODO: Check flags for HWC_GEOMETRY_CHANGED */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500126
Sean Paule42febf2015-05-07 11:35:29 -0700127 for (int i = 0; i < (int)num_displays; ++i) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400128 if (!display_contents[i])
129 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500130
Sean Paulef8f1f92015-04-29 16:05:23 -0400131 for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) {
132 int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]);
133 if (ret) {
134 ALOGE("Failed to prepare layer %d:%d", j, i);
135 return ret;
136 }
137 }
138 }
Sean Pauldffca952015-02-04 10:19:55 -0800139
Sean Paulef8f1f92015-04-29 16:05:23 -0400140 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500141}
142
Sean Paulef8f1f92015-04-29 16:05:23 -0400143static int hwc_queue_vblank_event(struct hwc_drm_display *hd) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400144 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
145 if (!crtc) {
146 ALOGE("Failed to get crtc for display");
147 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400148 }
Sean Paul814bddb2015-03-03 17:46:19 -0500149
Sean Paulef8f1f92015-04-29 16:05:23 -0400150 drmVBlank vblank;
151 memset(&vblank, 0, sizeof(vblank));
Sean Paul814bddb2015-03-03 17:46:19 -0500152
Sean Paul6a55e9f2015-04-30 15:31:06 -0400153 uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT);
Sean Paulef8f1f92015-04-29 16:05:23 -0400154 vblank.request.type = (drmVBlankSeqType)(
155 DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT |
156 (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK));
157 vblank.request.signal = (unsigned long)hd;
158 vblank.request.sequence = hd->vsync_sequence + 1;
Sean Paul814bddb2015-03-03 17:46:19 -0500159
Sean Paul6a55e9f2015-04-30 15:31:06 -0400160 int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank);
Sean Paulef8f1f92015-04-29 16:05:23 -0400161 if (ret) {
162 ALOGE("Failed to wait for vblank %d", ret);
163 return ret;
164 }
Sean Paul814bddb2015-03-03 17:46:19 -0500165
Sean Paulef8f1f92015-04-29 16:05:23 -0400166 return 0;
Sean Paul814bddb2015-03-03 17:46:19 -0500167}
168
169static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence,
Sean Paulef8f1f92015-04-29 16:05:23 -0400170 unsigned int tv_sec, unsigned int tv_usec,
171 void *user_data) {
172 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500173
Sean Paulef8f1f92015-04-29 16:05:23 -0400174 if (!hd->enable_vsync_events || !hd->ctx->procs->vsync)
175 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500176
Sean Paulef8f1f92015-04-29 16:05:23 -0400177 /*
178 * Discard duplicate vsync (can happen when enabling vsync events while
179 * already processing vsyncs).
180 */
181 if (sequence <= hd->vsync_sequence)
182 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500183
Sean Paulef8f1f92015-04-29 16:05:23 -0400184 hd->vsync_sequence = sequence;
185 int ret = hwc_queue_vblank_event(hd);
186 if (ret)
187 ALOGE("Failed to queue vblank event ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500188
Sean Paulef8f1f92015-04-29 16:05:23 -0400189 int64_t timestamp =
190 (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000;
191 hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp);
Sean Paul814bddb2015-03-03 17:46:19 -0500192}
193
194static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */,
Sean Paulef8f1f92015-04-29 16:05:23 -0400195 unsigned int /* tv_sec */,
196 unsigned int /* tv_usec */,
197 void *user_data) {
198 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500199
Sean Paulef8f1f92015-04-29 16:05:23 -0400200 int ret = pthread_mutex_lock(&hd->flip_lock);
201 if (ret) {
202 ALOGE("Failed to lock flip lock ret=%d", ret);
203 return;
204 }
Sean Paul814bddb2015-03-03 17:46:19 -0500205
Sean Paulef8f1f92015-04-29 16:05:23 -0400206 ret = pthread_cond_signal(&hd->flip_cond);
207 if (ret)
208 ALOGE("Failed to signal flip condition ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500209
Sean Paulef8f1f92015-04-29 16:05:23 -0400210 ret = pthread_mutex_unlock(&hd->flip_lock);
211 if (ret) {
212 ALOGE("Failed to unlock flip lock ret=%d", ret);
213 return;
214 }
Sean Paul814bddb2015-03-03 17:46:19 -0500215}
216
Sean Paulef8f1f92015-04-29 16:05:23 -0400217static void *hwc_event_worker(void *arg) {
218 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul814bddb2015-03-03 17:46:19 -0500219
Sean Paulef8f1f92015-04-29 16:05:23 -0400220 struct hwc_context_t *ctx = (struct hwc_context_t *)arg;
221 do {
222 fd_set fds;
223 FD_ZERO(&fds);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400224 FD_SET(ctx->drm.fd(), &fds);
Sean Paul814bddb2015-03-03 17:46:19 -0500225
Sean Paulef8f1f92015-04-29 16:05:23 -0400226 drmEventContext event_context;
227 event_context.version = DRM_EVENT_CONTEXT_VERSION;
228 event_context.page_flip_handler = hwc_flip_event_handler;
229 event_context.vblank_handler = hwc_vblank_event_handler;
Sean Paul814bddb2015-03-03 17:46:19 -0500230
Sean Paulef8f1f92015-04-29 16:05:23 -0400231 int ret;
232 do {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400233 ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400234 } while (ret == -1 && errno == EINTR);
Sean Paul814bddb2015-03-03 17:46:19 -0500235
Sean Paulef8f1f92015-04-29 16:05:23 -0400236 if (ret != 1) {
237 ALOGE("Failed waiting for drm event\n");
238 continue;
239 }
Sean Paul814bddb2015-03-03 17:46:19 -0500240
Sean Paul6a55e9f2015-04-30 15:31:06 -0400241 drmHandleEvent(ctx->drm.fd(), &event_context);
Sean Paulef8f1f92015-04-29 16:05:23 -0400242 } while (true);
Sean Paul814bddb2015-03-03 17:46:19 -0500243
Sean Paulef8f1f92015-04-29 16:05:23 -0400244 return NULL;
Sean Paul814bddb2015-03-03 17:46:19 -0500245}
246
Sean Paulef8f1f92015-04-29 16:05:23 -0400247static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) {
248 return a->clock == b->clock && a->hdisplay == b->hdisplay &&
249 a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end &&
250 a->htotal == b->htotal && a->hskew == b->hskew &&
251 a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start &&
252 a->vsync_end == b->vsync_end && a->vtotal == b->vtotal &&
253 a->vscan == b->vscan && a->vrefresh == b->vrefresh &&
254 a->flags == b->flags && a->type == b->type &&
255 !strcmp(a->name, b->name);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500256}
257
Sean Paul6a55e9f2015-04-30 15:31:06 -0400258static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) {
259 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400260 if (!crtc) {
261 ALOGE("Failed to get crtc for display %d", hd->display);
262 return -ENODEV;
263 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800264
Sean Paul6a55e9f2015-04-30 15:31:06 -0400265 DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display);
266 if (!connector) {
267 ALOGE("Failed to get connector for display %d", hd->display);
268 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400269 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400270
271 int ret;
272 if (crtc->requires_modeset()) {
273 drmModeModeInfo drm_mode;
274 connector->active_mode().ToModeModeInfo(&drm_mode);
275 uint32_t connector_id = connector->id();
276 ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0,
277 &connector_id, 1, &drm_mode);
Sean Paulef8f1f92015-04-29 16:05:23 -0400278 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400279 ALOGE("Modeset failed for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400280 return ret;
281 }
Sean Paulc0027942015-05-13 06:27:37 -0700282 crtc->set_requires_modeset(false);
Sean Paulef8f1f92015-04-29 16:05:23 -0400283 return 0;
284 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500285
Sean Paul6a55e9f2015-04-30 15:31:06 -0400286 ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id,
Sean Paulef8f1f92015-04-29 16:05:23 -0400287 DRM_MODE_PAGE_FLIP_EVENT, hd);
288 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400289 ALOGE("Failed to flip buffer for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400290 return ret;
291 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500292
Sean Paulef8f1f92015-04-29 16:05:23 -0400293 ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock);
294 if (ret) {
295 ALOGE("Failed to wait on condition %d", ret);
296 return ret;
297 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500298
Sean Paulef8f1f92015-04-29 16:05:23 -0400299 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500300}
301
Sean Paul3bc48e82015-01-23 01:41:13 -0500302static int hwc_wait_and_set(struct hwc_drm_display *hd,
Sean Paulef8f1f92015-04-29 16:05:23 -0400303 struct hwc_drm_bo *buf) {
304 int ret;
305 if (buf->acquire_fence_fd >= 0) {
306 ret = sync_wait(buf->acquire_fence_fd, -1);
307 close(buf->acquire_fence_fd);
308 buf->acquire_fence_fd = -1;
309 if (ret) {
310 ALOGE("Failed to wait for acquire %d", ret);
311 return ret;
312 }
313 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500314
Sean Paulef8f1f92015-04-29 16:05:23 -0400315 ret = hwc_flip(hd, buf);
316 if (ret) {
317 ALOGE("Failed to perform flip\n");
318 return ret;
319 }
Lauri Peltonen132e0102015-02-12 13:54:33 +0200320
Sean Paul6a55e9f2015-04-30 15:31:06 -0400321 if (hwc_import_bo_release(hd->ctx->drm.fd(), hd->ctx->import_ctx,
322 &hd->front)) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400323 struct drm_gem_close args;
324 memset(&args, 0, sizeof(args));
325 for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) {
326 if (!hd->front.gem_handles[i])
327 continue;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500328
Sean Paulef8f1f92015-04-29 16:05:23 -0400329 ret = pthread_mutex_lock(&hd->set_worker.lock);
330 if (ret) {
331 ALOGE("Failed to lock set lock in wait_and_set() %d", ret);
332 continue;
333 }
Allen Martin3d3f70a2015-02-21 21:20:17 -0800334
Sean Paulef8f1f92015-04-29 16:05:23 -0400335 /* check for duplicate handle in buf_queue */
336 bool found = false;
337 for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin();
338 bi != hd->buf_queue.end(); ++bi)
339 for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j)
340 if (hd->front.gem_handles[i] == bi->gem_handles[j])
341 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800342
Sean Paulef8f1f92015-04-29 16:05:23 -0400343 for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j)
344 if (hd->front.gem_handles[i] == buf->gem_handles[j])
345 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800346
Sean Paulef8f1f92015-04-29 16:05:23 -0400347 if (!found) {
348 args.handle = hd->front.gem_handles[i];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400349 drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args);
Sean Paulef8f1f92015-04-29 16:05:23 -0400350 }
351 if (pthread_mutex_unlock(&hd->set_worker.lock))
352 ALOGE("Failed to unlock set lock in wait_and_set() %d", ret);
353 }
354 }
Lauri Peltonen77d6d7a2015-02-23 20:44:16 +0200355
Sean Paulef8f1f92015-04-29 16:05:23 -0400356 hd->front = *buf;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800357
Sean Paulef8f1f92015-04-29 16:05:23 -0400358 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500359}
360
Sean Paulef8f1f92015-04-29 16:05:23 -0400361static void *hwc_set_worker(void *arg) {
362 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500363
Sean Paulef8f1f92015-04-29 16:05:23 -0400364 struct hwc_drm_display *hd = (struct hwc_drm_display *)arg;
365 int ret = pthread_mutex_lock(&hd->flip_lock);
366 if (ret) {
367 ALOGE("Failed to lock flip lock ret=%d", ret);
368 return NULL;
369 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500370
Sean Paulef8f1f92015-04-29 16:05:23 -0400371 do {
372 ret = pthread_mutex_lock(&hd->set_worker.lock);
373 if (ret) {
374 ALOGE("Failed to lock set lock %d", ret);
375 return NULL;
376 }
Sean Paul814bddb2015-03-03 17:46:19 -0500377
Sean Paulef8f1f92015-04-29 16:05:23 -0400378 if (hd->set_worker.exit)
379 break;
Sean Paul3bc48e82015-01-23 01:41:13 -0500380
Sean Paulef8f1f92015-04-29 16:05:23 -0400381 if (hd->buf_queue.empty()) {
382 ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock);
383 if (ret) {
384 ALOGE("Failed to wait on condition %d", ret);
385 break;
386 }
387 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500388
Sean Paulef8f1f92015-04-29 16:05:23 -0400389 struct hwc_drm_bo buf;
390 buf = hd->buf_queue.front();
391 hd->buf_queue.pop_front();
Sean Paul3bc48e82015-01-23 01:41:13 -0500392
Sean Paulef8f1f92015-04-29 16:05:23 -0400393 ret = pthread_mutex_unlock(&hd->set_worker.lock);
394 if (ret) {
395 ALOGE("Failed to unlock set lock %d", ret);
396 return NULL;
397 }
Sean Paul3bc48e82015-01-23 01:41:13 -0500398
Sean Paulef8f1f92015-04-29 16:05:23 -0400399 ret = hwc_wait_and_set(hd, &buf);
400 if (ret)
401 ALOGE("Failed to wait and set %d", ret);
Sean Paul3bc48e82015-01-23 01:41:13 -0500402
Sean Paulef8f1f92015-04-29 16:05:23 -0400403 ret = sw_sync_timeline_inc(hd->timeline_fd, 1);
404 if (ret)
405 ALOGE("Failed to increment sync timeline %d", ret);
406 } while (true);
Sean Paul3bc48e82015-01-23 01:41:13 -0500407
Sean Paulef8f1f92015-04-29 16:05:23 -0400408 ret = pthread_mutex_unlock(&hd->set_worker.lock);
409 if (ret)
410 ALOGE("Failed to unlock set lock while exiting %d", ret);
Sean Paulf1dc1912015-01-24 01:34:31 -0500411
Sean Paulef8f1f92015-04-29 16:05:23 -0400412 ret = pthread_mutex_unlock(&hd->flip_lock);
413 if (ret)
414 ALOGE("Failed to unlock flip lock ret=%d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500415
Sean Paulef8f1f92015-04-29 16:05:23 -0400416 return NULL;
417}
Sean Paul9aa5ad32015-01-22 15:47:54 -0500418
Sean Paulef8f1f92015-04-29 16:05:23 -0400419static void hwc_close_fences(hwc_display_contents_1_t *display_contents) {
420 for (int i = 0; i < (int)display_contents->numHwLayers; ++i) {
421 hwc_layer_1_t *layer = &display_contents->hwLayers[i];
422 if (layer->acquireFenceFd >= 0) {
423 close(layer->acquireFenceFd);
424 layer->acquireFenceFd = -1;
425 }
426 }
427 if (display_contents->outbufAcquireFenceFd >= 0) {
428 close(display_contents->outbufAcquireFenceFd);
429 display_contents->outbufAcquireFenceFd = -1;
430 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500431}
432
Sean Paule0c4c3d2015-01-20 16:56:04 -0500433static int hwc_set_display(hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -0400434 hwc_display_contents_1_t *display_contents) {
Sean Paule42febf2015-05-07 11:35:29 -0700435 struct hwc_drm_display *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400436 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display);
437 if (!crtc) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400438 ALOGE("There is no active crtc for display %d", display);
439 hwc_close_fences(display_contents);
440 return -ENOENT;
441 }
Sean Paul9b1bb842015-01-23 01:11:58 -0500442
Sean Paulef8f1f92015-04-29 16:05:23 -0400443 /*
444 * TODO: We can only support one hw layer atm, so choose either the
445 * first one or the framebuffer target.
446 */
447 hwc_layer_1_t *layer = NULL;
448 if (!display_contents->numHwLayers) {
449 return 0;
450 } else if (display_contents->numHwLayers == 1) {
451 layer = &display_contents->hwLayers[0];
452 } else {
453 int i;
454 for (i = 0; i < (int)display_contents->numHwLayers; ++i) {
455 layer = &display_contents->hwLayers[i];
456 if (layer->compositionType == HWC_FRAMEBUFFER_TARGET)
457 break;
458 }
459 if (i == (int)display_contents->numHwLayers) {
460 ALOGE("Could not find a suitable layer for display %d", display);
461 }
462 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500463
Sean Paule42febf2015-05-07 11:35:29 -0700464 int ret = pthread_mutex_lock(&hd->set_worker.lock);
Sean Paulef8f1f92015-04-29 16:05:23 -0400465 if (ret) {
466 ALOGE("Failed to lock set lock in set() %d", ret);
467 hwc_close_fences(display_contents);
468 return ret;
469 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500470
Sean Paulef8f1f92015-04-29 16:05:23 -0400471 struct hwc_drm_bo buf;
472 memset(&buf, 0, sizeof(buf));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400473 ret =
474 hwc_import_bo_create(ctx->drm.fd(), ctx->import_ctx, layer->handle, &buf);
Sean Paulef8f1f92015-04-29 16:05:23 -0400475 if (ret) {
476 ALOGE("Failed to import handle to drm bo %d", ret);
477 hwc_close_fences(display_contents);
478 return ret;
479 }
480 buf.acquire_fence_fd = layer->acquireFenceFd;
481 layer->acquireFenceFd = -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500482
Sean Paulef8f1f92015-04-29 16:05:23 -0400483 /*
484 * TODO: Retire and release can use the same sync point here b/c hwc is
485 * restricted to one layer. Once that is no longer true, this will need
486 * to change
487 */
488 ++hd->timeline_next;
489 display_contents->retireFenceFd = sw_sync_fence_create(
490 hd->timeline_fd, "drm_hwc_retire", hd->timeline_next);
491 layer->releaseFenceFd = sw_sync_fence_create(
492 hd->timeline_fd, "drm_hwc_release", hd->timeline_next);
493 hd->buf_queue.push_back(buf);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800494
Sean Paulef8f1f92015-04-29 16:05:23 -0400495 ret = pthread_cond_signal(&hd->set_worker.cond);
496 if (ret)
497 ALOGE("Failed to signal set worker %d", ret);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800498
Sean Paulef8f1f92015-04-29 16:05:23 -0400499 if (pthread_mutex_unlock(&hd->set_worker.lock))
500 ALOGE("Failed to unlock set lock in set()");
Sean Paul3bc48e82015-01-23 01:41:13 -0500501
Sean Paulef8f1f92015-04-29 16:05:23 -0400502 hwc_close_fences(display_contents);
503 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500504}
505
506static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400507 hwc_display_contents_1_t **display_contents) {
508 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500509
Sean Paulef8f1f92015-04-29 16:05:23 -0400510 int ret = 0;
Sean Paule42febf2015-05-07 11:35:29 -0700511 for (int i = 0; i < (int)num_displays; ++i) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400512 if (display_contents[i])
513 ret = hwc_set_display(ctx, i, display_contents[i]);
514 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500515
Sean Paulef8f1f92015-04-29 16:05:23 -0400516 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500517}
518
Sean Paulef8f1f92015-04-29 16:05:23 -0400519static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
520 int event, int enabled) {
521 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700522 struct hwc_drm_display *hd = &ctx->displays[display];
Sean Paulef8f1f92015-04-29 16:05:23 -0400523 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
524 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500525
Sean Paul6a55e9f2015-04-30 15:31:06 -0400526 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display);
527 if (!crtc) {
528 ALOGD("Can't service events for display %d, no crtc", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400529 return -EINVAL;
530 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500531
Sean Paulef8f1f92015-04-29 16:05:23 -0400532 hd->enable_vsync_events = !!enabled;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500533
Sean Paulef8f1f92015-04-29 16:05:23 -0400534 if (!hd->enable_vsync_events)
535 return 0;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500536
Sean Paulef8f1f92015-04-29 16:05:23 -0400537 /*
538 * Note that it's possible that the event worker is already waiting for
539 * a vsync, and this will be a duplicate request. In that event, we'll
540 * end up firing the event handler twice, and it will discard the second
541 * event. Not ideal, but not worth introducing a bunch of additional
542 * logic/locks/state for.
543 */
Sean Paule42febf2015-05-07 11:35:29 -0700544 int ret = hwc_queue_vblank_event(hd);
Sean Paulef8f1f92015-04-29 16:05:23 -0400545 if (ret) {
546 ALOGE("Failed to queue vblank event ret=%d", ret);
547 return ret;
548 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500549
Sean Paulef8f1f92015-04-29 16:05:23 -0400550 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500551}
552
Sean Paulef8f1f92015-04-29 16:05:23 -0400553static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
554 int mode) {
555 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500556
Sean Paul6a55e9f2015-04-30 15:31:06 -0400557 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400558 switch (mode) {
559 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400560 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400561 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500562
Sean Paulef8f1f92015-04-29 16:05:23 -0400563 /* We can't support dozing right now, so go full on */
564 case HWC_POWER_MODE_DOZE:
565 case HWC_POWER_MODE_DOZE_SUSPEND:
566 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400567 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400568 break;
569 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400570 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500571}
572
Sean Paulef8f1f92015-04-29 16:05:23 -0400573static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
574 int *value) {
575 switch (what) {
576 case HWC_BACKGROUND_LAYER_SUPPORTED:
577 *value = 0; /* TODO: We should do this */
578 break;
579 case HWC_VSYNC_PERIOD:
580 ALOGW("Query for deprecated vsync value, returning 60Hz");
581 *value = 1000 * 1000 * 1000 / 60;
582 break;
583 case HWC_DISPLAY_TYPES_SUPPORTED:
584 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
585 break;
586 }
587 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500588}
589
Sean Paulef8f1f92015-04-29 16:05:23 -0400590static void hwc_register_procs(struct hwc_composer_device_1 *dev,
591 hwc_procs_t const *procs) {
592 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500593
Sean Paulef8f1f92015-04-29 16:05:23 -0400594 ctx->procs = procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500595}
596
Sean Paulef8f1f92015-04-29 16:05:23 -0400597static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
598 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400599 size_t *num_configs) {
600 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400601 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500602
Sean Paulef8f1f92015-04-29 16:05:23 -0400603 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700604 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400605 hd->config_ids.clear();
606
607 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
608 if (!connector) {
609 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400610 return -ENODEV;
611 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500612
Sean Paule42febf2015-05-07 11:35:29 -0700613 int ret = connector->UpdateModes();
Sean Paul6a55e9f2015-04-30 15:31:06 -0400614 if (ret) {
615 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400616 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400617 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500618
Sean Paul6a55e9f2015-04-30 15:31:06 -0400619 for (DrmConnector::ModeIter iter = connector->begin_modes();
620 iter != connector->end_modes(); ++iter) {
621 size_t idx = hd->config_ids.size();
622 if (idx == *num_configs)
623 break;
624 hd->config_ids.push_back(iter->id());
625 configs[idx] = iter->id();
626 }
627 *num_configs = hd->config_ids.size();
628 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500629}
630
Sean Paulef8f1f92015-04-29 16:05:23 -0400631static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
632 int display, uint32_t config,
633 const uint32_t *attributes,
634 int32_t *values) {
635 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400636 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400637 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400638 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400639 return -ENODEV;
640 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400641 DrmMode mode;
642 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
643 ++iter) {
644 if (iter->id() == config) {
645 mode = *iter;
646 break;
647 }
648 }
649 if (mode.id() == 0) {
650 ALOGE("Failed to find active mode for display %d", display);
651 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400652 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500653
Sean Paul6a55e9f2015-04-30 15:31:06 -0400654 uint32_t mm_width = c->mm_width();
655 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400656 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
657 switch (attributes[i]) {
658 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400659 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400660 break;
661 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400662 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400663 break;
664 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400665 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400666 break;
667 case HWC_DISPLAY_DPI_X:
668 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400669 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400670 break;
671 case HWC_DISPLAY_DPI_Y:
672 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400673 values[i] =
674 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400675 break;
676 }
677 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400678 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500679}
680
Sean Paulef8f1f92015-04-29 16:05:23 -0400681static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
682 int display) {
683 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400684 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
685 if (!c) {
686 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400687 return -ENODEV;
688 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500689
Sean Paul6a55e9f2015-04-30 15:31:06 -0400690 DrmMode mode = c->active_mode();
Sean Paule42febf2015-05-07 11:35:29 -0700691 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400692 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
693 if (hd->config_ids[i] == mode.id())
694 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400695 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400696 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500697}
698
Sean Paulef8f1f92015-04-29 16:05:23 -0400699static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
700 int index) {
701 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700702 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400703 if (index >= (int)hd->config_ids.size()) {
704 ALOGE("Invalid config index %d passed in", index);
705 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400706 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500707
Sean Paule42febf2015-05-07 11:35:29 -0700708 int ret =
Sean Paul6a55e9f2015-04-30 15:31:06 -0400709 ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
710 if (ret) {
711 ALOGE("Failed to set config for display %d", display);
712 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400713 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500714
Sean Paul6a55e9f2015-04-30 15:31:06 -0400715 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500716}
717
Sean Paulef8f1f92015-04-29 16:05:23 -0400718static int hwc_destroy_worker(struct hwc_worker *worker) {
719 int ret = pthread_mutex_lock(&worker->lock);
720 if (ret) {
721 ALOGE("Failed to lock in destroy() %d", ret);
722 return ret;
723 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500724
Sean Paulef8f1f92015-04-29 16:05:23 -0400725 worker->exit = true;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500726
Sean Paulef8f1f92015-04-29 16:05:23 -0400727 ret |= pthread_cond_signal(&worker->cond);
728 if (ret)
729 ALOGE("Failed to signal cond in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500730
Sean Paulef8f1f92015-04-29 16:05:23 -0400731 ret |= pthread_mutex_unlock(&worker->lock);
732 if (ret)
733 ALOGE("Failed to unlock in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500734
Sean Paulef8f1f92015-04-29 16:05:23 -0400735 ret |= pthread_join(worker->thread, NULL);
736 if (ret && ret != ESRCH)
737 ALOGE("Failed to join thread in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500738
Sean Paulef8f1f92015-04-29 16:05:23 -0400739 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500740}
741
Sean Paulef8f1f92015-04-29 16:05:23 -0400742static void hwc_destroy_display(struct hwc_drm_display *hd) {
743 if (hwc_destroy_worker(&hd->set_worker))
744 ALOGE("Destroy set worker failed");
Sean Paul9aa5ad32015-01-22 15:47:54 -0500745}
746
Sean Paulef8f1f92015-04-29 16:05:23 -0400747static int hwc_device_close(struct hw_device_t *dev) {
748 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500749
Sean Paule42febf2015-05-07 11:35:29 -0700750 for (hwc_context_t::DisplayMapIter iter = ctx->displays.begin();
751 iter != ctx->displays.end(); ++iter)
752 hwc_destroy_display(&iter->second);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500753
Sean Paulef8f1f92015-04-29 16:05:23 -0400754 if (hwc_destroy_worker(&ctx->event_worker))
755 ALOGE("Destroy event worker failed");
Sean Paul814bddb2015-03-03 17:46:19 -0500756
Sean Paulef8f1f92015-04-29 16:05:23 -0400757 int ret = hwc_import_destroy(ctx->import_ctx);
758 if (ret)
759 ALOGE("Could not destroy import %d", ret);
Sean Paulcd36a9e2015-01-22 18:01:18 -0500760
Sean Paulef8f1f92015-04-29 16:05:23 -0400761 delete ctx;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500762
Sean Paulef8f1f92015-04-29 16:05:23 -0400763 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500764}
765
Sean Paul814bddb2015-03-03 17:46:19 -0500766static int hwc_initialize_worker(struct hwc_worker *worker,
Sean Paulef8f1f92015-04-29 16:05:23 -0400767 void *(*routine)(void *), void *arg) {
768 int ret = pthread_cond_init(&worker->cond, NULL);
769 if (ret) {
770 ALOGE("Failed to create worker condition %d", ret);
771 return ret;
772 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500773
Sean Paulef8f1f92015-04-29 16:05:23 -0400774 ret = pthread_mutex_init(&worker->lock, NULL);
775 if (ret) {
776 ALOGE("Failed to initialize worker lock %d", ret);
777 pthread_cond_destroy(&worker->cond);
778 return ret;
779 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500780
Sean Paulef8f1f92015-04-29 16:05:23 -0400781 worker->exit = false;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500782
Sean Paulef8f1f92015-04-29 16:05:23 -0400783 ret = pthread_create(&worker->thread, NULL, routine, arg);
784 if (ret) {
785 ALOGE("Could not create worker thread %d", ret);
786 pthread_mutex_destroy(&worker->lock);
787 pthread_cond_destroy(&worker->cond);
788 return ret;
789 }
790 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500791}
792
Sean Paul24a26e32015-02-04 10:34:47 -0800793/*
794 * TODO: This function sets the active config to the first one in the list. This
795 * should be fixed such that it selects the preferred mode for the display, or
796 * some other, saner, method of choosing the config.
797 */
Sean Paule42febf2015-05-07 11:35:29 -0700798static int hwc_set_initial_config(hwc_drm_display_t *hd) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400799 uint32_t config;
800 size_t num_configs = 1;
801 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
802 &num_configs);
803 if (ret || !num_configs)
804 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800805
Sean Paulef8f1f92015-04-29 16:05:23 -0400806 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
807 if (ret) {
808 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
809 return ret;
810 }
Sean Paul24a26e32015-02-04 10:34:47 -0800811
Sean Paulef8f1f92015-04-29 16:05:23 -0400812 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800813}
814
Sean Paul6a55e9f2015-04-30 15:31:06 -0400815static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paule42febf2015-05-07 11:35:29 -0700816 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paulef8f1f92015-04-29 16:05:23 -0400817 hd->ctx = ctx;
818 hd->display = display;
Sean Paulef8f1f92015-04-29 16:05:23 -0400819 hd->enable_vsync_events = false;
820 hd->vsync_sequence = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500821
Sean Paule42febf2015-05-07 11:35:29 -0700822 int ret = pthread_mutex_init(&hd->flip_lock, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400823 if (ret) {
824 ALOGE("Failed to initialize flip lock %d", ret);
825 return ret;
826 }
Sean Paul814bddb2015-03-03 17:46:19 -0500827
Sean Paulef8f1f92015-04-29 16:05:23 -0400828 ret = pthread_cond_init(&hd->flip_cond, NULL);
829 if (ret) {
830 ALOGE("Failed to intiialize flip condition %d", ret);
831 pthread_mutex_destroy(&hd->flip_lock);
832 return ret;
833 }
Sean Paul814bddb2015-03-03 17:46:19 -0500834
Sean Paulef8f1f92015-04-29 16:05:23 -0400835 ret = sw_sync_timeline_create();
836 if (ret < 0) {
837 ALOGE("Failed to create sw sync timeline %d", ret);
838 pthread_cond_destroy(&hd->flip_cond);
839 pthread_mutex_destroy(&hd->flip_lock);
840 return ret;
841 }
842 hd->timeline_fd = ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500843
Sean Paulef8f1f92015-04-29 16:05:23 -0400844 /*
845 * Initialize timeline_next to 1, because point 0 will be the very first
846 * set operation. Since we increment every time set() is called,
847 * initializing to 0 would cause an off-by-one error where
848 * surfaceflinger would composite on the front buffer.
849 */
850 hd->timeline_next = 1;
Sean Paule147a2a2015-02-22 17:55:43 -0500851
Sean Paulef8f1f92015-04-29 16:05:23 -0400852 ret = hwc_set_initial_config(hd);
853 if (ret) {
854 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
855 close(hd->timeline_fd);
856 pthread_cond_destroy(&hd->flip_cond);
857 pthread_mutex_destroy(&hd->flip_lock);
858 return ret;
859 }
Sean Paulf1dc1912015-01-24 01:34:31 -0500860
Sean Paulef8f1f92015-04-29 16:05:23 -0400861 ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd);
862 if (ret) {
863 ALOGE("Failed to create set worker %d\n", ret);
864 close(hd->timeline_fd);
865 pthread_cond_destroy(&hd->flip_cond);
866 pthread_mutex_destroy(&hd->flip_lock);
867 return ret;
868 }
Sean Paul24a26e32015-02-04 10:34:47 -0800869
Sean Paulef8f1f92015-04-29 16:05:23 -0400870 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500871}
872
Sean Paulef8f1f92015-04-29 16:05:23 -0400873static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) {
874 for (int i = 0; i < num_conn; ++i) {
875 if (conn_list[i])
876 drmModeFreeConnector(conn_list[i]);
877 }
878 free(conn_list);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500879}
880
Sean Paulef8f1f92015-04-29 16:05:23 -0400881static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400882 int ret;
883 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
884 c != ctx->drm.end_connectors(); ++c) {
885 ret = hwc_initialize_display(ctx, (*c)->display());
886 if (ret) {
887 ALOGE("Failed to initialize display %d", (*c)->display());
888 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400889 }
890 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400891
892 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500893}
894
Sean Paulef8f1f92015-04-29 16:05:23 -0400895static int hwc_device_open(const struct hw_module_t *module, const char *name,
896 struct hw_device_t **dev) {
897 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
898 ALOGE("Invalid module name- %s", name);
899 return -EINVAL;
900 }
901
902 struct hwc_context_t *ctx = new hwc_context_t();
903 if (!ctx) {
904 ALOGE("Failed to allocate hwc context");
905 return -ENOMEM;
906 }
907
Sean Paul6a55e9f2015-04-30 15:31:06 -0400908 int ret = ctx->drm.Init();
909 if (ret) {
910 ALOGE("Can't initialize Drm object %d", ret);
911 delete ctx;
912 return ret;
913 }
914
915 ret = hwc_import_init(&ctx->import_ctx);
Sean Paulef8f1f92015-04-29 16:05:23 -0400916 if (ret) {
917 ALOGE("Failed to initialize import context");
918 delete ctx;
919 return ret;
920 }
921
Sean Paulef8f1f92015-04-29 16:05:23 -0400922 ret = hwc_enumerate_displays(ctx);
923 if (ret) {
924 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400925 delete ctx;
926 return ret;
927 }
928
929 ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx);
930 if (ret) {
931 ALOGE("Failed to create event worker %d\n", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400932 delete ctx;
933 return ret;
934 }
935
936 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
937 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
938 ctx->device.common.module = const_cast<hw_module_t *>(module);
939 ctx->device.common.close = hwc_device_close;
940
941 ctx->device.prepare = hwc_prepare;
942 ctx->device.set = hwc_set;
943 ctx->device.eventControl = hwc_event_control;
944 ctx->device.setPowerMode = hwc_set_power_mode;
945 ctx->device.query = hwc_query;
946 ctx->device.registerProcs = hwc_register_procs;
947 ctx->device.getDisplayConfigs = hwc_get_display_configs;
948 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
949 ctx->device.getActiveConfig = hwc_get_active_config;
950 ctx->device.setActiveConfig = hwc_set_active_config;
951 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
952
953 *dev = &ctx->device.common;
954
955 return 0;
956}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400957}
Sean Paulef8f1f92015-04-29 16:05:23 -0400958
Sean Paul6a55e9f2015-04-30 15:31:06 -0400959static struct hw_module_methods_t hwc_module_methods = {
960 open : android::hwc_device_open
961};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500962
963hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -0400964 common : {
965 tag : HARDWARE_MODULE_TAG,
966 version_major : 1,
967 version_minor : 0,
968 id : HWC_HARDWARE_MODULE_ID,
969 name : "DRM hwcomposer module",
970 author : "The Android Open Source Project",
971 methods : &hwc_module_methods,
972 dso : NULL,
973 reserved : {0},
974 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500975};