blob: 06c09312c4d96910ad4423e0cb8d6b03c5e82086 [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Sean Paulda6270d2015-06-01 14:11:52 -040021#include "importer.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040022
Sean Paule0c4c3d2015-01-20 16:56:04 -050023#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040024#include <fcntl.h>
Sean Paul5ad302c2015-05-11 10:43:31 -070025#include <list>
Sean Paule42febf2015-05-07 11:35:29 -070026#include <map>
Sean Paulef8f1f92015-04-29 16:05:23 -040027#include <pthread.h>
Dan Albertc5255b32015-05-07 23:42:54 -070028#include <stdlib.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050029#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050030#include <sys/resource.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050031#include <xf86drm.h>
32#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050033
Sean Paulef8f1f92015-04-29 16:05:23 -040034#include <cutils/log.h>
35#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050036#include <hardware/hardware.h>
37#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050038#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040039#include <sync/sync.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050040
41#define ARRAY_SIZE(arr) (int)(sizeof(arr) / sizeof((arr)[0]))
42
Sean Paule0c4c3d2015-01-20 16:56:04 -050043#define UM_PER_INCH 25400
44
Sean Paul6a55e9f2015-04-30 15:31:06 -040045namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050046
Sean Paul9aa5ad32015-01-22 15:47:54 -050047struct hwc_worker {
Sean Paulef8f1f92015-04-29 16:05:23 -040048 pthread_t thread;
49 pthread_mutex_t lock;
50 pthread_cond_t cond;
51 bool exit;
Sean Paul9aa5ad32015-01-22 15:47:54 -050052};
53
Sean Paule42febf2015-05-07 11:35:29 -070054typedef struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -040055 struct hwc_context_t *ctx;
56 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -050057
Sean Paul6a55e9f2015-04-30 15:31:06 -040058 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -050059
Sean Paulef8f1f92015-04-29 16:05:23 -040060 struct hwc_worker set_worker;
Sean Paul9aa5ad32015-01-22 15:47:54 -050061
Sean Paulef8f1f92015-04-29 16:05:23 -040062 std::list<struct hwc_drm_bo> buf_queue;
63 struct hwc_drm_bo front;
64 pthread_mutex_t flip_lock;
65 pthread_cond_t flip_cond;
Sean Paulf1dc1912015-01-24 01:34:31 -050066
Sean Paulef8f1f92015-04-29 16:05:23 -040067 int timeline_fd;
68 unsigned timeline_next;
Sean Pauleb9e75c2015-01-25 23:31:30 -050069
Sean Paulef8f1f92015-04-29 16:05:23 -040070 bool enable_vsync_events;
71 unsigned int vsync_sequence;
Sean Paule42febf2015-05-07 11:35:29 -070072} hwc_drm_display_t;
Sean Paule0c4c3d2015-01-20 16:56:04 -050073
74struct hwc_context_t {
Sean Paule42febf2015-05-07 11:35:29 -070075 // map of display:hwc_drm_display_t
76 typedef std::map<int, hwc_drm_display_t> DisplayMap;
77 typedef DisplayMap::iterator DisplayMapIter;
Sean Paule0c4c3d2015-01-20 16:56:04 -050078
Sean Paulda6270d2015-06-01 14:11:52 -040079 hwc_context_t() : procs(NULL), importer(NULL) {
80 }
81
82 ~hwc_context_t() {
83 delete importer;
84 }
85
Sean Paule42febf2015-05-07 11:35:29 -070086 hwc_composer_device_1_t device;
Sean Paulef8f1f92015-04-29 16:05:23 -040087 hwc_procs_t const *procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -050088
Sean Paulef8f1f92015-04-29 16:05:23 -040089 struct hwc_worker event_worker;
Sean Paul6a55e9f2015-04-30 15:31:06 -040090
Sean Paule42febf2015-05-07 11:35:29 -070091 DisplayMap displays;
Sean Paul6a55e9f2015-04-30 15:31:06 -040092 DrmResources drm;
Sean Paulda6270d2015-06-01 14:11:52 -040093 Importer *importer;
Sean Paule0c4c3d2015-01-20 16:56:04 -050094};
95
Sean Paulef8f1f92015-04-29 16:05:23 -040096static int hwc_prepare_layer(hwc_layer_1_t *layer) {
97 /* TODO: We can't handle background right now, defer to sufaceFlinger */
98 if (layer->compositionType == HWC_BACKGROUND) {
99 layer->compositionType = HWC_FRAMEBUFFER;
100 ALOGV("Can't handle background layers yet");
Sean Paule0c4c3d2015-01-20 16:56:04 -0500101
Sean Paulef8f1f92015-04-29 16:05:23 -0400102 /* TODO: Support sideband compositions */
103 } else if (layer->compositionType == HWC_SIDEBAND) {
104 layer->compositionType = HWC_FRAMEBUFFER;
105 ALOGV("Can't handle sideband content yet");
106 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500107
Sean Paulef8f1f92015-04-29 16:05:23 -0400108 layer->hints = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500109
Sean Paulef8f1f92015-04-29 16:05:23 -0400110 /* TODO: Handle cursor by setting compositionType=HWC_CURSOR_OVERLAY */
111 if (layer->flags & HWC_IS_CURSOR_LAYER) {
112 ALOGV("Can't handle async cursors yet");
113 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500114
Sean Paulef8f1f92015-04-29 16:05:23 -0400115 /* TODO: Handle transformations */
116 if (layer->transform) {
117 ALOGV("Can't handle transformations yet");
118 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500119
Sean Paulef8f1f92015-04-29 16:05:23 -0400120 /* TODO: Handle blending & plane alpha*/
121 if (layer->blending == HWC_BLENDING_PREMULT ||
122 layer->blending == HWC_BLENDING_COVERAGE) {
123 ALOGV("Can't handle blending yet");
124 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500125
Sean Paulef8f1f92015-04-29 16:05:23 -0400126 /* TODO: Handle cropping & scaling */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500127
Sean Paulef8f1f92015-04-29 16:05:23 -0400128 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500129}
130
Sean Paulef8f1f92015-04-29 16:05:23 -0400131static int hwc_prepare(hwc_composer_device_1_t * /* dev */, size_t num_displays,
132 hwc_display_contents_1_t **display_contents) {
133 /* TODO: Check flags for HWC_GEOMETRY_CHANGED */
Sean Paule0c4c3d2015-01-20 16:56:04 -0500134
Sean Paule42febf2015-05-07 11:35:29 -0700135 for (int i = 0; i < (int)num_displays; ++i) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400136 if (!display_contents[i])
137 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500138
Sean Paulef8f1f92015-04-29 16:05:23 -0400139 for (int j = 0; j < (int)display_contents[i]->numHwLayers; ++j) {
140 int ret = hwc_prepare_layer(&display_contents[i]->hwLayers[j]);
141 if (ret) {
142 ALOGE("Failed to prepare layer %d:%d", j, i);
143 return ret;
144 }
145 }
146 }
Sean Pauldffca952015-02-04 10:19:55 -0800147
Sean Paulef8f1f92015-04-29 16:05:23 -0400148 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500149}
150
Sean Paulef8f1f92015-04-29 16:05:23 -0400151static int hwc_queue_vblank_event(struct hwc_drm_display *hd) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400152 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
153 if (!crtc) {
154 ALOGE("Failed to get crtc for display");
155 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400156 }
Sean Paul814bddb2015-03-03 17:46:19 -0500157
Sean Paulef8f1f92015-04-29 16:05:23 -0400158 drmVBlank vblank;
159 memset(&vblank, 0, sizeof(vblank));
Sean Paul814bddb2015-03-03 17:46:19 -0500160
Sean Paul6a55e9f2015-04-30 15:31:06 -0400161 uint32_t high_crtc = (crtc->pipe() << DRM_VBLANK_HIGH_CRTC_SHIFT);
Sean Paulef8f1f92015-04-29 16:05:23 -0400162 vblank.request.type = (drmVBlankSeqType)(
163 DRM_VBLANK_ABSOLUTE | DRM_VBLANK_NEXTONMISS | DRM_VBLANK_EVENT |
164 (high_crtc & DRM_VBLANK_HIGH_CRTC_MASK));
165 vblank.request.signal = (unsigned long)hd;
166 vblank.request.sequence = hd->vsync_sequence + 1;
Sean Paul814bddb2015-03-03 17:46:19 -0500167
Sean Paul6a55e9f2015-04-30 15:31:06 -0400168 int ret = drmWaitVBlank(hd->ctx->drm.fd(), &vblank);
Sean Paulef8f1f92015-04-29 16:05:23 -0400169 if (ret) {
170 ALOGE("Failed to wait for vblank %d", ret);
171 return ret;
172 }
Sean Paul814bddb2015-03-03 17:46:19 -0500173
Sean Paulef8f1f92015-04-29 16:05:23 -0400174 return 0;
Sean Paul814bddb2015-03-03 17:46:19 -0500175}
176
177static void hwc_vblank_event_handler(int /* fd */, unsigned int sequence,
Sean Paulef8f1f92015-04-29 16:05:23 -0400178 unsigned int tv_sec, unsigned int tv_usec,
179 void *user_data) {
180 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500181
Sean Paulef8f1f92015-04-29 16:05:23 -0400182 if (!hd->enable_vsync_events || !hd->ctx->procs->vsync)
183 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500184
Sean Paulef8f1f92015-04-29 16:05:23 -0400185 /*
186 * Discard duplicate vsync (can happen when enabling vsync events while
187 * already processing vsyncs).
188 */
189 if (sequence <= hd->vsync_sequence)
190 return;
Sean Paul814bddb2015-03-03 17:46:19 -0500191
Sean Paulef8f1f92015-04-29 16:05:23 -0400192 hd->vsync_sequence = sequence;
193 int ret = hwc_queue_vblank_event(hd);
194 if (ret)
195 ALOGE("Failed to queue vblank event ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500196
Sean Paulef8f1f92015-04-29 16:05:23 -0400197 int64_t timestamp =
198 (int64_t)tv_sec * 1000 * 1000 * 1000 + (int64_t)tv_usec * 1000;
199 hd->ctx->procs->vsync(hd->ctx->procs, hd->display, timestamp);
Sean Paul814bddb2015-03-03 17:46:19 -0500200}
201
202static void hwc_flip_event_handler(int /* fd */, unsigned int /* sequence */,
Sean Paulef8f1f92015-04-29 16:05:23 -0400203 unsigned int /* tv_sec */,
204 unsigned int /* tv_usec */,
205 void *user_data) {
206 struct hwc_drm_display *hd = (struct hwc_drm_display *)user_data;
Sean Paul814bddb2015-03-03 17:46:19 -0500207
Sean Paulef8f1f92015-04-29 16:05:23 -0400208 int ret = pthread_mutex_lock(&hd->flip_lock);
209 if (ret) {
210 ALOGE("Failed to lock flip lock ret=%d", ret);
211 return;
212 }
Sean Paul814bddb2015-03-03 17:46:19 -0500213
Sean Paulef8f1f92015-04-29 16:05:23 -0400214 ret = pthread_cond_signal(&hd->flip_cond);
215 if (ret)
216 ALOGE("Failed to signal flip condition ret=%d", ret);
Sean Paul814bddb2015-03-03 17:46:19 -0500217
Sean Paulef8f1f92015-04-29 16:05:23 -0400218 ret = pthread_mutex_unlock(&hd->flip_lock);
219 if (ret) {
220 ALOGE("Failed to unlock flip lock ret=%d", ret);
221 return;
222 }
Sean Paul814bddb2015-03-03 17:46:19 -0500223}
224
Sean Paulef8f1f92015-04-29 16:05:23 -0400225static void *hwc_event_worker(void *arg) {
226 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul814bddb2015-03-03 17:46:19 -0500227
Sean Paulef8f1f92015-04-29 16:05:23 -0400228 struct hwc_context_t *ctx = (struct hwc_context_t *)arg;
229 do {
230 fd_set fds;
231 FD_ZERO(&fds);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400232 FD_SET(ctx->drm.fd(), &fds);
Sean Paul814bddb2015-03-03 17:46:19 -0500233
Sean Paulef8f1f92015-04-29 16:05:23 -0400234 drmEventContext event_context;
235 event_context.version = DRM_EVENT_CONTEXT_VERSION;
236 event_context.page_flip_handler = hwc_flip_event_handler;
237 event_context.vblank_handler = hwc_vblank_event_handler;
Sean Paul814bddb2015-03-03 17:46:19 -0500238
Sean Paulef8f1f92015-04-29 16:05:23 -0400239 int ret;
240 do {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400241 ret = select(ctx->drm.fd() + 1, &fds, NULL, NULL, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400242 } while (ret == -1 && errno == EINTR);
Sean Paul814bddb2015-03-03 17:46:19 -0500243
Sean Paulef8f1f92015-04-29 16:05:23 -0400244 if (ret != 1) {
245 ALOGE("Failed waiting for drm event\n");
246 continue;
247 }
Sean Paul814bddb2015-03-03 17:46:19 -0500248
Sean Paul6a55e9f2015-04-30 15:31:06 -0400249 drmHandleEvent(ctx->drm.fd(), &event_context);
Sean Paulef8f1f92015-04-29 16:05:23 -0400250 } while (true);
Sean Paul814bddb2015-03-03 17:46:19 -0500251
Sean Paulef8f1f92015-04-29 16:05:23 -0400252 return NULL;
Sean Paul814bddb2015-03-03 17:46:19 -0500253}
254
Sean Paulef8f1f92015-04-29 16:05:23 -0400255static bool hwc_mode_is_equal(drmModeModeInfoPtr a, drmModeModeInfoPtr b) {
256 return a->clock == b->clock && a->hdisplay == b->hdisplay &&
257 a->hsync_start == b->hsync_start && a->hsync_end == b->hsync_end &&
258 a->htotal == b->htotal && a->hskew == b->hskew &&
259 a->vdisplay == b->vdisplay && a->vsync_start == b->vsync_start &&
260 a->vsync_end == b->vsync_end && a->vtotal == b->vtotal &&
261 a->vscan == b->vscan && a->vrefresh == b->vrefresh &&
262 a->flags == b->flags && a->type == b->type &&
263 !strcmp(a->name, b->name);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500264}
265
Sean Paul6a55e9f2015-04-30 15:31:06 -0400266static int hwc_flip(struct hwc_drm_display *hd, struct hwc_drm_bo *buf) {
267 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(hd->display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400268 if (!crtc) {
269 ALOGE("Failed to get crtc for display %d", hd->display);
270 return -ENODEV;
271 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800272
Sean Paul6a55e9f2015-04-30 15:31:06 -0400273 DrmConnector *connector = hd->ctx->drm.GetConnectorForDisplay(hd->display);
274 if (!connector) {
275 ALOGE("Failed to get connector for display %d", hd->display);
276 return -ENODEV;
Sean Paulef8f1f92015-04-29 16:05:23 -0400277 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400278
279 int ret;
280 if (crtc->requires_modeset()) {
281 drmModeModeInfo drm_mode;
282 connector->active_mode().ToModeModeInfo(&drm_mode);
283 uint32_t connector_id = connector->id();
284 ret = drmModeSetCrtc(hd->ctx->drm.fd(), crtc->id(), buf->fb_id, 0, 0,
285 &connector_id, 1, &drm_mode);
Sean Paulef8f1f92015-04-29 16:05:23 -0400286 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400287 ALOGE("Modeset failed for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400288 return ret;
289 }
Sean Paulc0027942015-05-13 06:27:37 -0700290 crtc->set_requires_modeset(false);
Sean Paulef8f1f92015-04-29 16:05:23 -0400291 return 0;
292 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500293
Sean Paul6a55e9f2015-04-30 15:31:06 -0400294 ret = drmModePageFlip(hd->ctx->drm.fd(), crtc->id(), buf->fb_id,
Sean Paulef8f1f92015-04-29 16:05:23 -0400295 DRM_MODE_PAGE_FLIP_EVENT, hd);
296 if (ret) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400297 ALOGE("Failed to flip buffer for crtc %d", crtc->id());
Sean Paulef8f1f92015-04-29 16:05:23 -0400298 return ret;
299 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500300
Sean Paulef8f1f92015-04-29 16:05:23 -0400301 ret = pthread_cond_wait(&hd->flip_cond, &hd->flip_lock);
302 if (ret) {
303 ALOGE("Failed to wait on condition %d", ret);
304 return ret;
305 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500306
Sean Paulef8f1f92015-04-29 16:05:23 -0400307 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500308}
309
Sean Paul3bc48e82015-01-23 01:41:13 -0500310static int hwc_wait_and_set(struct hwc_drm_display *hd,
Sean Paulef8f1f92015-04-29 16:05:23 -0400311 struct hwc_drm_bo *buf) {
312 int ret;
313 if (buf->acquire_fence_fd >= 0) {
314 ret = sync_wait(buf->acquire_fence_fd, -1);
315 close(buf->acquire_fence_fd);
316 buf->acquire_fence_fd = -1;
317 if (ret) {
318 ALOGE("Failed to wait for acquire %d", ret);
319 return ret;
320 }
321 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500322
Sean Paulef8f1f92015-04-29 16:05:23 -0400323 ret = hwc_flip(hd, buf);
324 if (ret) {
325 ALOGE("Failed to perform flip\n");
326 return ret;
327 }
Lauri Peltonen132e0102015-02-12 13:54:33 +0200328
Sean Paulda6270d2015-06-01 14:11:52 -0400329 if (!hd->ctx->importer->ReleaseBuffer(buf)) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400330 struct drm_gem_close args;
331 memset(&args, 0, sizeof(args));
332 for (int i = 0; i < ARRAY_SIZE(hd->front.gem_handles); ++i) {
333 if (!hd->front.gem_handles[i])
334 continue;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500335
Sean Paulef8f1f92015-04-29 16:05:23 -0400336 ret = pthread_mutex_lock(&hd->set_worker.lock);
337 if (ret) {
338 ALOGE("Failed to lock set lock in wait_and_set() %d", ret);
339 continue;
340 }
Allen Martin3d3f70a2015-02-21 21:20:17 -0800341
Sean Paulef8f1f92015-04-29 16:05:23 -0400342 /* check for duplicate handle in buf_queue */
343 bool found = false;
344 for (std::list<struct hwc_drm_bo>::iterator bi = hd->buf_queue.begin();
345 bi != hd->buf_queue.end(); ++bi)
346 for (int j = 0; j < ARRAY_SIZE(bi->gem_handles); ++j)
347 if (hd->front.gem_handles[i] == bi->gem_handles[j])
348 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800349
Sean Paulef8f1f92015-04-29 16:05:23 -0400350 for (int j = 0; j < ARRAY_SIZE(buf->gem_handles); ++j)
351 if (hd->front.gem_handles[i] == buf->gem_handles[j])
352 found = true;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800353
Sean Paulef8f1f92015-04-29 16:05:23 -0400354 if (!found) {
355 args.handle = hd->front.gem_handles[i];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400356 drmIoctl(hd->ctx->drm.fd(), DRM_IOCTL_GEM_CLOSE, &args);
Sean Paulef8f1f92015-04-29 16:05:23 -0400357 }
358 if (pthread_mutex_unlock(&hd->set_worker.lock))
359 ALOGE("Failed to unlock set lock in wait_and_set() %d", ret);
360 }
361 }
Lauri Peltonen77d6d7a2015-02-23 20:44:16 +0200362
Sean Paulef8f1f92015-04-29 16:05:23 -0400363 hd->front = *buf;
Allen Martin3d3f70a2015-02-21 21:20:17 -0800364
Sean Paulef8f1f92015-04-29 16:05:23 -0400365 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500366}
367
Sean Paulef8f1f92015-04-29 16:05:23 -0400368static void *hwc_set_worker(void *arg) {
369 setpriority(PRIO_PROCESS, 0, HAL_PRIORITY_URGENT_DISPLAY);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500370
Sean Paulef8f1f92015-04-29 16:05:23 -0400371 struct hwc_drm_display *hd = (struct hwc_drm_display *)arg;
372 int ret = pthread_mutex_lock(&hd->flip_lock);
373 if (ret) {
374 ALOGE("Failed to lock flip lock ret=%d", ret);
375 return NULL;
376 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500377
Sean Paulef8f1f92015-04-29 16:05:23 -0400378 do {
379 ret = pthread_mutex_lock(&hd->set_worker.lock);
380 if (ret) {
381 ALOGE("Failed to lock set lock %d", ret);
382 return NULL;
383 }
Sean Paul814bddb2015-03-03 17:46:19 -0500384
Sean Paulef8f1f92015-04-29 16:05:23 -0400385 if (hd->set_worker.exit)
386 break;
Sean Paul3bc48e82015-01-23 01:41:13 -0500387
Sean Paulef8f1f92015-04-29 16:05:23 -0400388 if (hd->buf_queue.empty()) {
389 ret = pthread_cond_wait(&hd->set_worker.cond, &hd->set_worker.lock);
390 if (ret) {
391 ALOGE("Failed to wait on condition %d", ret);
392 break;
393 }
394 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500395
Sean Paulef8f1f92015-04-29 16:05:23 -0400396 struct hwc_drm_bo buf;
397 buf = hd->buf_queue.front();
398 hd->buf_queue.pop_front();
Sean Paul3bc48e82015-01-23 01:41:13 -0500399
Sean Paulef8f1f92015-04-29 16:05:23 -0400400 ret = pthread_mutex_unlock(&hd->set_worker.lock);
401 if (ret) {
402 ALOGE("Failed to unlock set lock %d", ret);
403 return NULL;
404 }
Sean Paul3bc48e82015-01-23 01:41:13 -0500405
Sean Paulef8f1f92015-04-29 16:05:23 -0400406 ret = hwc_wait_and_set(hd, &buf);
407 if (ret)
408 ALOGE("Failed to wait and set %d", ret);
Sean Paul3bc48e82015-01-23 01:41:13 -0500409
Sean Paulef8f1f92015-04-29 16:05:23 -0400410 ret = sw_sync_timeline_inc(hd->timeline_fd, 1);
411 if (ret)
412 ALOGE("Failed to increment sync timeline %d", ret);
413 } while (true);
Sean Paul3bc48e82015-01-23 01:41:13 -0500414
Sean Paulef8f1f92015-04-29 16:05:23 -0400415 ret = pthread_mutex_unlock(&hd->set_worker.lock);
416 if (ret)
417 ALOGE("Failed to unlock set lock while exiting %d", ret);
Sean Paulf1dc1912015-01-24 01:34:31 -0500418
Sean Paulef8f1f92015-04-29 16:05:23 -0400419 ret = pthread_mutex_unlock(&hd->flip_lock);
420 if (ret)
421 ALOGE("Failed to unlock flip lock ret=%d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500422
Sean Paulef8f1f92015-04-29 16:05:23 -0400423 return NULL;
424}
Sean Paul9aa5ad32015-01-22 15:47:54 -0500425
Sean Paulef8f1f92015-04-29 16:05:23 -0400426static void hwc_close_fences(hwc_display_contents_1_t *display_contents) {
427 for (int i = 0; i < (int)display_contents->numHwLayers; ++i) {
428 hwc_layer_1_t *layer = &display_contents->hwLayers[i];
429 if (layer->acquireFenceFd >= 0) {
430 close(layer->acquireFenceFd);
431 layer->acquireFenceFd = -1;
432 }
433 }
434 if (display_contents->outbufAcquireFenceFd >= 0) {
435 close(display_contents->outbufAcquireFenceFd);
436 display_contents->outbufAcquireFenceFd = -1;
437 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500438}
439
Sean Paule0c4c3d2015-01-20 16:56:04 -0500440static int hwc_set_display(hwc_context_t *ctx, int display,
Sean Paulef8f1f92015-04-29 16:05:23 -0400441 hwc_display_contents_1_t *display_contents) {
Sean Paule42febf2015-05-07 11:35:29 -0700442 struct hwc_drm_display *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400443 DrmCrtc *crtc = hd->ctx->drm.GetCrtcForDisplay(display);
444 if (!crtc) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400445 ALOGE("There is no active crtc for display %d", display);
446 hwc_close_fences(display_contents);
447 return -ENOENT;
448 }
Sean Paul9b1bb842015-01-23 01:11:58 -0500449
Sean Paulef8f1f92015-04-29 16:05:23 -0400450 /*
451 * TODO: We can only support one hw layer atm, so choose either the
452 * first one or the framebuffer target.
453 */
454 hwc_layer_1_t *layer = NULL;
455 if (!display_contents->numHwLayers) {
456 return 0;
457 } else if (display_contents->numHwLayers == 1) {
458 layer = &display_contents->hwLayers[0];
459 } else {
460 int i;
461 for (i = 0; i < (int)display_contents->numHwLayers; ++i) {
462 layer = &display_contents->hwLayers[i];
463 if (layer->compositionType == HWC_FRAMEBUFFER_TARGET)
464 break;
465 }
466 if (i == (int)display_contents->numHwLayers) {
467 ALOGE("Could not find a suitable layer for display %d", display);
468 }
469 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500470
Sean Paule42febf2015-05-07 11:35:29 -0700471 int ret = pthread_mutex_lock(&hd->set_worker.lock);
Sean Paulef8f1f92015-04-29 16:05:23 -0400472 if (ret) {
473 ALOGE("Failed to lock set lock in set() %d", ret);
474 hwc_close_fences(display_contents);
475 return ret;
476 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500477
Sean Paulef8f1f92015-04-29 16:05:23 -0400478 struct hwc_drm_bo buf;
Sean Paulda6270d2015-06-01 14:11:52 -0400479 ret = ctx->importer->ImportBuffer(layer->handle, &buf);
Sean Paulef8f1f92015-04-29 16:05:23 -0400480 if (ret) {
481 ALOGE("Failed to import handle to drm bo %d", ret);
482 hwc_close_fences(display_contents);
483 return ret;
484 }
485 buf.acquire_fence_fd = layer->acquireFenceFd;
486 layer->acquireFenceFd = -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500487
Sean Paulef8f1f92015-04-29 16:05:23 -0400488 /*
489 * TODO: Retire and release can use the same sync point here b/c hwc is
490 * restricted to one layer. Once that is no longer true, this will need
491 * to change
492 */
493 ++hd->timeline_next;
494 display_contents->retireFenceFd = sw_sync_fence_create(
495 hd->timeline_fd, "drm_hwc_retire", hd->timeline_next);
496 layer->releaseFenceFd = sw_sync_fence_create(
497 hd->timeline_fd, "drm_hwc_release", hd->timeline_next);
498 hd->buf_queue.push_back(buf);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800499
Sean Paulef8f1f92015-04-29 16:05:23 -0400500 ret = pthread_cond_signal(&hd->set_worker.cond);
501 if (ret)
502 ALOGE("Failed to signal set worker %d", ret);
Allen Martin3d3f70a2015-02-21 21:20:17 -0800503
Sean Paulef8f1f92015-04-29 16:05:23 -0400504 if (pthread_mutex_unlock(&hd->set_worker.lock))
505 ALOGE("Failed to unlock set lock in set()");
Sean Paul3bc48e82015-01-23 01:41:13 -0500506
Sean Paulef8f1f92015-04-29 16:05:23 -0400507 hwc_close_fences(display_contents);
508 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500509}
510
511static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400512 hwc_display_contents_1_t **display_contents) {
513 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500514
Sean Paulef8f1f92015-04-29 16:05:23 -0400515 int ret = 0;
Sean Paule42febf2015-05-07 11:35:29 -0700516 for (int i = 0; i < (int)num_displays; ++i) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400517 if (display_contents[i])
518 ret = hwc_set_display(ctx, i, display_contents[i]);
519 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500520
Sean Paulef8f1f92015-04-29 16:05:23 -0400521 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500522}
523
Sean Paulef8f1f92015-04-29 16:05:23 -0400524static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
525 int event, int enabled) {
526 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700527 struct hwc_drm_display *hd = &ctx->displays[display];
Sean Paulef8f1f92015-04-29 16:05:23 -0400528 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
529 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500530
Sean Paul6a55e9f2015-04-30 15:31:06 -0400531 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(display);
532 if (!crtc) {
533 ALOGD("Can't service events for display %d, no crtc", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400534 return -EINVAL;
535 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500536
Sean Paulef8f1f92015-04-29 16:05:23 -0400537 hd->enable_vsync_events = !!enabled;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500538
Sean Paulef8f1f92015-04-29 16:05:23 -0400539 if (!hd->enable_vsync_events)
540 return 0;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500541
Sean Paulef8f1f92015-04-29 16:05:23 -0400542 /*
543 * Note that it's possible that the event worker is already waiting for
544 * a vsync, and this will be a duplicate request. In that event, we'll
545 * end up firing the event handler twice, and it will discard the second
546 * event. Not ideal, but not worth introducing a bunch of additional
547 * logic/locks/state for.
548 */
Sean Paule42febf2015-05-07 11:35:29 -0700549 int ret = hwc_queue_vblank_event(hd);
Sean Paulef8f1f92015-04-29 16:05:23 -0400550 if (ret) {
551 ALOGE("Failed to queue vblank event ret=%d", ret);
552 return ret;
553 }
Sean Pauleb9e75c2015-01-25 23:31:30 -0500554
Sean Paulef8f1f92015-04-29 16:05:23 -0400555 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500556}
557
Sean Paulef8f1f92015-04-29 16:05:23 -0400558static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
559 int mode) {
560 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500561
Sean Paul6a55e9f2015-04-30 15:31:06 -0400562 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400563 switch (mode) {
564 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400565 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400566 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500567
Sean Paulef8f1f92015-04-29 16:05:23 -0400568 /* We can't support dozing right now, so go full on */
569 case HWC_POWER_MODE_DOZE:
570 case HWC_POWER_MODE_DOZE_SUSPEND:
571 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400572 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400573 break;
574 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400575 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500576}
577
Sean Paulef8f1f92015-04-29 16:05:23 -0400578static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
579 int *value) {
580 switch (what) {
581 case HWC_BACKGROUND_LAYER_SUPPORTED:
582 *value = 0; /* TODO: We should do this */
583 break;
584 case HWC_VSYNC_PERIOD:
585 ALOGW("Query for deprecated vsync value, returning 60Hz");
586 *value = 1000 * 1000 * 1000 / 60;
587 break;
588 case HWC_DISPLAY_TYPES_SUPPORTED:
589 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
590 break;
591 }
592 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500593}
594
Sean Paulef8f1f92015-04-29 16:05:23 -0400595static void hwc_register_procs(struct hwc_composer_device_1 *dev,
596 hwc_procs_t const *procs) {
597 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500598
Sean Paulef8f1f92015-04-29 16:05:23 -0400599 ctx->procs = procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500600}
601
Sean Paulef8f1f92015-04-29 16:05:23 -0400602static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
603 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400604 size_t *num_configs) {
605 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400606 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500607
Sean Paulef8f1f92015-04-29 16:05:23 -0400608 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700609 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400610 hd->config_ids.clear();
611
612 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
613 if (!connector) {
614 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400615 return -ENODEV;
616 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500617
Sean Paule42febf2015-05-07 11:35:29 -0700618 int ret = connector->UpdateModes();
Sean Paul6a55e9f2015-04-30 15:31:06 -0400619 if (ret) {
620 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400621 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400622 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500623
Sean Paul6a55e9f2015-04-30 15:31:06 -0400624 for (DrmConnector::ModeIter iter = connector->begin_modes();
625 iter != connector->end_modes(); ++iter) {
626 size_t idx = hd->config_ids.size();
627 if (idx == *num_configs)
628 break;
629 hd->config_ids.push_back(iter->id());
630 configs[idx] = iter->id();
631 }
632 *num_configs = hd->config_ids.size();
633 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500634}
635
Sean Paulef8f1f92015-04-29 16:05:23 -0400636static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
637 int display, uint32_t config,
638 const uint32_t *attributes,
639 int32_t *values) {
640 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400641 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400642 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400643 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400644 return -ENODEV;
645 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400646 DrmMode mode;
647 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
648 ++iter) {
649 if (iter->id() == config) {
650 mode = *iter;
651 break;
652 }
653 }
654 if (mode.id() == 0) {
655 ALOGE("Failed to find active mode for display %d", display);
656 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400657 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500658
Sean Paul6a55e9f2015-04-30 15:31:06 -0400659 uint32_t mm_width = c->mm_width();
660 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400661 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
662 switch (attributes[i]) {
663 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400664 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400665 break;
666 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400667 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400668 break;
669 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400670 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400671 break;
672 case HWC_DISPLAY_DPI_X:
673 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400674 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400675 break;
676 case HWC_DISPLAY_DPI_Y:
677 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400678 values[i] =
679 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400680 break;
681 }
682 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400683 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500684}
685
Sean Paulef8f1f92015-04-29 16:05:23 -0400686static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
687 int display) {
688 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400689 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
690 if (!c) {
691 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400692 return -ENODEV;
693 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500694
Sean Paul6a55e9f2015-04-30 15:31:06 -0400695 DrmMode mode = c->active_mode();
Sean Paule42febf2015-05-07 11:35:29 -0700696 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400697 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
698 if (hd->config_ids[i] == mode.id())
699 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400700 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400701 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500702}
703
Sean Paulef8f1f92015-04-29 16:05:23 -0400704static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
705 int index) {
706 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700707 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400708 if (index >= (int)hd->config_ids.size()) {
709 ALOGE("Invalid config index %d passed in", index);
710 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400711 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500712
Sean Paule42febf2015-05-07 11:35:29 -0700713 int ret =
Sean Paul6a55e9f2015-04-30 15:31:06 -0400714 ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
715 if (ret) {
716 ALOGE("Failed to set config for display %d", display);
717 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400718 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500719
Sean Paul6a55e9f2015-04-30 15:31:06 -0400720 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500721}
722
Sean Paulef8f1f92015-04-29 16:05:23 -0400723static int hwc_destroy_worker(struct hwc_worker *worker) {
724 int ret = pthread_mutex_lock(&worker->lock);
725 if (ret) {
726 ALOGE("Failed to lock in destroy() %d", ret);
727 return ret;
728 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500729
Sean Paulef8f1f92015-04-29 16:05:23 -0400730 worker->exit = true;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500731
Sean Paulef8f1f92015-04-29 16:05:23 -0400732 ret |= pthread_cond_signal(&worker->cond);
733 if (ret)
734 ALOGE("Failed to signal cond in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500735
Sean Paulef8f1f92015-04-29 16:05:23 -0400736 ret |= pthread_mutex_unlock(&worker->lock);
737 if (ret)
738 ALOGE("Failed to unlock in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500739
Sean Paulef8f1f92015-04-29 16:05:23 -0400740 ret |= pthread_join(worker->thread, NULL);
741 if (ret && ret != ESRCH)
742 ALOGE("Failed to join thread in destroy() %d", ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500743
Sean Paulef8f1f92015-04-29 16:05:23 -0400744 return ret;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500745}
746
Sean Paulef8f1f92015-04-29 16:05:23 -0400747static void hwc_destroy_display(struct hwc_drm_display *hd) {
748 if (hwc_destroy_worker(&hd->set_worker))
749 ALOGE("Destroy set worker failed");
Sean Paul9aa5ad32015-01-22 15:47:54 -0500750}
751
Sean Paulef8f1f92015-04-29 16:05:23 -0400752static int hwc_device_close(struct hw_device_t *dev) {
753 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500754
Sean Paule42febf2015-05-07 11:35:29 -0700755 for (hwc_context_t::DisplayMapIter iter = ctx->displays.begin();
756 iter != ctx->displays.end(); ++iter)
757 hwc_destroy_display(&iter->second);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500758
Sean Paulef8f1f92015-04-29 16:05:23 -0400759 if (hwc_destroy_worker(&ctx->event_worker))
760 ALOGE("Destroy event worker failed");
Sean Paul814bddb2015-03-03 17:46:19 -0500761
Sean Paulef8f1f92015-04-29 16:05:23 -0400762 delete ctx;
Sean Paulef8f1f92015-04-29 16:05:23 -0400763 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500764}
765
Sean Paul814bddb2015-03-03 17:46:19 -0500766static int hwc_initialize_worker(struct hwc_worker *worker,
Sean Paulef8f1f92015-04-29 16:05:23 -0400767 void *(*routine)(void *), void *arg) {
768 int ret = pthread_cond_init(&worker->cond, NULL);
769 if (ret) {
770 ALOGE("Failed to create worker condition %d", ret);
771 return ret;
772 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500773
Sean Paulef8f1f92015-04-29 16:05:23 -0400774 ret = pthread_mutex_init(&worker->lock, NULL);
775 if (ret) {
776 ALOGE("Failed to initialize worker lock %d", ret);
777 pthread_cond_destroy(&worker->cond);
778 return ret;
779 }
Sean Paul9aa5ad32015-01-22 15:47:54 -0500780
Sean Paulef8f1f92015-04-29 16:05:23 -0400781 worker->exit = false;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500782
Sean Paulef8f1f92015-04-29 16:05:23 -0400783 ret = pthread_create(&worker->thread, NULL, routine, arg);
784 if (ret) {
785 ALOGE("Could not create worker thread %d", ret);
786 pthread_mutex_destroy(&worker->lock);
787 pthread_cond_destroy(&worker->cond);
788 return ret;
789 }
790 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500791}
792
Sean Paul24a26e32015-02-04 10:34:47 -0800793/*
794 * TODO: This function sets the active config to the first one in the list. This
795 * should be fixed such that it selects the preferred mode for the display, or
796 * some other, saner, method of choosing the config.
797 */
Sean Paule42febf2015-05-07 11:35:29 -0700798static int hwc_set_initial_config(hwc_drm_display_t *hd) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400799 uint32_t config;
800 size_t num_configs = 1;
801 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
802 &num_configs);
803 if (ret || !num_configs)
804 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800805
Sean Paulef8f1f92015-04-29 16:05:23 -0400806 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
807 if (ret) {
808 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
809 return ret;
810 }
Sean Paul24a26e32015-02-04 10:34:47 -0800811
Sean Paulef8f1f92015-04-29 16:05:23 -0400812 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800813}
814
Sean Paul6a55e9f2015-04-30 15:31:06 -0400815static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paule42febf2015-05-07 11:35:29 -0700816 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paulef8f1f92015-04-29 16:05:23 -0400817 hd->ctx = ctx;
818 hd->display = display;
Sean Paulef8f1f92015-04-29 16:05:23 -0400819 hd->enable_vsync_events = false;
820 hd->vsync_sequence = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500821
Sean Paule42febf2015-05-07 11:35:29 -0700822 int ret = pthread_mutex_init(&hd->flip_lock, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400823 if (ret) {
824 ALOGE("Failed to initialize flip lock %d", ret);
825 return ret;
826 }
Sean Paul814bddb2015-03-03 17:46:19 -0500827
Sean Paulef8f1f92015-04-29 16:05:23 -0400828 ret = pthread_cond_init(&hd->flip_cond, NULL);
829 if (ret) {
830 ALOGE("Failed to intiialize flip condition %d", ret);
831 pthread_mutex_destroy(&hd->flip_lock);
832 return ret;
833 }
Sean Paul814bddb2015-03-03 17:46:19 -0500834
Sean Paulef8f1f92015-04-29 16:05:23 -0400835 ret = sw_sync_timeline_create();
836 if (ret < 0) {
837 ALOGE("Failed to create sw sync timeline %d", ret);
838 pthread_cond_destroy(&hd->flip_cond);
839 pthread_mutex_destroy(&hd->flip_lock);
840 return ret;
841 }
842 hd->timeline_fd = ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500843
Sean Paulef8f1f92015-04-29 16:05:23 -0400844 /*
845 * Initialize timeline_next to 1, because point 0 will be the very first
846 * set operation. Since we increment every time set() is called,
847 * initializing to 0 would cause an off-by-one error where
848 * surfaceflinger would composite on the front buffer.
849 */
850 hd->timeline_next = 1;
Sean Paule147a2a2015-02-22 17:55:43 -0500851
Sean Paulef8f1f92015-04-29 16:05:23 -0400852 ret = hwc_set_initial_config(hd);
853 if (ret) {
854 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
855 close(hd->timeline_fd);
856 pthread_cond_destroy(&hd->flip_cond);
857 pthread_mutex_destroy(&hd->flip_lock);
858 return ret;
859 }
Sean Paulf1dc1912015-01-24 01:34:31 -0500860
Sean Paulef8f1f92015-04-29 16:05:23 -0400861 ret = hwc_initialize_worker(&hd->set_worker, hwc_set_worker, hd);
862 if (ret) {
863 ALOGE("Failed to create set worker %d\n", ret);
864 close(hd->timeline_fd);
865 pthread_cond_destroy(&hd->flip_cond);
866 pthread_mutex_destroy(&hd->flip_lock);
867 return ret;
868 }
Sean Paul24a26e32015-02-04 10:34:47 -0800869
Sean Paulef8f1f92015-04-29 16:05:23 -0400870 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500871}
872
Sean Paulef8f1f92015-04-29 16:05:23 -0400873static void hwc_free_conn_list(drmModeConnectorPtr *conn_list, int num_conn) {
874 for (int i = 0; i < num_conn; ++i) {
875 if (conn_list[i])
876 drmModeFreeConnector(conn_list[i]);
877 }
878 free(conn_list);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500879}
880
Sean Paulef8f1f92015-04-29 16:05:23 -0400881static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400882 int ret;
883 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
884 c != ctx->drm.end_connectors(); ++c) {
885 ret = hwc_initialize_display(ctx, (*c)->display());
886 if (ret) {
887 ALOGE("Failed to initialize display %d", (*c)->display());
888 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400889 }
890 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400891
892 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500893}
894
Sean Paulef8f1f92015-04-29 16:05:23 -0400895static int hwc_device_open(const struct hw_module_t *module, const char *name,
896 struct hw_device_t **dev) {
897 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
898 ALOGE("Invalid module name- %s", name);
899 return -EINVAL;
900 }
901
902 struct hwc_context_t *ctx = new hwc_context_t();
903 if (!ctx) {
904 ALOGE("Failed to allocate hwc context");
905 return -ENOMEM;
906 }
907
Sean Paul6a55e9f2015-04-30 15:31:06 -0400908 int ret = ctx->drm.Init();
909 if (ret) {
910 ALOGE("Can't initialize Drm object %d", ret);
911 delete ctx;
912 return ret;
913 }
914
Sean Paulda6270d2015-06-01 14:11:52 -0400915 ctx->importer = Importer::CreateInstance(&ctx->drm);
916 if (!ctx->importer) {
917 ALOGE("Failed to create importer instance");
Sean Paulef8f1f92015-04-29 16:05:23 -0400918 delete ctx;
919 return ret;
920 }
921
Sean Paulef8f1f92015-04-29 16:05:23 -0400922 ret = hwc_enumerate_displays(ctx);
923 if (ret) {
924 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400925 delete ctx;
926 return ret;
927 }
928
929 ret = hwc_initialize_worker(&ctx->event_worker, hwc_event_worker, ctx);
930 if (ret) {
931 ALOGE("Failed to create event worker %d\n", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400932 delete ctx;
933 return ret;
934 }
935
936 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
937 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
938 ctx->device.common.module = const_cast<hw_module_t *>(module);
939 ctx->device.common.close = hwc_device_close;
940
941 ctx->device.prepare = hwc_prepare;
942 ctx->device.set = hwc_set;
943 ctx->device.eventControl = hwc_event_control;
944 ctx->device.setPowerMode = hwc_set_power_mode;
945 ctx->device.query = hwc_query;
946 ctx->device.registerProcs = hwc_register_procs;
947 ctx->device.getDisplayConfigs = hwc_get_display_configs;
948 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
949 ctx->device.getActiveConfig = hwc_get_active_config;
950 ctx->device.setActiveConfig = hwc_set_active_config;
951 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
952
953 *dev = &ctx->device.common;
954
955 return 0;
956}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400957}
Sean Paulef8f1f92015-04-29 16:05:23 -0400958
Sean Paul6a55e9f2015-04-30 15:31:06 -0400959static struct hw_module_methods_t hwc_module_methods = {
960 open : android::hwc_device_open
961};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500962
963hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -0400964 common : {
965 tag : HARDWARE_MODULE_TAG,
966 version_major : 1,
967 version_minor : 0,
968 id : HWC_HARDWARE_MODULE_ID,
969 name : "DRM hwcomposer module",
970 author : "The Android Open Source Project",
971 methods : &hwc_module_methods,
972 dso : NULL,
973 reserved : {0},
974 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500975};