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Christopher Ferris38062f92014-07-09 15:33:25 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MSM_DRM_H__
20#define __MSM_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
Christopher Ferris38062f92014-07-09 15:33:25 -070025#define MSM_PIPE_NONE 0x00
26#define MSM_PIPE_2D0 0x01
27#define MSM_PIPE_2D1 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define MSM_PIPE_3D0 0x10
Christopher Ferris6a9755d2017-01-13 14:09:31 -080029#define MSM_PIPE_ID_MASK 0xffff
30#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
31#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
Christopher Ferris38062f92014-07-09 15:33:25 -070032struct drm_msm_timespec {
Christopher Ferris05d08e92016-02-04 13:16:38 -080033 __s64 tv_sec;
34 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070035};
Christopher Ferris38062f92014-07-09 15:33:25 -070036#define MSM_PARAM_GPU_ID 0x01
37#define MSM_PARAM_GMEM_SIZE 0x02
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070038#define MSM_PARAM_CHIP_ID 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070039#define MSM_PARAM_MAX_FREQ 0x04
40#define MSM_PARAM_TIMESTAMP 0x05
Christopher Ferris525ce912017-07-26 13:12:53 -070041#define MSM_PARAM_GMEM_BASE 0x06
Christopher Ferris934ec942018-01-31 15:29:16 -080042#define MSM_PARAM_NR_RINGS 0x07
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -070043#define MSM_PARAM_PP_PGTABLE 0x08
44#define MSM_PARAM_FAULTS 0x09
Christopher Ferris106b3a82016-08-24 12:15:38 -070045struct drm_msm_param {
Christopher Ferris05d08e92016-02-04 13:16:38 -080046 __u32 pipe;
47 __u32 param;
48 __u64 value;
Christopher Ferris38062f92014-07-09 15:33:25 -070049};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070050#define MSM_BO_SCANOUT 0x00000001
Christopher Ferris38062f92014-07-09 15:33:25 -070051#define MSM_BO_GPU_READONLY 0x00000002
52#define MSM_BO_CACHE_MASK 0x000f0000
53#define MSM_BO_CACHED 0x00010000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070054#define MSM_BO_WC 0x00020000
Christopher Ferris38062f92014-07-09 15:33:25 -070055#define MSM_BO_UNCACHED 0x00040000
Tao Baod7db5942015-01-28 10:07:51 -080056#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
Christopher Ferris38062f92014-07-09 15:33:25 -070057struct drm_msm_gem_new {
Christopher Ferris05d08e92016-02-04 13:16:38 -080058 __u64 size;
59 __u32 flags;
60 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070061};
Christopher Ferrisd842e432019-03-07 10:21:59 -080062#define MSM_INFO_GET_OFFSET 0x00
63#define MSM_INFO_GET_IOVA 0x01
64#define MSM_INFO_SET_NAME 0x02
65#define MSM_INFO_GET_NAME 0x03
Christopher Ferris38062f92014-07-09 15:33:25 -070066struct drm_msm_gem_info {
Christopher Ferris05d08e92016-02-04 13:16:38 -080067 __u32 handle;
Christopher Ferrisd842e432019-03-07 10:21:59 -080068 __u32 info;
69 __u64 value;
70 __u32 len;
71 __u32 pad;
Christopher Ferris38062f92014-07-09 15:33:25 -070072};
73#define MSM_PREP_READ 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -070074#define MSM_PREP_WRITE 0x02
75#define MSM_PREP_NOSYNC 0x04
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070076#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
Christopher Ferris38062f92014-07-09 15:33:25 -070077struct drm_msm_gem_cpu_prep {
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 __u32 handle;
79 __u32 op;
Tao Baod7db5942015-01-28 10:07:51 -080080 struct drm_msm_timespec timeout;
Christopher Ferris38062f92014-07-09 15:33:25 -070081};
82struct drm_msm_gem_cpu_fini {
Christopher Ferris05d08e92016-02-04 13:16:38 -080083 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070084};
85struct drm_msm_gem_submit_reloc {
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 __u32 submit_offset;
87 __u32 or;
Christopher Ferris05d08e92016-02-04 13:16:38 -080088 __s32 shift;
89 __u32 reloc_idx;
90 __u64 reloc_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -070091};
92#define MSM_SUBMIT_CMD_BUF 0x0001
93#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
94#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
Christopher Ferris38062f92014-07-09 15:33:25 -070095struct drm_msm_gem_submit_cmd {
Christopher Ferris05d08e92016-02-04 13:16:38 -080096 __u32 type;
97 __u32 submit_idx;
98 __u32 submit_offset;
99 __u32 size;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800100 __u32 pad;
101 __u32 nr_relocs;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800102 __u64 relocs;
Christopher Ferris38062f92014-07-09 15:33:25 -0700103};
104#define MSM_SUBMIT_BO_READ 0x0001
105#define MSM_SUBMIT_BO_WRITE 0x0002
Christopher Ferrisd842e432019-03-07 10:21:59 -0800106#define MSM_SUBMIT_BO_DUMP 0x0004
107#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE | MSM_SUBMIT_BO_DUMP)
Christopher Ferris38062f92014-07-09 15:33:25 -0700108struct drm_msm_gem_submit_bo {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 __u32 flags;
110 __u32 handle;
111 __u64 presumed;
Christopher Ferris38062f92014-07-09 15:33:25 -0700112};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800113#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
114#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800115#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
Christopher Ferris76a1d452018-06-27 14:12:29 -0700116#define MSM_SUBMIT_SUDO 0x10000000
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700117#define MSM_SUBMIT_SYNCOBJ_IN 0x08000000
118#define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000
119#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | MSM_SUBMIT_SUDO | MSM_SUBMIT_SYNCOBJ_IN | MSM_SUBMIT_SYNCOBJ_OUT | 0)
120#define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001
121#define MSM_SUBMIT_SYNCOBJ_FLAGS (MSM_SUBMIT_SYNCOBJ_RESET | 0)
122struct drm_msm_gem_submit_syncobj {
123 __u32 handle;
124 __u32 flags;
125 __u64 point;
126};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800127struct drm_msm_gem_submit {
128 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800129 __u32 fence;
130 __u32 nr_bos;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131 __u32 nr_cmds;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800132 __u64 bos;
133 __u64 cmds;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800134 __s32 fence_fd;
Christopher Ferris934ec942018-01-31 15:29:16 -0800135 __u32 queueid;
Christopher Ferris8177cdf2020-08-03 11:53:55 -0700136 __u64 in_syncobjs;
137 __u64 out_syncobjs;
138 __u32 nr_in_syncobjs;
139 __u32 nr_out_syncobjs;
140 __u32 syncobj_stride;
141 __u32 pad;
Christopher Ferris38062f92014-07-09 15:33:25 -0700142};
Christopher Ferris38062f92014-07-09 15:33:25 -0700143struct drm_msm_wait_fence {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800144 __u32 fence;
145 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800146 struct drm_msm_timespec timeout;
Christopher Ferris934ec942018-01-31 15:29:16 -0800147 __u32 queueid;
Christopher Ferris38062f92014-07-09 15:33:25 -0700148};
Christopher Ferris49f525c2016-12-12 14:55:36 -0800149#define MSM_MADV_WILLNEED 0
150#define MSM_MADV_DONTNEED 1
151#define __MSM_MADV_PURGED 2
152struct drm_msm_gem_madvise {
Christopher Ferris49f525c2016-12-12 14:55:36 -0800153 __u32 handle;
154 __u32 madv;
155 __u32 retained;
156};
Christopher Ferris934ec942018-01-31 15:29:16 -0800157#define MSM_SUBMITQUEUE_FLAGS (0)
158struct drm_msm_submitqueue {
159 __u32 flags;
160 __u32 prio;
161 __u32 id;
162};
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700163#define MSM_SUBMITQUEUE_PARAM_FAULTS 0
164struct drm_msm_submitqueue_query {
165 __u64 data;
166 __u32 id;
167 __u32 param;
168 __u32 len;
169 __u32 pad;
170};
Christopher Ferris38062f92014-07-09 15:33:25 -0700171#define DRM_MSM_GET_PARAM 0x00
172#define DRM_MSM_GEM_NEW 0x02
173#define DRM_MSM_GEM_INFO 0x03
Christopher Ferris38062f92014-07-09 15:33:25 -0700174#define DRM_MSM_GEM_CPU_PREP 0x04
175#define DRM_MSM_GEM_CPU_FINI 0x05
176#define DRM_MSM_GEM_SUBMIT 0x06
177#define DRM_MSM_WAIT_FENCE 0x07
Christopher Ferris49f525c2016-12-12 14:55:36 -0800178#define DRM_MSM_GEM_MADVISE 0x08
Christopher Ferris934ec942018-01-31 15:29:16 -0800179#define DRM_MSM_SUBMITQUEUE_NEW 0x0A
180#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700181#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
Christopher Ferris38062f92014-07-09 15:33:25 -0700182#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
183#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
184#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800185#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
Tao Baod7db5942015-01-28 10:07:51 -0800186#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
Christopher Ferris38062f92014-07-09 15:33:25 -0700187#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
Tao Baod7db5942015-01-28 10:07:51 -0800188#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800189#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
Christopher Ferris934ec942018-01-31 15:29:16 -0800190#define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
191#define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700192#define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800193#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800194}
Christopher Ferris38062f92014-07-09 15:33:25 -0700195#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700196#endif