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Christopher Ferris38062f92014-07-09 15:33:25 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MSM_DRM_H__
20#define __MSM_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
Christopher Ferris38062f92014-07-09 15:33:25 -070024#define MSM_PIPE_NONE 0x00
25#define MSM_PIPE_2D0 0x01
26#define MSM_PIPE_2D1 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070027#define MSM_PIPE_3D0 0x10
Christopher Ferris6a9755d2017-01-13 14:09:31 -080028#define MSM_PIPE_ID_MASK 0xffff
29#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
30#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
Christopher Ferris38062f92014-07-09 15:33:25 -070031struct drm_msm_timespec {
Christopher Ferris05d08e92016-02-04 13:16:38 -080032 __s64 tv_sec;
33 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070034};
Christopher Ferris38062f92014-07-09 15:33:25 -070035#define MSM_PARAM_GPU_ID 0x01
36#define MSM_PARAM_GMEM_SIZE 0x02
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070037#define MSM_PARAM_CHIP_ID 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070038#define MSM_PARAM_MAX_FREQ 0x04
39#define MSM_PARAM_TIMESTAMP 0x05
Christopher Ferris525ce912017-07-26 13:12:53 -070040#define MSM_PARAM_GMEM_BASE 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -070041struct drm_msm_param {
Christopher Ferris05d08e92016-02-04 13:16:38 -080042 __u32 pipe;
43 __u32 param;
44 __u64 value;
Christopher Ferris38062f92014-07-09 15:33:25 -070045};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070046#define MSM_BO_SCANOUT 0x00000001
Christopher Ferris38062f92014-07-09 15:33:25 -070047#define MSM_BO_GPU_READONLY 0x00000002
48#define MSM_BO_CACHE_MASK 0x000f0000
49#define MSM_BO_CACHED 0x00010000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070050#define MSM_BO_WC 0x00020000
Christopher Ferris38062f92014-07-09 15:33:25 -070051#define MSM_BO_UNCACHED 0x00040000
Tao Baod7db5942015-01-28 10:07:51 -080052#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
Christopher Ferris38062f92014-07-09 15:33:25 -070053struct drm_msm_gem_new {
Christopher Ferris05d08e92016-02-04 13:16:38 -080054 __u64 size;
55 __u32 flags;
56 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070057};
58struct drm_msm_gem_info {
Christopher Ferris05d08e92016-02-04 13:16:38 -080059 __u32 handle;
60 __u32 pad;
61 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -070062};
63#define MSM_PREP_READ 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -070064#define MSM_PREP_WRITE 0x02
65#define MSM_PREP_NOSYNC 0x04
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070066#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
Christopher Ferris38062f92014-07-09 15:33:25 -070067struct drm_msm_gem_cpu_prep {
Christopher Ferris05d08e92016-02-04 13:16:38 -080068 __u32 handle;
69 __u32 op;
Tao Baod7db5942015-01-28 10:07:51 -080070 struct drm_msm_timespec timeout;
Christopher Ferris38062f92014-07-09 15:33:25 -070071};
72struct drm_msm_gem_cpu_fini {
Christopher Ferris05d08e92016-02-04 13:16:38 -080073 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070074};
75struct drm_msm_gem_submit_reloc {
Christopher Ferris05d08e92016-02-04 13:16:38 -080076 __u32 submit_offset;
77 __u32 or;
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 __s32 shift;
79 __u32 reloc_idx;
80 __u64 reloc_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -070081};
82#define MSM_SUBMIT_CMD_BUF 0x0001
83#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
84#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
Christopher Ferris38062f92014-07-09 15:33:25 -070085struct drm_msm_gem_submit_cmd {
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 __u32 type;
87 __u32 submit_idx;
88 __u32 submit_offset;
89 __u32 size;
Christopher Ferris05d08e92016-02-04 13:16:38 -080090 __u32 pad;
91 __u32 nr_relocs;
92 __u64 __user relocs;
Christopher Ferris38062f92014-07-09 15:33:25 -070093};
94#define MSM_SUBMIT_BO_READ 0x0001
95#define MSM_SUBMIT_BO_WRITE 0x0002
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070096#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
Christopher Ferris38062f92014-07-09 15:33:25 -070097struct drm_msm_gem_submit_bo {
Christopher Ferris05d08e92016-02-04 13:16:38 -080098 __u32 flags;
99 __u32 handle;
100 __u64 presumed;
Christopher Ferris38062f92014-07-09 15:33:25 -0700101};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800102#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
103#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800104#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
105#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0)
106struct drm_msm_gem_submit {
107 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800108 __u32 fence;
109 __u32 nr_bos;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 __u32 nr_cmds;
111 __u64 __user bos;
112 __u64 __user cmds;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800113 __s32 fence_fd;
Christopher Ferris38062f92014-07-09 15:33:25 -0700114};
Christopher Ferris38062f92014-07-09 15:33:25 -0700115struct drm_msm_wait_fence {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800116 __u32 fence;
117 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800118 struct drm_msm_timespec timeout;
Christopher Ferris38062f92014-07-09 15:33:25 -0700119};
Christopher Ferris49f525c2016-12-12 14:55:36 -0800120#define MSM_MADV_WILLNEED 0
121#define MSM_MADV_DONTNEED 1
122#define __MSM_MADV_PURGED 2
123struct drm_msm_gem_madvise {
Christopher Ferris49f525c2016-12-12 14:55:36 -0800124 __u32 handle;
125 __u32 madv;
126 __u32 retained;
127};
Christopher Ferris38062f92014-07-09 15:33:25 -0700128#define DRM_MSM_GET_PARAM 0x00
129#define DRM_MSM_GEM_NEW 0x02
130#define DRM_MSM_GEM_INFO 0x03
Christopher Ferris38062f92014-07-09 15:33:25 -0700131#define DRM_MSM_GEM_CPU_PREP 0x04
132#define DRM_MSM_GEM_CPU_FINI 0x05
133#define DRM_MSM_GEM_SUBMIT 0x06
134#define DRM_MSM_WAIT_FENCE 0x07
Christopher Ferris49f525c2016-12-12 14:55:36 -0800135#define DRM_MSM_GEM_MADVISE 0x08
Christopher Ferris49f525c2016-12-12 14:55:36 -0800136#define DRM_MSM_NUM_IOCTLS 0x09
Christopher Ferris38062f92014-07-09 15:33:25 -0700137#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
138#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
139#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800140#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
Tao Baod7db5942015-01-28 10:07:51 -0800141#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
Christopher Ferris38062f92014-07-09 15:33:25 -0700142#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
Tao Baod7db5942015-01-28 10:07:51 -0800143#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800144#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
145#ifdef __cplusplus
Christopher Ferris38062f92014-07-09 15:33:25 -0700146#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147#endif