blob: 4f1a423e4354be2008ab71f249fe51304e9345d7 [file] [log] [blame]
Christopher Ferris38062f92014-07-09 15:33:25 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __MSM_DRM_H__
20#define __MSM_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
Christopher Ferris38062f92014-07-09 15:33:25 -070024#define MSM_PIPE_NONE 0x00
25#define MSM_PIPE_2D0 0x01
26#define MSM_PIPE_2D1 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070027#define MSM_PIPE_3D0 0x10
Christopher Ferris6a9755d2017-01-13 14:09:31 -080028#define MSM_PIPE_ID_MASK 0xffff
29#define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
30#define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
Christopher Ferris38062f92014-07-09 15:33:25 -070031struct drm_msm_timespec {
Christopher Ferris05d08e92016-02-04 13:16:38 -080032 __s64 tv_sec;
33 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070034};
Christopher Ferris38062f92014-07-09 15:33:25 -070035#define MSM_PARAM_GPU_ID 0x01
36#define MSM_PARAM_GMEM_SIZE 0x02
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070037#define MSM_PARAM_CHIP_ID 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070038#define MSM_PARAM_MAX_FREQ 0x04
39#define MSM_PARAM_TIMESTAMP 0x05
Christopher Ferris525ce912017-07-26 13:12:53 -070040#define MSM_PARAM_GMEM_BASE 0x06
Christopher Ferris106b3a82016-08-24 12:15:38 -070041struct drm_msm_param {
Christopher Ferris05d08e92016-02-04 13:16:38 -080042 __u32 pipe;
43 __u32 param;
44 __u64 value;
Christopher Ferris38062f92014-07-09 15:33:25 -070045};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070046#define MSM_BO_SCANOUT 0x00000001
Christopher Ferris38062f92014-07-09 15:33:25 -070047#define MSM_BO_GPU_READONLY 0x00000002
48#define MSM_BO_CACHE_MASK 0x000f0000
49#define MSM_BO_CACHED 0x00010000
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070050#define MSM_BO_WC 0x00020000
Christopher Ferris38062f92014-07-09 15:33:25 -070051#define MSM_BO_UNCACHED 0x00040000
Tao Baod7db5942015-01-28 10:07:51 -080052#define MSM_BO_FLAGS (MSM_BO_SCANOUT | MSM_BO_GPU_READONLY | MSM_BO_CACHED | MSM_BO_WC | MSM_BO_UNCACHED)
Christopher Ferris38062f92014-07-09 15:33:25 -070053struct drm_msm_gem_new {
Christopher Ferris05d08e92016-02-04 13:16:38 -080054 __u64 size;
55 __u32 flags;
56 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070057};
Christopher Ferris1308ad32017-11-14 17:32:13 -080058#define MSM_INFO_IOVA 0x01
59#define MSM_INFO_FLAGS (MSM_INFO_IOVA)
Christopher Ferris38062f92014-07-09 15:33:25 -070060struct drm_msm_gem_info {
Christopher Ferris05d08e92016-02-04 13:16:38 -080061 __u32 handle;
Christopher Ferris1308ad32017-11-14 17:32:13 -080062 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -080063 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -070064};
65#define MSM_PREP_READ 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -070066#define MSM_PREP_WRITE 0x02
67#define MSM_PREP_NOSYNC 0x04
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070068#define MSM_PREP_FLAGS (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
Christopher Ferris38062f92014-07-09 15:33:25 -070069struct drm_msm_gem_cpu_prep {
Christopher Ferris05d08e92016-02-04 13:16:38 -080070 __u32 handle;
71 __u32 op;
Tao Baod7db5942015-01-28 10:07:51 -080072 struct drm_msm_timespec timeout;
Christopher Ferris38062f92014-07-09 15:33:25 -070073};
74struct drm_msm_gem_cpu_fini {
Christopher Ferris05d08e92016-02-04 13:16:38 -080075 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -070076};
77struct drm_msm_gem_submit_reloc {
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 __u32 submit_offset;
79 __u32 or;
Christopher Ferris05d08e92016-02-04 13:16:38 -080080 __s32 shift;
81 __u32 reloc_idx;
82 __u64 reloc_offset;
Christopher Ferris38062f92014-07-09 15:33:25 -070083};
84#define MSM_SUBMIT_CMD_BUF 0x0001
85#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
86#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
Christopher Ferris38062f92014-07-09 15:33:25 -070087struct drm_msm_gem_submit_cmd {
Christopher Ferris05d08e92016-02-04 13:16:38 -080088 __u32 type;
89 __u32 submit_idx;
90 __u32 submit_offset;
91 __u32 size;
Christopher Ferris05d08e92016-02-04 13:16:38 -080092 __u32 pad;
93 __u32 nr_relocs;
Christopher Ferris1308ad32017-11-14 17:32:13 -080094 __u64 relocs;
Christopher Ferris38062f92014-07-09 15:33:25 -070095};
96#define MSM_SUBMIT_BO_READ 0x0001
97#define MSM_SUBMIT_BO_WRITE 0x0002
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070098#define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | MSM_SUBMIT_BO_WRITE)
Christopher Ferris38062f92014-07-09 15:33:25 -070099struct drm_msm_gem_submit_bo {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800100 __u32 flags;
101 __u32 handle;
102 __u64 presumed;
Christopher Ferris38062f92014-07-09 15:33:25 -0700103};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800104#define MSM_SUBMIT_NO_IMPLICIT 0x80000000
105#define MSM_SUBMIT_FENCE_FD_IN 0x40000000
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800106#define MSM_SUBMIT_FENCE_FD_OUT 0x20000000
107#define MSM_SUBMIT_FLAGS (MSM_SUBMIT_NO_IMPLICIT | MSM_SUBMIT_FENCE_FD_IN | MSM_SUBMIT_FENCE_FD_OUT | 0)
108struct drm_msm_gem_submit {
109 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 __u32 fence;
111 __u32 nr_bos;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800112 __u32 nr_cmds;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800113 __u64 bos;
114 __u64 cmds;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800115 __s32 fence_fd;
Christopher Ferris38062f92014-07-09 15:33:25 -0700116};
Christopher Ferris38062f92014-07-09 15:33:25 -0700117struct drm_msm_wait_fence {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118 __u32 fence;
119 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800120 struct drm_msm_timespec timeout;
Christopher Ferris38062f92014-07-09 15:33:25 -0700121};
Christopher Ferris49f525c2016-12-12 14:55:36 -0800122#define MSM_MADV_WILLNEED 0
123#define MSM_MADV_DONTNEED 1
124#define __MSM_MADV_PURGED 2
125struct drm_msm_gem_madvise {
Christopher Ferris49f525c2016-12-12 14:55:36 -0800126 __u32 handle;
127 __u32 madv;
128 __u32 retained;
129};
Christopher Ferris38062f92014-07-09 15:33:25 -0700130#define DRM_MSM_GET_PARAM 0x00
131#define DRM_MSM_GEM_NEW 0x02
132#define DRM_MSM_GEM_INFO 0x03
Christopher Ferris38062f92014-07-09 15:33:25 -0700133#define DRM_MSM_GEM_CPU_PREP 0x04
134#define DRM_MSM_GEM_CPU_FINI 0x05
135#define DRM_MSM_GEM_SUBMIT 0x06
136#define DRM_MSM_WAIT_FENCE 0x07
Christopher Ferris49f525c2016-12-12 14:55:36 -0800137#define DRM_MSM_GEM_MADVISE 0x08
Christopher Ferris38062f92014-07-09 15:33:25 -0700138#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
139#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
140#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800141#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
Tao Baod7db5942015-01-28 10:07:51 -0800142#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
Christopher Ferris38062f92014-07-09 15:33:25 -0700143#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
Tao Baod7db5942015-01-28 10:07:51 -0800144#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
Christopher Ferris49f525c2016-12-12 14:55:36 -0800145#define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
146#ifdef __cplusplus
Christopher Ferris38062f92014-07-09 15:33:25 -0700147#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700148#endif