blob: 01897af4145ae531b60b756bb1b53e7db44e8f76 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef __NOUVEAU_DRM_H__
8#define __NOUVEAU_DRM_H__
Christopher Ferris82d75042015-01-26 10:57:07 -08009#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070010#include "drm.h"
Christopher Ferris106b3a82016-08-24 12:15:38 -070011#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080012extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070013#endif
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070014#define NOUVEAU_GETPARAM_PCI_VENDOR 3
15#define NOUVEAU_GETPARAM_PCI_DEVICE 4
16#define NOUVEAU_GETPARAM_BUS_TYPE 5
17#define NOUVEAU_GETPARAM_FB_SIZE 8
18#define NOUVEAU_GETPARAM_AGP_SIZE 9
19#define NOUVEAU_GETPARAM_CHIPSET_ID 11
20#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
21#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
22#define NOUVEAU_GETPARAM_PTIMER_TIME 14
23#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
24#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
25#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
Christopher Ferrisb830ddf2024-03-28 11:48:08 -070026#define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
27#define NOUVEAU_GETPARAM_VRAM_USED 19
Christopher Ferris7ac54f52024-08-07 21:07:12 +000028#define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070029struct drm_nouveau_getparam {
30 __u64 param;
31 __u64 value;
32};
Christopher Ferris7ac54f52024-08-07 21:07:12 +000033#define NOUVEAU_FIFO_ENGINE_GR 0x01
34#define NOUVEAU_FIFO_ENGINE_VP 0x02
35#define NOUVEAU_FIFO_ENGINE_PPP 0x04
36#define NOUVEAU_FIFO_ENGINE_BSP 0x08
37#define NOUVEAU_FIFO_ENGINE_CE 0x30
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070038struct drm_nouveau_channel_alloc {
39 __u32 fb_ctxdma_handle;
40 __u32 tt_ctxdma_handle;
41 __s32 channel;
42 __u32 pushbuf_domains;
43 __u32 notifier_handle;
44 struct {
45 __u32 handle;
46 __u32 grclass;
47 } subchan[8];
48 __u32 nr_subchan;
49};
50struct drm_nouveau_channel_free {
51 __s32 channel;
52};
Christopher Ferris7ac54f52024-08-07 21:07:12 +000053struct drm_nouveau_notifierobj_alloc {
54 __u32 channel;
55 __u32 handle;
56 __u32 size;
57 __u32 offset;
58};
59struct drm_nouveau_gpuobj_free {
60 __s32 channel;
61 __u32 handle;
62};
Christopher Ferris106b3a82016-08-24 12:15:38 -070063#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -080064#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070065#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
66#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
Christopher Ferris05d08e92016-02-04 13:16:38 -080067#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070068#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
Ben Cheng655a7c02013-10-16 16:09:24 -070069#define NOUVEAU_GEM_TILE_COMP 0x00030000
70#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define NOUVEAU_GEM_TILE_16BPP 0x00000001
72#define NOUVEAU_GEM_TILE_32BPP 0x00000002
73#define NOUVEAU_GEM_TILE_ZETA 0x00000004
74#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070075struct drm_nouveau_gem_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070076 __u32 handle;
77 __u32 domain;
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u64 size;
79 __u64 offset;
80 __u64 map_handle;
81 __u32 tile_mode;
Christopher Ferris106b3a82016-08-24 12:15:38 -070082 __u32 tile_flags;
Ben Cheng655a7c02013-10-16 16:09:24 -070083};
84struct drm_nouveau_gem_new {
Tao Baod7db5942015-01-28 10:07:51 -080085 struct drm_nouveau_gem_info info;
Christopher Ferris106b3a82016-08-24 12:15:38 -070086 __u32 channel_hint;
87 __u32 align;
Ben Cheng655a7c02013-10-16 16:09:24 -070088};
89#define NOUVEAU_GEM_MAX_BUFFERS 1024
Christopher Ferris106b3a82016-08-24 12:15:38 -070090struct drm_nouveau_gem_pushbuf_bo_presumed {
91 __u32 valid;
92 __u32 domain;
93 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070094};
Ben Cheng655a7c02013-10-16 16:09:24 -070095struct drm_nouveau_gem_pushbuf_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -070096 __u64 user_priv;
97 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070098 __u32 read_domains;
99 __u32 write_domains;
100 __u32 valid_domains;
Tao Baod7db5942015-01-28 10:07:51 -0800101 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
Ben Cheng655a7c02013-10-16 16:09:24 -0700103#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
104#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
105#define NOUVEAU_GEM_RELOC_OR (1 << 2)
106#define NOUVEAU_GEM_MAX_RELOCS 1024
Ben Cheng655a7c02013-10-16 16:09:24 -0700107struct drm_nouveau_gem_pushbuf_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700108 __u32 reloc_bo_index;
109 __u32 reloc_bo_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700110 __u32 bo_index;
111 __u32 flags;
112 __u32 data;
113 __u32 vor;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700114 __u32 tor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700115};
116#define NOUVEAU_GEM_MAX_PUSH 512
117struct drm_nouveau_gem_pushbuf_push {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118 __u32 bo_index;
119 __u32 pad;
120 __u64 offset;
121 __u64 length;
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700122#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
Ben Cheng655a7c02013-10-16 16:09:24 -0700123};
Ben Cheng655a7c02013-10-16 16:09:24 -0700124struct drm_nouveau_gem_pushbuf {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700125 __u32 channel;
126 __u32 nr_buffers;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127 __u64 buffers;
128 __u32 nr_relocs;
129 __u32 nr_push;
130 __u64 relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700131 __u64 push;
132 __u32 suffix0;
133 __u32 suffix1;
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700134#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700135 __u64 vram_available;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700136 __u64 gart_available;
Ben Cheng655a7c02013-10-16 16:09:24 -0700137};
138#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
139#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
140struct drm_nouveau_gem_cpu_prep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700141 __u32 handle;
142 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700143};
144struct drm_nouveau_gem_cpu_fini {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700145 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700146};
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700147struct drm_nouveau_sync {
148 __u32 flags;
149#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
150#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
151#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
152 __u32 handle;
153 __u64 timeline_value;
154};
155struct drm_nouveau_vm_init {
156 __u64 kernel_managed_addr;
157 __u64 kernel_managed_size;
158};
159struct drm_nouveau_vm_bind_op {
160 __u32 op;
161#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
162#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
163 __u32 flags;
164#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
165 __u32 handle;
166 __u32 pad;
167 __u64 addr;
168 __u64 bo_offset;
169 __u64 range;
170};
171struct drm_nouveau_vm_bind {
172 __u32 op_count;
173 __u32 flags;
174#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
175 __u32 wait_count;
176 __u32 sig_count;
177 __u64 wait_ptr;
178 __u64 sig_ptr;
179 __u64 op_ptr;
180};
181struct drm_nouveau_exec_push {
182 __u64 va;
183 __u32 va_len;
184 __u32 flags;
185#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
186};
187struct drm_nouveau_exec {
188 __u32 channel;
189 __u32 push_count;
190 __u32 wait_count;
191 __u32 sig_count;
192 __u64 wait_ptr;
193 __u64 sig_ptr;
194 __u64 push_ptr;
195};
Ben Cheng655a7c02013-10-16 16:09:24 -0700196#define DRM_NOUVEAU_GETPARAM 0x00
197#define DRM_NOUVEAU_SETPARAM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700198#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
199#define DRM_NOUVEAU_CHANNEL_FREE 0x03
200#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
201#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800203#define DRM_NOUVEAU_NVIF 0x07
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700204#define DRM_NOUVEAU_SVM_INIT 0x08
205#define DRM_NOUVEAU_SVM_BIND 0x09
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700206#define DRM_NOUVEAU_VM_INIT 0x10
207#define DRM_NOUVEAU_VM_BIND 0x11
208#define DRM_NOUVEAU_EXEC 0x12
Ben Cheng655a7c02013-10-16 16:09:24 -0700209#define DRM_NOUVEAU_GEM_NEW 0x40
210#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
Christopher Ferris82d75042015-01-26 10:57:07 -0800211#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
Ben Cheng655a7c02013-10-16 16:09:24 -0700212#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
213#define DRM_NOUVEAU_GEM_INFO 0x44
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700214struct drm_nouveau_svm_init {
215 __u64 unmanaged_addr;
216 __u64 unmanaged_size;
217};
218struct drm_nouveau_svm_bind {
219 __u64 header;
220 __u64 va_start;
221 __u64 va_end;
222 __u64 npages;
223 __u64 stride;
224 __u64 result;
225 __u64 reserved0;
226 __u64 reserved1;
227};
228#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
229#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
230#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
231#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
232#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
233#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
234#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
235#define NOUVEAU_SVM_BIND_TARGET_BITS 32
236#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
237#define NOUVEAU_SVM_BIND_VALID_BITS 48
238#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
239#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
240#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700241#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
242#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
243#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700244#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
245#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
Ben Cheng655a7c02013-10-16 16:09:24 -0700246#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
Christopher Ferris82d75042015-01-26 10:57:07 -0800247#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
Tao Baod7db5942015-01-28 10:07:51 -0800248#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
249#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
Ben Cheng655a7c02013-10-16 16:09:24 -0700250#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700251#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
252#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
253#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700254#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800255}
Christopher Ferris82d75042015-01-26 10:57:07 -0800256#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700257#endif