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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / drm / nouveau_drm.h
blob: 38ee5892cb5e0b80cf3497000e24787dee57d2b7 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __NOUVEAU_DRM_H__
20#define __NOUVEAU_DRM_H__
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]21#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]22#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]24#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
26#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]27#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define NOUVEAU_GEM_TILE_COMP 0x00030000
30#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]31#define NOUVEAU_GEM_TILE_16BPP 0x00000001
32#define NOUVEAU_GEM_TILE_32BPP 0x00000002
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define NOUVEAU_GEM_TILE_ZETA 0x00000004
35#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]36struct drm_nouveau_gem_info {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]37 uint32_t handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]39 uint32_t domain;
40 uint64_t size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]41 uint64_t offset;
42 uint64_t map_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]44 uint32_t tile_mode;
45 uint32_t tile_flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46};
47struct drm_nouveau_gem_new {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]49 struct drm_nouveau_gem_info info;
50 uint32_t channel_hint;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]51 uint32_t align;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]52};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define NOUVEAU_GEM_MAX_BUFFERS 1024
55struct drm_nouveau_gem_pushbuf_bo_presumed {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]56 uint32_t valid;
57 uint32_t domain;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]59 uint64_t offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]61struct drm_nouveau_gem_pushbuf_bo {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]62 uint64_t user_priv;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]64 uint32_t handle;
65 uint32_t read_domains;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]66 uint32_t write_domains;
67 uint32_t valid_domains;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]69 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]71#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
72#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define NOUVEAU_GEM_RELOC_OR (1 << 2)
75#define NOUVEAU_GEM_MAX_RELOCS 1024
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76struct drm_nouveau_gem_pushbuf_reloc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]77 uint32_t reloc_bo_index;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 uint32_t reloc_bo_offset;
80 uint32_t bo_index;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]81 uint32_t flags;
82 uint32_t data;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]84 uint32_t vor;
85 uint32_t tor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]86};
87#define NOUVEAU_GEM_MAX_PUSH 512
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89struct drm_nouveau_gem_pushbuf_push {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]90 uint32_t bo_index;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]91 uint32_t pad;
92 uint64_t offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]94 uint64_t length;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]96struct drm_nouveau_gem_pushbuf {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 uint32_t channel;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]99 uint32_t nr_buffers;
100 uint64_t buffers;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]101 uint32_t nr_relocs;
102 uint32_t nr_push;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]104 uint64_t relocs;
105 uint64_t push;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]106 uint32_t suffix0;
107 uint32_t suffix1;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]109 uint64_t vram_available;
110 uint64_t gart_available;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]111};
112#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]114#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
115struct drm_nouveau_gem_cpu_prep {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]116 uint32_t handle;
117 uint32_t flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119};
120struct drm_nouveau_gem_cpu_fini {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]121 uint32_t handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124#define DRM_NOUVEAU_GETPARAM 0x00
125#define DRM_NOUVEAU_SETPARAM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
127#define DRM_NOUVEAU_CHANNEL_FREE 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
130#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]131#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]132#define DRM_NOUVEAU_NVIF 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define DRM_NOUVEAU_GEM_NEW 0x40
135#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]136#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define DRM_NOUVEAU_GEM_INFO 0x44
140#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]141#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]142#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]146#endif