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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / nouveau_drm.h
blob: 06cc6c10c708055cff04e6d96fbe24d7dde1a606 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __NOUVEAU_DRM_H__
20#define __NOUVEAU_DRM_H__
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]21#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]22#include "drm.h"
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#ifdef __cplusplus
25#endif
26#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]27#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
30#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]31#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32#define NOUVEAU_GEM_TILE_COMP 0x00030000
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define NOUVEAU_GEM_TILE_16BPP 0x00000001
36#define NOUVEAU_GEM_TILE_32BPP 0x00000002
37#define NOUVEAU_GEM_TILE_ZETA 0x00000004
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40struct drm_nouveau_gem_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]41 __u32 handle;
42 __u32 domain;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]44 __u64 size;
45 __u64 offset;
46 __u64 map_handle;
47 __u32 tile_mode;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]49 __u32 tile_flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50};
51struct drm_nouveau_gem_new {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52 struct drm_nouveau_gem_info info;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
54 __u32 channel_hint;
55 __u32 align;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]56};
57#define NOUVEAU_GEM_MAX_BUFFERS 1024
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]59struct drm_nouveau_gem_pushbuf_bo_presumed {
60 __u32 valid;
61 __u32 domain;
62 __u64 offset;
63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65struct drm_nouveau_gem_pushbuf_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]66 __u64 user_priv;
67 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]69 __u32 read_domains;
70 __u32 write_domains;
71 __u32 valid_domains;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]72 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
76#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
77#define NOUVEAU_GEM_RELOC_OR (1 << 2)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79#define NOUVEAU_GEM_MAX_RELOCS 1024
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80struct drm_nouveau_gem_pushbuf_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]81 __u32 reloc_bo_index;
82 __u32 reloc_bo_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]84 __u32 bo_index;
85 __u32 flags;
86 __u32 data;
87 __u32 vor;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]89 __u32 tor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90};
91#define NOUVEAU_GEM_MAX_PUSH 512
92struct drm_nouveau_gem_pushbuf_push {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]94 __u32 bo_index;
95 __u32 pad;
96 __u64 offset;
97 __u64 length;
98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100struct drm_nouveau_gem_pushbuf {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]101 __u32 channel;
102 __u32 nr_buffers;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]104 __u64 buffers;
105 __u32 nr_relocs;
106 __u32 nr_push;
107 __u64 relocs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]109 __u64 push;
110 __u32 suffix0;
111 __u32 suffix1;
112 __u64 vram_available;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]114 __u64 gart_available;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115};
116#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
117#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]119struct drm_nouveau_gem_cpu_prep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]120 __u32 handle;
121 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]122};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]124struct drm_nouveau_gem_cpu_fini {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]125 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]126};
127#define DRM_NOUVEAU_GETPARAM 0x00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]129#define DRM_NOUVEAU_SETPARAM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
131#define DRM_NOUVEAU_CHANNEL_FREE 0x03
132#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]135#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]136#define DRM_NOUVEAU_NVIF 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]137#define DRM_NOUVEAU_GEM_NEW 0x40
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]140#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]141#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
142#define DRM_NOUVEAU_GEM_INFO 0x44
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]144#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]145#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]146#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
147#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]150#ifdef __cplusplus
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]151#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]152#endif
153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */