blob: 221ff2132ae220b19b848a13babb29c8d7c6f790 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef __NOUVEAU_DRM_H__
8#define __NOUVEAU_DRM_H__
Christopher Ferris82d75042015-01-26 10:57:07 -08009#define DRM_NOUVEAU_EVENT_NVIF 0x80000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070010#include "drm.h"
Christopher Ferris106b3a82016-08-24 12:15:38 -070011#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080012extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070013#endif
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070014#define NOUVEAU_GETPARAM_PCI_VENDOR 3
15#define NOUVEAU_GETPARAM_PCI_DEVICE 4
16#define NOUVEAU_GETPARAM_BUS_TYPE 5
17#define NOUVEAU_GETPARAM_FB_SIZE 8
18#define NOUVEAU_GETPARAM_AGP_SIZE 9
19#define NOUVEAU_GETPARAM_CHIPSET_ID 11
20#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
21#define NOUVEAU_GETPARAM_GRAPH_UNITS 13
22#define NOUVEAU_GETPARAM_PTIMER_TIME 14
23#define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
24#define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
25#define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
26struct drm_nouveau_getparam {
27 __u64 param;
28 __u64 value;
29};
30struct drm_nouveau_channel_alloc {
31 __u32 fb_ctxdma_handle;
32 __u32 tt_ctxdma_handle;
33 __s32 channel;
34 __u32 pushbuf_domains;
35 __u32 notifier_handle;
36 struct {
37 __u32 handle;
38 __u32 grclass;
39 } subchan[8];
40 __u32 nr_subchan;
41};
42struct drm_nouveau_channel_free {
43 __s32 channel;
44};
Christopher Ferris106b3a82016-08-24 12:15:38 -070045#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -080046#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
48#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
Christopher Ferris05d08e92016-02-04 13:16:38 -080049#define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070050#define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define NOUVEAU_GEM_TILE_COMP 0x00030000
52#define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define NOUVEAU_GEM_TILE_16BPP 0x00000001
54#define NOUVEAU_GEM_TILE_32BPP 0x00000002
55#define NOUVEAU_GEM_TILE_ZETA 0x00000004
56#define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070057struct drm_nouveau_gem_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070058 __u32 handle;
59 __u32 domain;
Christopher Ferris106b3a82016-08-24 12:15:38 -070060 __u64 size;
61 __u64 offset;
62 __u64 map_handle;
63 __u32 tile_mode;
Christopher Ferris106b3a82016-08-24 12:15:38 -070064 __u32 tile_flags;
Ben Cheng655a7c02013-10-16 16:09:24 -070065};
66struct drm_nouveau_gem_new {
Tao Baod7db5942015-01-28 10:07:51 -080067 struct drm_nouveau_gem_info info;
Christopher Ferris106b3a82016-08-24 12:15:38 -070068 __u32 channel_hint;
69 __u32 align;
Ben Cheng655a7c02013-10-16 16:09:24 -070070};
71#define NOUVEAU_GEM_MAX_BUFFERS 1024
Christopher Ferris106b3a82016-08-24 12:15:38 -070072struct drm_nouveau_gem_pushbuf_bo_presumed {
73 __u32 valid;
74 __u32 domain;
75 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070076};
Ben Cheng655a7c02013-10-16 16:09:24 -070077struct drm_nouveau_gem_pushbuf_bo {
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u64 user_priv;
79 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070080 __u32 read_domains;
81 __u32 write_domains;
82 __u32 valid_domains;
Tao Baod7db5942015-01-28 10:07:51 -080083 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
Ben Cheng655a7c02013-10-16 16:09:24 -070084};
Ben Cheng655a7c02013-10-16 16:09:24 -070085#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
86#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
87#define NOUVEAU_GEM_RELOC_OR (1 << 2)
88#define NOUVEAU_GEM_MAX_RELOCS 1024
Ben Cheng655a7c02013-10-16 16:09:24 -070089struct drm_nouveau_gem_pushbuf_reloc {
Christopher Ferris106b3a82016-08-24 12:15:38 -070090 __u32 reloc_bo_index;
91 __u32 reloc_bo_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070092 __u32 bo_index;
93 __u32 flags;
94 __u32 data;
95 __u32 vor;
Christopher Ferris106b3a82016-08-24 12:15:38 -070096 __u32 tor;
Ben Cheng655a7c02013-10-16 16:09:24 -070097};
98#define NOUVEAU_GEM_MAX_PUSH 512
99struct drm_nouveau_gem_pushbuf_push {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 __u32 bo_index;
101 __u32 pad;
102 __u64 offset;
103 __u64 length;
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700104#define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
Ben Cheng655a7c02013-10-16 16:09:24 -0700105};
Ben Cheng655a7c02013-10-16 16:09:24 -0700106struct drm_nouveau_gem_pushbuf {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700107 __u32 channel;
108 __u32 nr_buffers;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700109 __u64 buffers;
110 __u32 nr_relocs;
111 __u32 nr_push;
112 __u64 relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700113 __u64 push;
114 __u32 suffix0;
115 __u32 suffix1;
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700116#define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700117 __u64 vram_available;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118 __u64 gart_available;
Ben Cheng655a7c02013-10-16 16:09:24 -0700119};
120#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
121#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
122struct drm_nouveau_gem_cpu_prep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123 __u32 handle;
124 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700125};
126struct drm_nouveau_gem_cpu_fini {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700128};
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700129struct drm_nouveau_sync {
130 __u32 flags;
131#define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
132#define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
133#define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
134 __u32 handle;
135 __u64 timeline_value;
136};
137struct drm_nouveau_vm_init {
138 __u64 kernel_managed_addr;
139 __u64 kernel_managed_size;
140};
141struct drm_nouveau_vm_bind_op {
142 __u32 op;
143#define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
144#define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
145 __u32 flags;
146#define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
147 __u32 handle;
148 __u32 pad;
149 __u64 addr;
150 __u64 bo_offset;
151 __u64 range;
152};
153struct drm_nouveau_vm_bind {
154 __u32 op_count;
155 __u32 flags;
156#define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
157 __u32 wait_count;
158 __u32 sig_count;
159 __u64 wait_ptr;
160 __u64 sig_ptr;
161 __u64 op_ptr;
162};
163struct drm_nouveau_exec_push {
164 __u64 va;
165 __u32 va_len;
166 __u32 flags;
167#define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
168};
169struct drm_nouveau_exec {
170 __u32 channel;
171 __u32 push_count;
172 __u32 wait_count;
173 __u32 sig_count;
174 __u64 wait_ptr;
175 __u64 sig_ptr;
176 __u64 push_ptr;
177};
Ben Cheng655a7c02013-10-16 16:09:24 -0700178#define DRM_NOUVEAU_GETPARAM 0x00
179#define DRM_NOUVEAU_SETPARAM 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700180#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
181#define DRM_NOUVEAU_CHANNEL_FREE 0x03
182#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
183#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700184#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
Christopher Ferris82d75042015-01-26 10:57:07 -0800185#define DRM_NOUVEAU_NVIF 0x07
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700186#define DRM_NOUVEAU_SVM_INIT 0x08
187#define DRM_NOUVEAU_SVM_BIND 0x09
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700188#define DRM_NOUVEAU_VM_INIT 0x10
189#define DRM_NOUVEAU_VM_BIND 0x11
190#define DRM_NOUVEAU_EXEC 0x12
Ben Cheng655a7c02013-10-16 16:09:24 -0700191#define DRM_NOUVEAU_GEM_NEW 0x40
192#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
Christopher Ferris82d75042015-01-26 10:57:07 -0800193#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
Ben Cheng655a7c02013-10-16 16:09:24 -0700194#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
195#define DRM_NOUVEAU_GEM_INFO 0x44
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700196struct drm_nouveau_svm_init {
197 __u64 unmanaged_addr;
198 __u64 unmanaged_size;
199};
200struct drm_nouveau_svm_bind {
201 __u64 header;
202 __u64 va_start;
203 __u64 va_end;
204 __u64 npages;
205 __u64 stride;
206 __u64 result;
207 __u64 reserved0;
208 __u64 reserved1;
209};
210#define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
211#define NOUVEAU_SVM_BIND_COMMAND_BITS 8
212#define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
213#define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
214#define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
215#define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
216#define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
217#define NOUVEAU_SVM_BIND_TARGET_BITS 32
218#define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
219#define NOUVEAU_SVM_BIND_VALID_BITS 48
220#define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
221#define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
222#define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700223#define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
224#define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
225#define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700226#define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
227#define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
Ben Cheng655a7c02013-10-16 16:09:24 -0700228#define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
Christopher Ferris82d75042015-01-26 10:57:07 -0800229#define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
Tao Baod7db5942015-01-28 10:07:51 -0800230#define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
231#define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
Ben Cheng655a7c02013-10-16 16:09:24 -0700232#define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700233#define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
234#define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
235#define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700236#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800237}
Christopher Ferris82d75042015-01-26 10:57:07 -0800238#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -0700239#endif