Elliott Hughes | 180edef | 2023-11-02 00:08:05 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is auto-generated. Modifications will be lost. |
| 3 | * |
| 4 | * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/ |
| 5 | * for more information. |
| 6 | */ |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 7 | #ifndef __VMW_PVRDMA_ABI_H__ |
| 8 | #define __VMW_PVRDMA_ABI_H__ |
| 9 | #include <linux/types.h> |
| 10 | #define PVRDMA_UVERBS_ABI_VERSION 3 |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 11 | #define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF |
| 12 | #define PVRDMA_UAR_QP_OFFSET 0 |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 13 | #define PVRDMA_UAR_QP_SEND (1 << 30) |
| 14 | #define PVRDMA_UAR_QP_RECV (1 << 31) |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 15 | #define PVRDMA_UAR_CQ_OFFSET 4 |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 16 | #define PVRDMA_UAR_CQ_ARM_SOL (1 << 29) |
| 17 | #define PVRDMA_UAR_CQ_ARM (1 << 30) |
| 18 | #define PVRDMA_UAR_CQ_POLL (1 << 31) |
| 19 | #define PVRDMA_UAR_SRQ_OFFSET 8 |
| 20 | #define PVRDMA_UAR_SRQ_RECV (1 << 30) |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 21 | enum pvrdma_wr_opcode { |
| 22 | PVRDMA_WR_RDMA_WRITE, |
| 23 | PVRDMA_WR_RDMA_WRITE_WITH_IMM, |
| 24 | PVRDMA_WR_SEND, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 25 | PVRDMA_WR_SEND_WITH_IMM, |
| 26 | PVRDMA_WR_RDMA_READ, |
| 27 | PVRDMA_WR_ATOMIC_CMP_AND_SWP, |
| 28 | PVRDMA_WR_ATOMIC_FETCH_AND_ADD, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 29 | PVRDMA_WR_LSO, |
| 30 | PVRDMA_WR_SEND_WITH_INV, |
| 31 | PVRDMA_WR_RDMA_READ_WITH_INV, |
| 32 | PVRDMA_WR_LOCAL_INV, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 33 | PVRDMA_WR_FAST_REG_MR, |
| 34 | PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP, |
| 35 | PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD, |
| 36 | PVRDMA_WR_BIND_MW, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 37 | PVRDMA_WR_REG_SIG_MR, |
Christopher Ferris | d842e43 | 2019-03-07 10:21:59 -0800 | [diff] [blame] | 38 | PVRDMA_WR_ERROR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 39 | }; |
| 40 | enum pvrdma_wc_status { |
| 41 | PVRDMA_WC_SUCCESS, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 42 | PVRDMA_WC_LOC_LEN_ERR, |
| 43 | PVRDMA_WC_LOC_QP_OP_ERR, |
| 44 | PVRDMA_WC_LOC_EEC_OP_ERR, |
| 45 | PVRDMA_WC_LOC_PROT_ERR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 46 | PVRDMA_WC_WR_FLUSH_ERR, |
| 47 | PVRDMA_WC_MW_BIND_ERR, |
| 48 | PVRDMA_WC_BAD_RESP_ERR, |
| 49 | PVRDMA_WC_LOC_ACCESS_ERR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 50 | PVRDMA_WC_REM_INV_REQ_ERR, |
| 51 | PVRDMA_WC_REM_ACCESS_ERR, |
| 52 | PVRDMA_WC_REM_OP_ERR, |
| 53 | PVRDMA_WC_RETRY_EXC_ERR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 54 | PVRDMA_WC_RNR_RETRY_EXC_ERR, |
| 55 | PVRDMA_WC_LOC_RDD_VIOL_ERR, |
| 56 | PVRDMA_WC_REM_INV_RD_REQ_ERR, |
| 57 | PVRDMA_WC_REM_ABORT_ERR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 58 | PVRDMA_WC_INV_EECN_ERR, |
| 59 | PVRDMA_WC_INV_EEC_STATE_ERR, |
| 60 | PVRDMA_WC_FATAL_ERR, |
| 61 | PVRDMA_WC_RESP_TIMEOUT_ERR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 62 | PVRDMA_WC_GENERAL_ERR, |
| 63 | }; |
| 64 | enum pvrdma_wc_opcode { |
| 65 | PVRDMA_WC_SEND, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 66 | PVRDMA_WC_RDMA_WRITE, |
| 67 | PVRDMA_WC_RDMA_READ, |
| 68 | PVRDMA_WC_COMP_SWAP, |
| 69 | PVRDMA_WC_FETCH_ADD, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 70 | PVRDMA_WC_BIND_MW, |
| 71 | PVRDMA_WC_LSO, |
| 72 | PVRDMA_WC_LOCAL_INV, |
| 73 | PVRDMA_WC_FAST_REG_MR, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 74 | PVRDMA_WC_MASKED_COMP_SWAP, |
| 75 | PVRDMA_WC_MASKED_FETCH_ADD, |
| 76 | PVRDMA_WC_RECV = 1 << 7, |
| 77 | PVRDMA_WC_RECV_RDMA_WITH_IMM, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 78 | }; |
| 79 | enum pvrdma_wc_flags { |
| 80 | PVRDMA_WC_GRH = 1 << 0, |
| 81 | PVRDMA_WC_WITH_IMM = 1 << 1, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 82 | PVRDMA_WC_WITH_INVALIDATE = 1 << 2, |
| 83 | PVRDMA_WC_IP_CSUM_OK = 1 << 3, |
| 84 | PVRDMA_WC_WITH_SMAC = 1 << 4, |
| 85 | PVRDMA_WC_WITH_VLAN = 1 << 5, |
Christopher Ferris | 1308ad3 | 2017-11-14 17:32:13 -0800 | [diff] [blame] | 86 | PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6, |
| 87 | PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE, |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 88 | }; |
Christopher Ferris | 05667cd | 2021-02-16 16:01:34 -0800 | [diff] [blame] | 89 | enum pvrdma_network_type { |
| 90 | PVRDMA_NETWORK_IB, |
| 91 | PVRDMA_NETWORK_ROCE_V1 = PVRDMA_NETWORK_IB, |
| 92 | PVRDMA_NETWORK_IPV4, |
| 93 | PVRDMA_NETWORK_IPV6 |
| 94 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 95 | struct pvrdma_alloc_ucontext_resp { |
| 96 | __u32 qp_tab_size; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 97 | __u32 reserved; |
| 98 | }; |
| 99 | struct pvrdma_alloc_pd_resp { |
| 100 | __u32 pdn; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 101 | __u32 reserved; |
| 102 | }; |
| 103 | struct pvrdma_create_cq { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 104 | __aligned_u64 buf_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 105 | __u32 buf_size; |
| 106 | __u32 reserved; |
| 107 | }; |
| 108 | struct pvrdma_create_cq_resp { |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 109 | __u32 cqn; |
| 110 | __u32 reserved; |
| 111 | }; |
| 112 | struct pvrdma_resize_cq { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 113 | __aligned_u64 buf_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 114 | __u32 buf_size; |
| 115 | __u32 reserved; |
| 116 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 117 | struct pvrdma_create_srq { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 118 | __aligned_u64 buf_addr; |
Christopher Ferris | 934ec94 | 2018-01-31 15:29:16 -0800 | [diff] [blame] | 119 | __u32 buf_size; |
| 120 | __u32 reserved; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 121 | }; |
| 122 | struct pvrdma_create_srq_resp { |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 123 | __u32 srqn; |
| 124 | __u32 reserved; |
| 125 | }; |
| 126 | struct pvrdma_create_qp { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 127 | __aligned_u64 rbuf_addr; |
| 128 | __aligned_u64 sbuf_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 129 | __u32 rbuf_size; |
| 130 | __u32 sbuf_size; |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 131 | __aligned_u64 qp_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 132 | }; |
Christopher Ferris | d32ca14 | 2020-02-04 16:16:51 -0800 | [diff] [blame] | 133 | struct pvrdma_create_qp_resp { |
| 134 | __u32 qpn; |
| 135 | __u32 qp_handle; |
| 136 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 137 | struct pvrdma_ex_cmp_swap { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 138 | __aligned_u64 swap_val; |
| 139 | __aligned_u64 compare_val; |
| 140 | __aligned_u64 swap_mask; |
| 141 | __aligned_u64 compare_mask; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 142 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 143 | struct pvrdma_ex_fetch_add { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 144 | __aligned_u64 add_val; |
| 145 | __aligned_u64 field_boundary; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 146 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 147 | struct pvrdma_av { |
| 148 | __u32 port_pd; |
| 149 | __u32 sl_tclass_flowlabel; |
| 150 | __u8 dgid[16]; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 151 | __u8 src_path_bits; |
| 152 | __u8 gid_index; |
| 153 | __u8 stat_rate; |
| 154 | __u8 hop_limit; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 155 | __u8 dmac[6]; |
| 156 | __u8 reserved[6]; |
| 157 | }; |
| 158 | struct pvrdma_sge { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 159 | __aligned_u64 addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 160 | __u32 length; |
| 161 | __u32 lkey; |
| 162 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 163 | struct pvrdma_rq_wqe_hdr { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 164 | __aligned_u64 wr_id; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 165 | __u32 num_sge; |
| 166 | __u32 total_len; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 167 | }; |
| 168 | struct pvrdma_sq_wqe_hdr { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 169 | __aligned_u64 wr_id; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 170 | __u32 num_sge; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 171 | __u32 total_len; |
| 172 | __u32 opcode; |
| 173 | __u32 send_flags; |
| 174 | union { |
Christopher Ferris | 525ce91 | 2017-07-26 13:12:53 -0700 | [diff] [blame] | 175 | __be32 imm_data; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 176 | __u32 invalidate_rkey; |
| 177 | } ex; |
| 178 | __u32 reserved; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 179 | union { |
| 180 | struct { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 181 | __aligned_u64 remote_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 182 | __u32 rkey; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 183 | __u8 reserved[4]; |
| 184 | } rdma; |
| 185 | struct { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 186 | __aligned_u64 remote_addr; |
| 187 | __aligned_u64 compare_add; |
| 188 | __aligned_u64 swap; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 189 | __u32 rkey; |
| 190 | __u32 reserved; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 191 | } atomic; |
| 192 | struct { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 193 | __aligned_u64 remote_addr; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 194 | __u32 log_arg_sz; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 195 | __u32 rkey; |
| 196 | union { |
| 197 | struct pvrdma_ex_cmp_swap cmp_swap; |
| 198 | struct pvrdma_ex_fetch_add fetch_add; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 199 | } wr_data; |
| 200 | } masked_atomics; |
| 201 | struct { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 202 | __aligned_u64 iova_start; |
| 203 | __aligned_u64 pl_pdir_dma; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 204 | __u32 page_shift; |
| 205 | __u32 page_list_len; |
| 206 | __u32 length; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 207 | __u32 access_flags; |
| 208 | __u32 rkey; |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 209 | __u32 reserved; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 210 | } fast_reg; |
| 211 | struct { |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 212 | __u32 remote_qpn; |
| 213 | __u32 remote_qkey; |
| 214 | struct pvrdma_av av; |
| 215 | } ud; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 216 | } wr; |
| 217 | }; |
| 218 | struct pvrdma_cqe { |
Christopher Ferris | 76a1d45 | 2018-06-27 14:12:29 -0700 | [diff] [blame] | 219 | __aligned_u64 wr_id; |
| 220 | __aligned_u64 qp; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 221 | __u32 opcode; |
| 222 | __u32 status; |
| 223 | __u32 byte_len; |
Christopher Ferris | 525ce91 | 2017-07-26 13:12:53 -0700 | [diff] [blame] | 224 | __be32 imm_data; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 225 | __u32 src_qp; |
| 226 | __u32 wc_flags; |
| 227 | __u32 vendor_err; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 228 | __u16 pkey_index; |
| 229 | __u16 slid; |
| 230 | __u8 sl; |
| 231 | __u8 dlid_path_bits; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 232 | __u8 port_num; |
| 233 | __u8 smac[6]; |
Christopher Ferris | 1308ad3 | 2017-11-14 17:32:13 -0800 | [diff] [blame] | 234 | __u8 network_hdr_type; |
| 235 | __u8 reserved2[6]; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 236 | }; |
Christopher Ferris | 48af7cb | 2017-02-21 12:35:09 -0800 | [diff] [blame] | 237 | #endif |