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Christopher Ferris48af7cb2017-02-21 12:35:09 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMW_PVRDMA_ABI_H__
20#define __VMW_PVRDMA_ABI_H__
21#include <linux/types.h>
22#define PVRDMA_UVERBS_ABI_VERSION 3
Christopher Ferris48af7cb2017-02-21 12:35:09 -080023#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF
24#define PVRDMA_UAR_QP_OFFSET 0
Christopher Ferris76a1d452018-06-27 14:12:29 -070025#define PVRDMA_UAR_QP_SEND (1 << 30)
26#define PVRDMA_UAR_QP_RECV (1 << 31)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080027#define PVRDMA_UAR_CQ_OFFSET 4
Christopher Ferris76a1d452018-06-27 14:12:29 -070028#define PVRDMA_UAR_CQ_ARM_SOL (1 << 29)
29#define PVRDMA_UAR_CQ_ARM (1 << 30)
30#define PVRDMA_UAR_CQ_POLL (1 << 31)
31#define PVRDMA_UAR_SRQ_OFFSET 8
32#define PVRDMA_UAR_SRQ_RECV (1 << 30)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080033enum pvrdma_wr_opcode {
34 PVRDMA_WR_RDMA_WRITE,
35 PVRDMA_WR_RDMA_WRITE_WITH_IMM,
36 PVRDMA_WR_SEND,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080037 PVRDMA_WR_SEND_WITH_IMM,
38 PVRDMA_WR_RDMA_READ,
39 PVRDMA_WR_ATOMIC_CMP_AND_SWP,
40 PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080041 PVRDMA_WR_LSO,
42 PVRDMA_WR_SEND_WITH_INV,
43 PVRDMA_WR_RDMA_READ_WITH_INV,
44 PVRDMA_WR_LOCAL_INV,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080045 PVRDMA_WR_FAST_REG_MR,
46 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
47 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
48 PVRDMA_WR_BIND_MW,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080049 PVRDMA_WR_REG_SIG_MR,
50};
51enum pvrdma_wc_status {
52 PVRDMA_WC_SUCCESS,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080053 PVRDMA_WC_LOC_LEN_ERR,
54 PVRDMA_WC_LOC_QP_OP_ERR,
55 PVRDMA_WC_LOC_EEC_OP_ERR,
56 PVRDMA_WC_LOC_PROT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080057 PVRDMA_WC_WR_FLUSH_ERR,
58 PVRDMA_WC_MW_BIND_ERR,
59 PVRDMA_WC_BAD_RESP_ERR,
60 PVRDMA_WC_LOC_ACCESS_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080061 PVRDMA_WC_REM_INV_REQ_ERR,
62 PVRDMA_WC_REM_ACCESS_ERR,
63 PVRDMA_WC_REM_OP_ERR,
64 PVRDMA_WC_RETRY_EXC_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080065 PVRDMA_WC_RNR_RETRY_EXC_ERR,
66 PVRDMA_WC_LOC_RDD_VIOL_ERR,
67 PVRDMA_WC_REM_INV_RD_REQ_ERR,
68 PVRDMA_WC_REM_ABORT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080069 PVRDMA_WC_INV_EECN_ERR,
70 PVRDMA_WC_INV_EEC_STATE_ERR,
71 PVRDMA_WC_FATAL_ERR,
72 PVRDMA_WC_RESP_TIMEOUT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080073 PVRDMA_WC_GENERAL_ERR,
74};
75enum pvrdma_wc_opcode {
76 PVRDMA_WC_SEND,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080077 PVRDMA_WC_RDMA_WRITE,
78 PVRDMA_WC_RDMA_READ,
79 PVRDMA_WC_COMP_SWAP,
80 PVRDMA_WC_FETCH_ADD,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080081 PVRDMA_WC_BIND_MW,
82 PVRDMA_WC_LSO,
83 PVRDMA_WC_LOCAL_INV,
84 PVRDMA_WC_FAST_REG_MR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080085 PVRDMA_WC_MASKED_COMP_SWAP,
86 PVRDMA_WC_MASKED_FETCH_ADD,
87 PVRDMA_WC_RECV = 1 << 7,
88 PVRDMA_WC_RECV_RDMA_WITH_IMM,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080089};
90enum pvrdma_wc_flags {
91 PVRDMA_WC_GRH = 1 << 0,
92 PVRDMA_WC_WITH_IMM = 1 << 1,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080093 PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
94 PVRDMA_WC_IP_CSUM_OK = 1 << 3,
95 PVRDMA_WC_WITH_SMAC = 1 << 4,
96 PVRDMA_WC_WITH_VLAN = 1 << 5,
Christopher Ferris1308ad32017-11-14 17:32:13 -080097 PVRDMA_WC_WITH_NETWORK_HDR_TYPE = 1 << 6,
98 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_NETWORK_HDR_TYPE,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080099};
100struct pvrdma_alloc_ucontext_resp {
101 __u32 qp_tab_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800102 __u32 reserved;
103};
104struct pvrdma_alloc_pd_resp {
105 __u32 pdn;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800106 __u32 reserved;
107};
108struct pvrdma_create_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700109 __aligned_u64 buf_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800110 __u32 buf_size;
111 __u32 reserved;
112};
113struct pvrdma_create_cq_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800114 __u32 cqn;
115 __u32 reserved;
116};
117struct pvrdma_resize_cq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700118 __aligned_u64 buf_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800119 __u32 buf_size;
120 __u32 reserved;
121};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800122struct pvrdma_create_srq {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700123 __aligned_u64 buf_addr;
Christopher Ferris934ec942018-01-31 15:29:16 -0800124 __u32 buf_size;
125 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800126};
127struct pvrdma_create_srq_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800128 __u32 srqn;
129 __u32 reserved;
130};
131struct pvrdma_create_qp {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700132 __aligned_u64 rbuf_addr;
133 __aligned_u64 sbuf_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800134 __u32 rbuf_size;
135 __u32 sbuf_size;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700136 __aligned_u64 qp_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800137};
138struct pvrdma_ex_cmp_swap {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700139 __aligned_u64 swap_val;
140 __aligned_u64 compare_val;
141 __aligned_u64 swap_mask;
142 __aligned_u64 compare_mask;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800143};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800144struct pvrdma_ex_fetch_add {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700145 __aligned_u64 add_val;
146 __aligned_u64 field_boundary;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800147};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800148struct pvrdma_av {
149 __u32 port_pd;
150 __u32 sl_tclass_flowlabel;
151 __u8 dgid[16];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800152 __u8 src_path_bits;
153 __u8 gid_index;
154 __u8 stat_rate;
155 __u8 hop_limit;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800156 __u8 dmac[6];
157 __u8 reserved[6];
158};
159struct pvrdma_sge {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700160 __aligned_u64 addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800161 __u32 length;
162 __u32 lkey;
163};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800164struct pvrdma_rq_wqe_hdr {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700165 __aligned_u64 wr_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800166 __u32 num_sge;
167 __u32 total_len;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800168};
169struct pvrdma_sq_wqe_hdr {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700170 __aligned_u64 wr_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800171 __u32 num_sge;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800172 __u32 total_len;
173 __u32 opcode;
174 __u32 send_flags;
175 union {
Christopher Ferris525ce912017-07-26 13:12:53 -0700176 __be32 imm_data;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800177 __u32 invalidate_rkey;
178 } ex;
179 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800180 union {
181 struct {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700182 __aligned_u64 remote_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800183 __u32 rkey;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800184 __u8 reserved[4];
185 } rdma;
186 struct {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700187 __aligned_u64 remote_addr;
188 __aligned_u64 compare_add;
189 __aligned_u64 swap;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800190 __u32 rkey;
191 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800192 } atomic;
193 struct {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700194 __aligned_u64 remote_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800195 __u32 log_arg_sz;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800196 __u32 rkey;
197 union {
198 struct pvrdma_ex_cmp_swap cmp_swap;
199 struct pvrdma_ex_fetch_add fetch_add;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800200 } wr_data;
201 } masked_atomics;
202 struct {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700203 __aligned_u64 iova_start;
204 __aligned_u64 pl_pdir_dma;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800205 __u32 page_shift;
206 __u32 page_list_len;
207 __u32 length;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800208 __u32 access_flags;
209 __u32 rkey;
Christopher Ferris76a1d452018-06-27 14:12:29 -0700210 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800211 } fast_reg;
212 struct {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800213 __u32 remote_qpn;
214 __u32 remote_qkey;
215 struct pvrdma_av av;
216 } ud;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800217 } wr;
218};
219struct pvrdma_cqe {
Christopher Ferris76a1d452018-06-27 14:12:29 -0700220 __aligned_u64 wr_id;
221 __aligned_u64 qp;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800222 __u32 opcode;
223 __u32 status;
224 __u32 byte_len;
Christopher Ferris525ce912017-07-26 13:12:53 -0700225 __be32 imm_data;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800226 __u32 src_qp;
227 __u32 wc_flags;
228 __u32 vendor_err;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800229 __u16 pkey_index;
230 __u16 slid;
231 __u8 sl;
232 __u8 dlid_path_bits;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800233 __u8 port_num;
234 __u8 smac[6];
Christopher Ferris1308ad32017-11-14 17:32:13 -0800235 __u8 network_hdr_type;
236 __u8 reserved2[6];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800237};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800238#endif