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Christopher Ferris48af7cb2017-02-21 12:35:09 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMW_PVRDMA_ABI_H__
20#define __VMW_PVRDMA_ABI_H__
21#include <linux/types.h>
22#define PVRDMA_UVERBS_ABI_VERSION 3
Christopher Ferris48af7cb2017-02-21 12:35:09 -080023#define PVRDMA_UAR_HANDLE_MASK 0x00FFFFFF
24#define PVRDMA_UAR_QP_OFFSET 0
25#define PVRDMA_UAR_QP_SEND BIT(30)
26#define PVRDMA_UAR_QP_RECV BIT(31)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080027#define PVRDMA_UAR_CQ_OFFSET 4
28#define PVRDMA_UAR_CQ_ARM_SOL BIT(29)
29#define PVRDMA_UAR_CQ_ARM BIT(30)
30#define PVRDMA_UAR_CQ_POLL BIT(31)
Christopher Ferris48af7cb2017-02-21 12:35:09 -080031enum pvrdma_wr_opcode {
32 PVRDMA_WR_RDMA_WRITE,
33 PVRDMA_WR_RDMA_WRITE_WITH_IMM,
34 PVRDMA_WR_SEND,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080035 PVRDMA_WR_SEND_WITH_IMM,
36 PVRDMA_WR_RDMA_READ,
37 PVRDMA_WR_ATOMIC_CMP_AND_SWP,
38 PVRDMA_WR_ATOMIC_FETCH_AND_ADD,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080039 PVRDMA_WR_LSO,
40 PVRDMA_WR_SEND_WITH_INV,
41 PVRDMA_WR_RDMA_READ_WITH_INV,
42 PVRDMA_WR_LOCAL_INV,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080043 PVRDMA_WR_FAST_REG_MR,
44 PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP,
45 PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD,
46 PVRDMA_WR_BIND_MW,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080047 PVRDMA_WR_REG_SIG_MR,
48};
49enum pvrdma_wc_status {
50 PVRDMA_WC_SUCCESS,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080051 PVRDMA_WC_LOC_LEN_ERR,
52 PVRDMA_WC_LOC_QP_OP_ERR,
53 PVRDMA_WC_LOC_EEC_OP_ERR,
54 PVRDMA_WC_LOC_PROT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080055 PVRDMA_WC_WR_FLUSH_ERR,
56 PVRDMA_WC_MW_BIND_ERR,
57 PVRDMA_WC_BAD_RESP_ERR,
58 PVRDMA_WC_LOC_ACCESS_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080059 PVRDMA_WC_REM_INV_REQ_ERR,
60 PVRDMA_WC_REM_ACCESS_ERR,
61 PVRDMA_WC_REM_OP_ERR,
62 PVRDMA_WC_RETRY_EXC_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080063 PVRDMA_WC_RNR_RETRY_EXC_ERR,
64 PVRDMA_WC_LOC_RDD_VIOL_ERR,
65 PVRDMA_WC_REM_INV_RD_REQ_ERR,
66 PVRDMA_WC_REM_ABORT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080067 PVRDMA_WC_INV_EECN_ERR,
68 PVRDMA_WC_INV_EEC_STATE_ERR,
69 PVRDMA_WC_FATAL_ERR,
70 PVRDMA_WC_RESP_TIMEOUT_ERR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080071 PVRDMA_WC_GENERAL_ERR,
72};
73enum pvrdma_wc_opcode {
74 PVRDMA_WC_SEND,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080075 PVRDMA_WC_RDMA_WRITE,
76 PVRDMA_WC_RDMA_READ,
77 PVRDMA_WC_COMP_SWAP,
78 PVRDMA_WC_FETCH_ADD,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080079 PVRDMA_WC_BIND_MW,
80 PVRDMA_WC_LSO,
81 PVRDMA_WC_LOCAL_INV,
82 PVRDMA_WC_FAST_REG_MR,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080083 PVRDMA_WC_MASKED_COMP_SWAP,
84 PVRDMA_WC_MASKED_FETCH_ADD,
85 PVRDMA_WC_RECV = 1 << 7,
86 PVRDMA_WC_RECV_RDMA_WITH_IMM,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080087};
88enum pvrdma_wc_flags {
89 PVRDMA_WC_GRH = 1 << 0,
90 PVRDMA_WC_WITH_IMM = 1 << 1,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080091 PVRDMA_WC_WITH_INVALIDATE = 1 << 2,
92 PVRDMA_WC_IP_CSUM_OK = 1 << 3,
93 PVRDMA_WC_WITH_SMAC = 1 << 4,
94 PVRDMA_WC_WITH_VLAN = 1 << 5,
Christopher Ferris48af7cb2017-02-21 12:35:09 -080095 PVRDMA_WC_FLAGS_MAX = PVRDMA_WC_WITH_VLAN,
96};
97struct pvrdma_alloc_ucontext_resp {
98 __u32 qp_tab_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -080099 __u32 reserved;
100};
101struct pvrdma_alloc_pd_resp {
102 __u32 pdn;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800103 __u32 reserved;
104};
105struct pvrdma_create_cq {
106 __u64 buf_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800107 __u32 buf_size;
108 __u32 reserved;
109};
110struct pvrdma_create_cq_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800111 __u32 cqn;
112 __u32 reserved;
113};
114struct pvrdma_resize_cq {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800115 __u64 buf_addr;
116 __u32 buf_size;
117 __u32 reserved;
118};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800119struct pvrdma_create_srq {
120 __u64 buf_addr;
121};
122struct pvrdma_create_srq_resp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800123 __u32 srqn;
124 __u32 reserved;
125};
126struct pvrdma_create_qp {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800127 __u64 rbuf_addr;
128 __u64 sbuf_addr;
129 __u32 rbuf_size;
130 __u32 sbuf_size;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800131 __u64 qp_addr;
132};
133struct pvrdma_ex_cmp_swap {
134 __u64 swap_val;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800135 __u64 compare_val;
136 __u64 swap_mask;
137 __u64 compare_mask;
138};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800139struct pvrdma_ex_fetch_add {
140 __u64 add_val;
141 __u64 field_boundary;
142};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800143struct pvrdma_av {
144 __u32 port_pd;
145 __u32 sl_tclass_flowlabel;
146 __u8 dgid[16];
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800147 __u8 src_path_bits;
148 __u8 gid_index;
149 __u8 stat_rate;
150 __u8 hop_limit;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800151 __u8 dmac[6];
152 __u8 reserved[6];
153};
154struct pvrdma_sge {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800155 __u64 addr;
156 __u32 length;
157 __u32 lkey;
158};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800159struct pvrdma_rq_wqe_hdr {
160 __u64 wr_id;
161 __u32 num_sge;
162 __u32 total_len;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800163};
164struct pvrdma_sq_wqe_hdr {
165 __u64 wr_id;
166 __u32 num_sge;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800167 __u32 total_len;
168 __u32 opcode;
169 __u32 send_flags;
170 union {
Christopher Ferris525ce912017-07-26 13:12:53 -0700171 __be32 imm_data;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800172 __u32 invalidate_rkey;
173 } ex;
174 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800175 union {
176 struct {
177 __u64 remote_addr;
178 __u32 rkey;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800179 __u8 reserved[4];
180 } rdma;
181 struct {
182 __u64 remote_addr;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800183 __u64 compare_add;
184 __u64 swap;
185 __u32 rkey;
186 __u32 reserved;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800187 } atomic;
188 struct {
189 __u64 remote_addr;
190 __u32 log_arg_sz;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800191 __u32 rkey;
192 union {
193 struct pvrdma_ex_cmp_swap cmp_swap;
194 struct pvrdma_ex_fetch_add fetch_add;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800195 } wr_data;
196 } masked_atomics;
197 struct {
198 __u64 iova_start;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800199 __u64 pl_pdir_dma;
200 __u32 page_shift;
201 __u32 page_list_len;
202 __u32 length;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800203 __u32 access_flags;
204 __u32 rkey;
205 } fast_reg;
206 struct {
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800207 __u32 remote_qpn;
208 __u32 remote_qkey;
209 struct pvrdma_av av;
210 } ud;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800211 } wr;
212};
213struct pvrdma_cqe {
214 __u64 wr_id;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800215 __u64 qp;
216 __u32 opcode;
217 __u32 status;
218 __u32 byte_len;
Christopher Ferris525ce912017-07-26 13:12:53 -0700219 __be32 imm_data;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800220 __u32 src_qp;
221 __u32 wc_flags;
222 __u32 vendor_err;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800223 __u16 pkey_index;
224 __u16 slid;
225 __u8 sl;
226 __u8 dlid_path_bits;
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800227 __u8 port_num;
228 __u8 smac[6];
229 __u8 reserved2[7];
230};
Christopher Ferris48af7cb2017-02-21 12:35:09 -0800231#endif