blob: 7ea6a727c970737f6c857bfa08ab7d841c702907 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _UAPI__LINUX_MDIO_H__
8#define _UAPI__LINUX_MDIO_H__
9#include <linux/types.h>
10#include <linux/mii.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070011#define MDIO_MMD_PMAPMD 1
12#define MDIO_MMD_WIS 2
13#define MDIO_MMD_PCS 3
14#define MDIO_MMD_PHYXS 4
Ben Cheng655a7c02013-10-16 16:09:24 -070015#define MDIO_MMD_DTEXS 5
16#define MDIO_MMD_TC 6
17#define MDIO_MMD_AN 7
18#define MDIO_MMD_C22EXT 29
Ben Cheng655a7c02013-10-16 16:09:24 -070019#define MDIO_MMD_VEND1 30
20#define MDIO_MMD_VEND2 31
21#define MDIO_CTRL1 MII_BMCR
22#define MDIO_STAT1 MII_BMSR
Ben Cheng655a7c02013-10-16 16:09:24 -070023#define MDIO_DEVID1 MII_PHYSID1
24#define MDIO_DEVID2 MII_PHYSID2
25#define MDIO_SPEED 4
26#define MDIO_DEVS1 5
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define MDIO_DEVS2 6
28#define MDIO_CTRL2 7
29#define MDIO_STAT2 8
30#define MDIO_PMA_TXDIS 9
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define MDIO_PMA_RXDET 10
32#define MDIO_PMA_EXTABLE 11
33#define MDIO_PKGID1 14
34#define MDIO_PKGID2 15
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define MDIO_AN_ADVERTISE 16
36#define MDIO_AN_LPA 19
37#define MDIO_PCS_EEE_ABLE 20
Christopher Ferris9584fa42019-12-09 15:36:13 -080038#define MDIO_PCS_EEE_ABLE2 21
Christopher Ferris24f97eb2019-05-20 12:58:13 -070039#define MDIO_PMA_NG_EXTABLE 21
Ben Cheng655a7c02013-10-16 16:09:24 -070040#define MDIO_PCS_EEE_WK_ERR 22
Ben Cheng655a7c02013-10-16 16:09:24 -070041#define MDIO_PHYXS_LNSTAT 24
42#define MDIO_AN_EEE_ADV 60
43#define MDIO_AN_EEE_LPABLE 61
Christopher Ferris9584fa42019-12-09 15:36:13 -080044#define MDIO_AN_EEE_ADV2 62
45#define MDIO_AN_EEE_LPABLE2 63
Christopher Ferrisa4792612022-01-10 13:51:15 -080046#define MDIO_AN_CTRL2 64
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define MDIO_PMA_10GBT_SWAPPOL 130
Ben Cheng655a7c02013-10-16 16:09:24 -070048#define MDIO_PMA_10GBT_TXPWR 131
49#define MDIO_PMA_10GBT_SNR 133
Christopher Ferrisa4792612022-01-10 13:51:15 -080050#define MDIO_PMA_10GBR_FSRT_CSR 147
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define MDIO_PMA_10GBR_FECABLE 170
52#define MDIO_PCS_10GBX_STAT1 24
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define MDIO_PCS_10GBRT_STAT1 32
54#define MDIO_PCS_10GBRT_STAT2 33
55#define MDIO_AN_10GBT_CTRL 32
56#define MDIO_AN_10GBT_STAT 33
Christopher Ferris80ae69d2022-08-02 16:32:21 -070057#define MDIO_B10L_PMA_CTRL 2294
58#define MDIO_PMA_10T1L_STAT 2295
59#define MDIO_PCS_10T1L_CTRL 2278
60#define MDIO_PMA_PMD_BT1 18
61#define MDIO_AN_T1_CTRL 512
62#define MDIO_AN_T1_STAT 513
63#define MDIO_AN_T1_ADV_L 514
64#define MDIO_AN_T1_ADV_M 515
65#define MDIO_AN_T1_ADV_H 516
66#define MDIO_AN_T1_LP_L 517
67#define MDIO_AN_T1_LP_M 518
68#define MDIO_AN_T1_LP_H 519
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +000069#define MDIO_AN_10BT1_AN_CTRL 526
70#define MDIO_AN_10BT1_AN_STAT 527
Christopher Ferris80ae69d2022-08-02 16:32:21 -070071#define MDIO_PMA_PMD_BT1_CTRL 2100
Christopher Ferris67d1e5e2023-10-31 13:36:37 -070072#define MDIO_PCS_1000BT1_CTRL 2304
73#define MDIO_PCS_1000BT1_STAT 2305
Ben Cheng655a7c02013-10-16 16:09:24 -070074#define MDIO_PMA_LASI_RXCTRL 0x9000
75#define MDIO_PMA_LASI_TXCTRL 0x9001
76#define MDIO_PMA_LASI_CTRL 0x9002
77#define MDIO_PMA_LASI_RXSTAT 0x9003
Ben Cheng655a7c02013-10-16 16:09:24 -070078#define MDIO_PMA_LASI_TXSTAT 0x9004
79#define MDIO_PMA_LASI_STAT 0x9005
80#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
81#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
Ben Cheng655a7c02013-10-16 16:09:24 -070082#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
83#define MDIO_CTRL1_LPOWER BMCR_PDOWN
84#define MDIO_CTRL1_RESET BMCR_RESET
85#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -070086#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
87#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
88#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
89#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
Ben Cheng655a7c02013-10-16 16:09:24 -070090#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
91#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
92#define MDIO_AN_CTRL1_XNP 0x2000
93#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400
Ben Cheng655a7c02013-10-16 16:09:24 -070094#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
95#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
Christopher Ferris24f97eb2019-05-20 12:58:13 -070096#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
97#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
Ben Cheng655a7c02013-10-16 16:09:24 -070098#define MDIO_STAT1_LPOWERABLE 0x0002
99#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
Ben Cheng655a7c02013-10-16 16:09:24 -0700100#define MDIO_STAT1_FAULT 0x0080
101#define MDIO_AN_STAT1_LPABLE 0x0001
102#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
103#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
Ben Cheng655a7c02013-10-16 16:09:24 -0700104#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
105#define MDIO_AN_STAT1_PAGE 0x0040
106#define MDIO_AN_STAT1_XNP 0x0080
107#define MDIO_SPEED_10G 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700108#define MDIO_PMA_SPEED_2B 0x0002
109#define MDIO_PMA_SPEED_10P 0x0004
110#define MDIO_PMA_SPEED_1000 0x0010
111#define MDIO_PMA_SPEED_100 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700112#define MDIO_PMA_SPEED_10 0x0040
113#define MDIO_PCS_SPEED_10P2B 0x0002
Christopher Ferrisfcc3b4f2021-07-01 01:30:21 +0000114#define MDIO_PCS_SPEED_2_5G 0x0040
115#define MDIO_PCS_SPEED_5G 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700116#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700117#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700118#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
Ben Cheng655a7c02013-10-16 16:09:24 -0700119#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
120#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
121#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
122#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
Ben Cheng655a7c02013-10-16 16:09:24 -0700123#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
124#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
125#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700126#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
127#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700128#define MDIO_PMA_CTRL2_TYPE 0x000f
Ben Cheng655a7c02013-10-16 16:09:24 -0700129#define MDIO_PMA_CTRL2_10GBCX4 0x0000
130#define MDIO_PMA_CTRL2_10GBEW 0x0001
131#define MDIO_PMA_CTRL2_10GBLW 0x0002
132#define MDIO_PMA_CTRL2_10GBSW 0x0003
Ben Cheng655a7c02013-10-16 16:09:24 -0700133#define MDIO_PMA_CTRL2_10GBLX4 0x0004
134#define MDIO_PMA_CTRL2_10GBER 0x0005
135#define MDIO_PMA_CTRL2_10GBLR 0x0006
136#define MDIO_PMA_CTRL2_10GBSR 0x0007
Ben Cheng655a7c02013-10-16 16:09:24 -0700137#define MDIO_PMA_CTRL2_10GBLRM 0x0008
138#define MDIO_PMA_CTRL2_10GBT 0x0009
139#define MDIO_PMA_CTRL2_10GBKX4 0x000a
140#define MDIO_PMA_CTRL2_10GBKR 0x000b
Ben Cheng655a7c02013-10-16 16:09:24 -0700141#define MDIO_PMA_CTRL2_1000BT 0x000c
142#define MDIO_PMA_CTRL2_1000BKX 0x000d
143#define MDIO_PMA_CTRL2_100BTX 0x000e
144#define MDIO_PMA_CTRL2_10BT 0x000f
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700145#define MDIO_PMA_CTRL2_2_5GBT 0x0030
146#define MDIO_PMA_CTRL2_5GBT 0x0031
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700147#define MDIO_PMA_CTRL2_BASET1 0x003D
Ben Cheng655a7c02013-10-16 16:09:24 -0700148#define MDIO_PCS_CTRL2_TYPE 0x0003
149#define MDIO_PCS_CTRL2_10GBR 0x0000
150#define MDIO_PCS_CTRL2_10GBX 0x0001
151#define MDIO_PCS_CTRL2_10GBW 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700152#define MDIO_PCS_CTRL2_10GBT 0x0003
153#define MDIO_STAT2_RXFAULT 0x0400
154#define MDIO_STAT2_TXFAULT 0x0800
155#define MDIO_STAT2_DEVPRST 0xc000
Ben Cheng655a7c02013-10-16 16:09:24 -0700156#define MDIO_STAT2_DEVPRST_VAL 0x8000
157#define MDIO_PMA_STAT2_LBABLE 0x0001
158#define MDIO_PMA_STAT2_10GBEW 0x0002
159#define MDIO_PMA_STAT2_10GBLW 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700160#define MDIO_PMA_STAT2_10GBSW 0x0008
161#define MDIO_PMA_STAT2_10GBLX4 0x0010
162#define MDIO_PMA_STAT2_10GBER 0x0020
163#define MDIO_PMA_STAT2_10GBLR 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700164#define MDIO_PMA_STAT2_10GBSR 0x0080
165#define MDIO_PMD_STAT2_TXDISAB 0x0100
166#define MDIO_PMA_STAT2_EXTABLE 0x0200
167#define MDIO_PMA_STAT2_RXFLTABLE 0x1000
Ben Cheng655a7c02013-10-16 16:09:24 -0700168#define MDIO_PMA_STAT2_TXFLTABLE 0x2000
169#define MDIO_PCS_STAT2_10GBR 0x0001
170#define MDIO_PCS_STAT2_10GBX 0x0002
171#define MDIO_PCS_STAT2_10GBW 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700172#define MDIO_PCS_STAT2_RXFLTABLE 0x1000
173#define MDIO_PCS_STAT2_TXFLTABLE 0x2000
174#define MDIO_PMD_TXDIS_GLOBAL 0x0001
175#define MDIO_PMD_TXDIS_0 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700176#define MDIO_PMD_TXDIS_1 0x0004
177#define MDIO_PMD_TXDIS_2 0x0008
178#define MDIO_PMD_TXDIS_3 0x0010
179#define MDIO_PMD_RXDET_GLOBAL 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700180#define MDIO_PMD_RXDET_0 0x0002
181#define MDIO_PMD_RXDET_1 0x0004
182#define MDIO_PMD_RXDET_2 0x0008
183#define MDIO_PMD_RXDET_3 0x0010
Ben Cheng655a7c02013-10-16 16:09:24 -0700184#define MDIO_PMA_EXTABLE_10GCX4 0x0001
185#define MDIO_PMA_EXTABLE_10GBLRM 0x0002
186#define MDIO_PMA_EXTABLE_10GBT 0x0004
187#define MDIO_PMA_EXTABLE_10GBKX4 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700188#define MDIO_PMA_EXTABLE_10GBKR 0x0010
189#define MDIO_PMA_EXTABLE_1000BT 0x0020
190#define MDIO_PMA_EXTABLE_1000BKX 0x0040
191#define MDIO_PMA_EXTABLE_100BTX 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700192#define MDIO_PMA_EXTABLE_10BT 0x0100
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700193#define MDIO_PMA_EXTABLE_BT1 0x0800
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700194#define MDIO_PMA_EXTABLE_NBT 0x4000
Christopher Ferris8666d042023-09-06 14:55:31 -0700195#define MDIO_AN_C73_0_S_MASK GENMASK(4, 0)
196#define MDIO_AN_C73_0_E_MASK GENMASK(9, 5)
197#define MDIO_AN_C73_0_PAUSE BIT(10)
198#define MDIO_AN_C73_0_ASM_DIR BIT(11)
199#define MDIO_AN_C73_0_C2 BIT(12)
200#define MDIO_AN_C73_0_RF BIT(13)
201#define MDIO_AN_C73_0_ACK BIT(14)
202#define MDIO_AN_C73_0_NP BIT(15)
203#define MDIO_AN_C73_1_T_MASK GENMASK(4, 0)
204#define MDIO_AN_C73_1_1000BASE_KX BIT(5)
205#define MDIO_AN_C73_1_10GBASE_KX4 BIT(6)
206#define MDIO_AN_C73_1_10GBASE_KR BIT(7)
207#define MDIO_AN_C73_1_40GBASE_KR4 BIT(8)
208#define MDIO_AN_C73_1_40GBASE_CR4 BIT(9)
209#define MDIO_AN_C73_1_100GBASE_CR10 BIT(10)
210#define MDIO_AN_C73_1_100GBASE_KP4 BIT(11)
211#define MDIO_AN_C73_1_100GBASE_KR4 BIT(12)
212#define MDIO_AN_C73_1_100GBASE_CR4 BIT(13)
213#define MDIO_AN_C73_1_25GBASE_R_S BIT(14)
214#define MDIO_AN_C73_1_25GBASE_R BIT(15)
215#define MDIO_AN_C73_2_2500BASE_KX BIT(0)
216#define MDIO_AN_C73_2_5GBASE_KR BIT(1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700217#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
218#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
219#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
221#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
222#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001
223#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700224#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100
225#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200
226#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400
227#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700228#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001
229#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
230#define MDIO_PMA_10GBT_SNR_MAX 127
231#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700232#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
Christopher Ferrisa4792612022-01-10 13:51:15 -0800233#define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700234#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001
235#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
236#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
Christopher Ferrisa4792612022-01-10 13:51:15 -0800237#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700238#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080
239#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700240#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700241#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020
242#define MDIO_AN_10GBT_STAT_LP5G 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700243#define MDIO_AN_10GBT_STAT_LPTRR 0x0200
244#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400
245#define MDIO_AN_10GBT_STAT_LP10G 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700246#define MDIO_AN_10GBT_STAT_REMOK 0x1000
247#define MDIO_AN_10GBT_STAT_LOCOK 0x2000
248#define MDIO_AN_10GBT_STAT_MS 0x4000
249#define MDIO_AN_10GBT_STAT_MSFLT 0x8000
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700250#define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001
251#define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400
252#define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800
253#define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000
254#define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000
255#define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000
256#define MDIO_PMA_10T1L_STAT_LINK 0x0001
257#define MDIO_PMA_10T1L_STAT_FAULT 0x0002
258#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004
259#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200
260#define MDIO_PMA_10T1L_STAT_EEE 0x0400
261#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800
262#define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000
263#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000
264#define MDIO_PCS_10T1L_CTRL_LB 0x4000
265#define MDIO_PCS_10T1L_CTRL_RESET 0x8000
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700266#define MDIO_PMA_PMD_BT1_B100_ABLE 0x0001
267#define MDIO_PMA_PMD_BT1_B1000_ABLE 0x0002
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700268#define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004
269#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
270#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
271#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000
272#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
273#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
274#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
275#define MDIO_AN_T1_ADV_M_B10L 0x4000
276#define MDIO_AN_T1_ADV_M_MST 0x0010
277#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000
278#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000
279#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
280#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
281#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000
282#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
283#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
284#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
285#define MDIO_AN_T1_LP_M_MST 0x0010
286#define MDIO_AN_T1_LP_M_B10L 0x4000
287#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000
288#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000289#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000
290#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700291#define MDIO_PMA_PMD_BT1_CTRL_STRAP 0x000F
292#define MDIO_PMA_PMD_BT1_CTRL_STRAP_B1000 0x0001
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700293#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700294#define MDIO_PCS_1000BT1_CTRL_LOW_POWER 0x0800
295#define MDIO_PCS_1000BT1_CTRL_DISABLE_TX 0x4000
296#define MDIO_PCS_1000BT1_CTRL_RESET 0x8000
297#define MDIO_PCS_1000BT1_STAT_LINK 0x0004
298#define MDIO_PCS_1000BT1_STAT_FAULT 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700299#define MDIO_AN_EEE_ADV_100TX 0x0002
300#define MDIO_AN_EEE_ADV_1000T 0x0004
301#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX
302#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T
Ben Cheng655a7c02013-10-16 16:09:24 -0700303#define MDIO_EEE_10GT 0x0008
304#define MDIO_EEE_1000KX 0x0010
305#define MDIO_EEE_10GKX4 0x0020
306#define MDIO_EEE_10GKR 0x0040
Christopher Ferris9584fa42019-12-09 15:36:13 -0800307#define MDIO_EEE_40GR_FW 0x0100
308#define MDIO_EEE_40GR_DS 0x0200
309#define MDIO_EEE_100GR_FW 0x1000
310#define MDIO_EEE_100GR_DS 0x2000
311#define MDIO_EEE_2_5GT 0x0001
312#define MDIO_EEE_5GT 0x0002
Christopher Ferrisa4792612022-01-10 13:51:15 -0800313#define MDIO_AN_THP_BP2_5GT 0x0008
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700314#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001
315#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700316#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001
317#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008
318#define MDIO_PMA_LASI_RX_PMALFLT 0x0010
319#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700320#define MDIO_PMA_LASI_RX_WISLFLT 0x0200
321#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001
322#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008
323#define MDIO_PMA_LASI_TX_PMALFLT 0x0010
Ben Cheng655a7c02013-10-16 16:09:24 -0700324#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080
325#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100
326#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200
327#define MDIO_PMA_LASI_LSALARM 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700328#define MDIO_PMA_LASI_TXALARM 0x0002
329#define MDIO_PMA_LASI_RXALARM 0x0004
330#define MDIO_PHY_ID_C45 0x8000
331#define MDIO_PHY_ID_PRTAD 0x03e0
Ben Cheng655a7c02013-10-16 16:09:24 -0700332#define MDIO_PHY_ID_DEVAD 0x001f
Tao Baod7db5942015-01-28 10:07:51 -0800333#define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
Christopher Ferris25c18d42020-10-14 17:42:58 -0700334#define MDIO_USXGMII_EEE_CLK_STP 0x0080
335#define MDIO_USXGMII_EEE 0x0100
336#define MDIO_USXGMII_SPD_MASK 0x0e00
337#define MDIO_USXGMII_FULL_DUPLEX 0x1000
338#define MDIO_USXGMII_DPX_SPD_MASK 0x1e00
339#define MDIO_USXGMII_10 0x0000
340#define MDIO_USXGMII_10HALF 0x0000
341#define MDIO_USXGMII_10FULL 0x1000
342#define MDIO_USXGMII_100 0x0200
343#define MDIO_USXGMII_100HALF 0x0200
344#define MDIO_USXGMII_100FULL 0x1200
345#define MDIO_USXGMII_1000 0x0400
346#define MDIO_USXGMII_1000HALF 0x0400
347#define MDIO_USXGMII_1000FULL 0x1400
348#define MDIO_USXGMII_10G 0x0600
349#define MDIO_USXGMII_10GHALF 0x0600
350#define MDIO_USXGMII_10GFULL 0x1600
351#define MDIO_USXGMII_2500 0x0800
352#define MDIO_USXGMII_2500HALF 0x0800
353#define MDIO_USXGMII_2500FULL 0x1800
354#define MDIO_USXGMII_5000 0x0a00
355#define MDIO_USXGMII_5000HALF 0x0a00
356#define MDIO_USXGMII_5000FULL 0x1a00
357#define MDIO_USXGMII_LINK 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700358#endif