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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI__LINUX_MDIO_H__
20#define _UAPI__LINUX_MDIO_H__
21#include <linux/types.h>
22#include <linux/mii.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070023#define MDIO_MMD_PMAPMD 1
24#define MDIO_MMD_WIS 2
25#define MDIO_MMD_PCS 3
26#define MDIO_MMD_PHYXS 4
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define MDIO_MMD_DTEXS 5
28#define MDIO_MMD_TC 6
29#define MDIO_MMD_AN 7
30#define MDIO_MMD_C22EXT 29
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define MDIO_MMD_VEND1 30
32#define MDIO_MMD_VEND2 31
33#define MDIO_CTRL1 MII_BMCR
34#define MDIO_STAT1 MII_BMSR
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define MDIO_DEVID1 MII_PHYSID1
36#define MDIO_DEVID2 MII_PHYSID2
37#define MDIO_SPEED 4
38#define MDIO_DEVS1 5
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define MDIO_DEVS2 6
40#define MDIO_CTRL2 7
41#define MDIO_STAT2 8
42#define MDIO_PMA_TXDIS 9
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define MDIO_PMA_RXDET 10
44#define MDIO_PMA_EXTABLE 11
45#define MDIO_PKGID1 14
46#define MDIO_PKGID2 15
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define MDIO_AN_ADVERTISE 16
48#define MDIO_AN_LPA 19
49#define MDIO_PCS_EEE_ABLE 20
Christopher Ferris9584fa42019-12-09 15:36:13 -080050#define MDIO_PCS_EEE_ABLE2 21
Christopher Ferris24f97eb2019-05-20 12:58:13 -070051#define MDIO_PMA_NG_EXTABLE 21
Ben Cheng655a7c02013-10-16 16:09:24 -070052#define MDIO_PCS_EEE_WK_ERR 22
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define MDIO_PHYXS_LNSTAT 24
54#define MDIO_AN_EEE_ADV 60
55#define MDIO_AN_EEE_LPABLE 61
Christopher Ferris9584fa42019-12-09 15:36:13 -080056#define MDIO_AN_EEE_ADV2 62
57#define MDIO_AN_EEE_LPABLE2 63
Christopher Ferrisa4792612022-01-10 13:51:15 -080058#define MDIO_AN_CTRL2 64
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define MDIO_PMA_10GBT_SWAPPOL 130
Ben Cheng655a7c02013-10-16 16:09:24 -070060#define MDIO_PMA_10GBT_TXPWR 131
61#define MDIO_PMA_10GBT_SNR 133
Christopher Ferrisa4792612022-01-10 13:51:15 -080062#define MDIO_PMA_10GBR_FSRT_CSR 147
Ben Cheng655a7c02013-10-16 16:09:24 -070063#define MDIO_PMA_10GBR_FECABLE 170
64#define MDIO_PCS_10GBX_STAT1 24
Ben Cheng655a7c02013-10-16 16:09:24 -070065#define MDIO_PCS_10GBRT_STAT1 32
66#define MDIO_PCS_10GBRT_STAT2 33
67#define MDIO_AN_10GBT_CTRL 32
68#define MDIO_AN_10GBT_STAT 33
Christopher Ferris80ae69d2022-08-02 16:32:21 -070069#define MDIO_B10L_PMA_CTRL 2294
70#define MDIO_PMA_10T1L_STAT 2295
71#define MDIO_PCS_10T1L_CTRL 2278
72#define MDIO_PMA_PMD_BT1 18
73#define MDIO_AN_T1_CTRL 512
74#define MDIO_AN_T1_STAT 513
75#define MDIO_AN_T1_ADV_L 514
76#define MDIO_AN_T1_ADV_M 515
77#define MDIO_AN_T1_ADV_H 516
78#define MDIO_AN_T1_LP_L 517
79#define MDIO_AN_T1_LP_M 518
80#define MDIO_AN_T1_LP_H 519
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +000081#define MDIO_AN_10BT1_AN_CTRL 526
82#define MDIO_AN_10BT1_AN_STAT 527
Christopher Ferris80ae69d2022-08-02 16:32:21 -070083#define MDIO_PMA_PMD_BT1_CTRL 2100
Ben Cheng655a7c02013-10-16 16:09:24 -070084#define MDIO_PMA_LASI_RXCTRL 0x9000
85#define MDIO_PMA_LASI_TXCTRL 0x9001
86#define MDIO_PMA_LASI_CTRL 0x9002
87#define MDIO_PMA_LASI_RXSTAT 0x9003
Ben Cheng655a7c02013-10-16 16:09:24 -070088#define MDIO_PMA_LASI_TXSTAT 0x9004
89#define MDIO_PMA_LASI_STAT 0x9005
90#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
91#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
Ben Cheng655a7c02013-10-16 16:09:24 -070092#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
93#define MDIO_CTRL1_LPOWER BMCR_PDOWN
94#define MDIO_CTRL1_RESET BMCR_RESET
95#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -070096#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
97#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
98#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
99#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
Ben Cheng655a7c02013-10-16 16:09:24 -0700100#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
101#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
102#define MDIO_AN_CTRL1_XNP 0x2000
103#define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400
Ben Cheng655a7c02013-10-16 16:09:24 -0700104#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
105#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700106#define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18)
107#define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c)
Ben Cheng655a7c02013-10-16 16:09:24 -0700108#define MDIO_STAT1_LPOWERABLE 0x0002
109#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
Ben Cheng655a7c02013-10-16 16:09:24 -0700110#define MDIO_STAT1_FAULT 0x0080
111#define MDIO_AN_STAT1_LPABLE 0x0001
112#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
113#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
Ben Cheng655a7c02013-10-16 16:09:24 -0700114#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
115#define MDIO_AN_STAT1_PAGE 0x0040
116#define MDIO_AN_STAT1_XNP 0x0080
117#define MDIO_SPEED_10G 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700118#define MDIO_PMA_SPEED_2B 0x0002
119#define MDIO_PMA_SPEED_10P 0x0004
120#define MDIO_PMA_SPEED_1000 0x0010
121#define MDIO_PMA_SPEED_100 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700122#define MDIO_PMA_SPEED_10 0x0040
123#define MDIO_PCS_SPEED_10P2B 0x0002
Christopher Ferrisfcc3b4f2021-07-01 01:30:21 +0000124#define MDIO_PCS_SPEED_2_5G 0x0040
125#define MDIO_PCS_SPEED_5G 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700126#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700127#define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700128#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
Ben Cheng655a7c02013-10-16 16:09:24 -0700129#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
130#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
131#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
132#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
Ben Cheng655a7c02013-10-16 16:09:24 -0700133#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
134#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
135#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700136#define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1)
137#define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700138#define MDIO_PMA_CTRL2_TYPE 0x000f
Ben Cheng655a7c02013-10-16 16:09:24 -0700139#define MDIO_PMA_CTRL2_10GBCX4 0x0000
140#define MDIO_PMA_CTRL2_10GBEW 0x0001
141#define MDIO_PMA_CTRL2_10GBLW 0x0002
142#define MDIO_PMA_CTRL2_10GBSW 0x0003
Ben Cheng655a7c02013-10-16 16:09:24 -0700143#define MDIO_PMA_CTRL2_10GBLX4 0x0004
144#define MDIO_PMA_CTRL2_10GBER 0x0005
145#define MDIO_PMA_CTRL2_10GBLR 0x0006
146#define MDIO_PMA_CTRL2_10GBSR 0x0007
Ben Cheng655a7c02013-10-16 16:09:24 -0700147#define MDIO_PMA_CTRL2_10GBLRM 0x0008
148#define MDIO_PMA_CTRL2_10GBT 0x0009
149#define MDIO_PMA_CTRL2_10GBKX4 0x000a
150#define MDIO_PMA_CTRL2_10GBKR 0x000b
Ben Cheng655a7c02013-10-16 16:09:24 -0700151#define MDIO_PMA_CTRL2_1000BT 0x000c
152#define MDIO_PMA_CTRL2_1000BKX 0x000d
153#define MDIO_PMA_CTRL2_100BTX 0x000e
154#define MDIO_PMA_CTRL2_10BT 0x000f
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700155#define MDIO_PMA_CTRL2_2_5GBT 0x0030
156#define MDIO_PMA_CTRL2_5GBT 0x0031
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700157#define MDIO_PMA_CTRL2_BASET1 0x003D
Ben Cheng655a7c02013-10-16 16:09:24 -0700158#define MDIO_PCS_CTRL2_TYPE 0x0003
159#define MDIO_PCS_CTRL2_10GBR 0x0000
160#define MDIO_PCS_CTRL2_10GBX 0x0001
161#define MDIO_PCS_CTRL2_10GBW 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700162#define MDIO_PCS_CTRL2_10GBT 0x0003
163#define MDIO_STAT2_RXFAULT 0x0400
164#define MDIO_STAT2_TXFAULT 0x0800
165#define MDIO_STAT2_DEVPRST 0xc000
Ben Cheng655a7c02013-10-16 16:09:24 -0700166#define MDIO_STAT2_DEVPRST_VAL 0x8000
167#define MDIO_PMA_STAT2_LBABLE 0x0001
168#define MDIO_PMA_STAT2_10GBEW 0x0002
169#define MDIO_PMA_STAT2_10GBLW 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700170#define MDIO_PMA_STAT2_10GBSW 0x0008
171#define MDIO_PMA_STAT2_10GBLX4 0x0010
172#define MDIO_PMA_STAT2_10GBER 0x0020
173#define MDIO_PMA_STAT2_10GBLR 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700174#define MDIO_PMA_STAT2_10GBSR 0x0080
175#define MDIO_PMD_STAT2_TXDISAB 0x0100
176#define MDIO_PMA_STAT2_EXTABLE 0x0200
177#define MDIO_PMA_STAT2_RXFLTABLE 0x1000
Ben Cheng655a7c02013-10-16 16:09:24 -0700178#define MDIO_PMA_STAT2_TXFLTABLE 0x2000
179#define MDIO_PCS_STAT2_10GBR 0x0001
180#define MDIO_PCS_STAT2_10GBX 0x0002
181#define MDIO_PCS_STAT2_10GBW 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700182#define MDIO_PCS_STAT2_RXFLTABLE 0x1000
183#define MDIO_PCS_STAT2_TXFLTABLE 0x2000
184#define MDIO_PMD_TXDIS_GLOBAL 0x0001
185#define MDIO_PMD_TXDIS_0 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700186#define MDIO_PMD_TXDIS_1 0x0004
187#define MDIO_PMD_TXDIS_2 0x0008
188#define MDIO_PMD_TXDIS_3 0x0010
189#define MDIO_PMD_RXDET_GLOBAL 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700190#define MDIO_PMD_RXDET_0 0x0002
191#define MDIO_PMD_RXDET_1 0x0004
192#define MDIO_PMD_RXDET_2 0x0008
193#define MDIO_PMD_RXDET_3 0x0010
Ben Cheng655a7c02013-10-16 16:09:24 -0700194#define MDIO_PMA_EXTABLE_10GCX4 0x0001
195#define MDIO_PMA_EXTABLE_10GBLRM 0x0002
196#define MDIO_PMA_EXTABLE_10GBT 0x0004
197#define MDIO_PMA_EXTABLE_10GBKX4 0x0008
Ben Cheng655a7c02013-10-16 16:09:24 -0700198#define MDIO_PMA_EXTABLE_10GBKR 0x0010
199#define MDIO_PMA_EXTABLE_1000BT 0x0020
200#define MDIO_PMA_EXTABLE_1000BKX 0x0040
201#define MDIO_PMA_EXTABLE_100BTX 0x0080
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#define MDIO_PMA_EXTABLE_10BT 0x0100
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700203#define MDIO_PMA_EXTABLE_BT1 0x0800
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700204#define MDIO_PMA_EXTABLE_NBT 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700205#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
206#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
207#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
Ben Cheng655a7c02013-10-16 16:09:24 -0700208#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
209#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
210#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001
211#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700212#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100
213#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200
214#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400
215#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700216#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001
217#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
218#define MDIO_PMA_10GBT_SNR_MAX 127
219#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
Christopher Ferrisa4792612022-01-10 13:51:15 -0800221#define MDIO_PMA_10GBR_FSRT_ENABLE 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700222#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001
223#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
224#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
Christopher Ferrisa4792612022-01-10 13:51:15 -0800225#define MDIO_AN_10GBT_CTRL_ADVFSRT2_5G 0x0020
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700226#define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080
227#define MDIO_AN_10GBT_CTRL_ADV5G 0x0100
Ben Cheng655a7c02013-10-16 16:09:24 -0700228#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700229#define MDIO_AN_10GBT_STAT_LP2_5G 0x0020
230#define MDIO_AN_10GBT_STAT_LP5G 0x0040
Ben Cheng655a7c02013-10-16 16:09:24 -0700231#define MDIO_AN_10GBT_STAT_LPTRR 0x0200
232#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400
233#define MDIO_AN_10GBT_STAT_LP10G 0x0800
Ben Cheng655a7c02013-10-16 16:09:24 -0700234#define MDIO_AN_10GBT_STAT_REMOK 0x1000
235#define MDIO_AN_10GBT_STAT_LOCOK 0x2000
236#define MDIO_AN_10GBT_STAT_MS 0x4000
237#define MDIO_AN_10GBT_STAT_MSFLT 0x8000
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700238#define MDIO_PMA_10T1L_CTRL_LB_EN 0x0001
239#define MDIO_PMA_10T1L_CTRL_EEE_EN 0x0400
240#define MDIO_PMA_10T1L_CTRL_LOW_POWER 0x0800
241#define MDIO_PMA_10T1L_CTRL_2V4_EN 0x1000
242#define MDIO_PMA_10T1L_CTRL_TX_DIS 0x4000
243#define MDIO_PMA_10T1L_CTRL_PMA_RST 0x8000
244#define MDIO_PMA_10T1L_STAT_LINK 0x0001
245#define MDIO_PMA_10T1L_STAT_FAULT 0x0002
246#define MDIO_PMA_10T1L_STAT_POLARITY 0x0004
247#define MDIO_PMA_10T1L_STAT_RECV_FAULT 0x0200
248#define MDIO_PMA_10T1L_STAT_EEE 0x0400
249#define MDIO_PMA_10T1L_STAT_LOW_POWER 0x0800
250#define MDIO_PMA_10T1L_STAT_2V4_ABLE 0x1000
251#define MDIO_PMA_10T1L_STAT_LB_ABLE 0x2000
252#define MDIO_PCS_10T1L_CTRL_LB 0x4000
253#define MDIO_PCS_10T1L_CTRL_RESET 0x8000
254#define MDIO_PMA_PMD_BT1_B10L_ABLE 0x0004
255#define MDIO_AN_T1_ADV_L_PAUSE_CAP ADVERTISE_PAUSE_CAP
256#define MDIO_AN_T1_ADV_L_PAUSE_ASYM ADVERTISE_PAUSE_ASYM
257#define MDIO_AN_T1_ADV_L_FORCE_MS 0x1000
258#define MDIO_AN_T1_ADV_L_REMOTE_FAULT ADVERTISE_RFAULT
259#define MDIO_AN_T1_ADV_L_ACK ADVERTISE_LPACK
260#define MDIO_AN_T1_ADV_L_NEXT_PAGE_REQ ADVERTISE_NPAGE
261#define MDIO_AN_T1_ADV_M_B10L 0x4000
262#define MDIO_AN_T1_ADV_M_MST 0x0010
263#define MDIO_AN_T1_ADV_H_10L_TX_HI_REQ 0x1000
264#define MDIO_AN_T1_ADV_H_10L_TX_HI 0x2000
265#define MDIO_AN_T1_LP_L_PAUSE_CAP LPA_PAUSE_CAP
266#define MDIO_AN_T1_LP_L_PAUSE_ASYM LPA_PAUSE_ASYM
267#define MDIO_AN_T1_LP_L_FORCE_MS 0x1000
268#define MDIO_AN_T1_LP_L_REMOTE_FAULT LPA_RFAULT
269#define MDIO_AN_T1_LP_L_ACK LPA_LPACK
270#define MDIO_AN_T1_LP_L_NEXT_PAGE_REQ LPA_NPAGE
271#define MDIO_AN_T1_LP_M_MST 0x0010
272#define MDIO_AN_T1_LP_M_B10L 0x4000
273#define MDIO_AN_T1_LP_H_10L_TX_HI_REQ 0x1000
274#define MDIO_AN_T1_LP_H_10L_TX_HI 0x2000
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +0000275#define MDIO_AN_10BT1_AN_CTRL_ADV_EEE_T1L 0x4000
276#define MDIO_AN_10BT1_AN_STAT_LPA_EEE_T1L 0x4000
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700277#define MDIO_PMA_PMD_BT1_CTRL_CFG_MST 0x4000
Ben Cheng655a7c02013-10-16 16:09:24 -0700278#define MDIO_AN_EEE_ADV_100TX 0x0002
279#define MDIO_AN_EEE_ADV_1000T 0x0004
280#define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX
281#define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T
Ben Cheng655a7c02013-10-16 16:09:24 -0700282#define MDIO_EEE_10GT 0x0008
283#define MDIO_EEE_1000KX 0x0010
284#define MDIO_EEE_10GKX4 0x0020
285#define MDIO_EEE_10GKR 0x0040
Christopher Ferris9584fa42019-12-09 15:36:13 -0800286#define MDIO_EEE_40GR_FW 0x0100
287#define MDIO_EEE_40GR_DS 0x0200
288#define MDIO_EEE_100GR_FW 0x1000
289#define MDIO_EEE_100GR_DS 0x2000
290#define MDIO_EEE_2_5GT 0x0001
291#define MDIO_EEE_5GT 0x0002
Christopher Ferrisa4792612022-01-10 13:51:15 -0800292#define MDIO_AN_THP_BP2_5GT 0x0008
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700293#define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001
294#define MDIO_PMA_NG_EXTABLE_5GBT 0x0002
Ben Cheng655a7c02013-10-16 16:09:24 -0700295#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001
296#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008
297#define MDIO_PMA_LASI_RX_PMALFLT 0x0010
298#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020
Ben Cheng655a7c02013-10-16 16:09:24 -0700299#define MDIO_PMA_LASI_RX_WISLFLT 0x0200
300#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001
301#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008
302#define MDIO_PMA_LASI_TX_PMALFLT 0x0010
Ben Cheng655a7c02013-10-16 16:09:24 -0700303#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080
304#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100
305#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200
306#define MDIO_PMA_LASI_LSALARM 0x0001
Ben Cheng655a7c02013-10-16 16:09:24 -0700307#define MDIO_PMA_LASI_TXALARM 0x0002
308#define MDIO_PMA_LASI_RXALARM 0x0004
309#define MDIO_PHY_ID_C45 0x8000
310#define MDIO_PHY_ID_PRTAD 0x03e0
Ben Cheng655a7c02013-10-16 16:09:24 -0700311#define MDIO_PHY_ID_DEVAD 0x001f
Tao Baod7db5942015-01-28 10:07:51 -0800312#define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
Christopher Ferris25c18d42020-10-14 17:42:58 -0700313#define MDIO_USXGMII_EEE_CLK_STP 0x0080
314#define MDIO_USXGMII_EEE 0x0100
315#define MDIO_USXGMII_SPD_MASK 0x0e00
316#define MDIO_USXGMII_FULL_DUPLEX 0x1000
317#define MDIO_USXGMII_DPX_SPD_MASK 0x1e00
318#define MDIO_USXGMII_10 0x0000
319#define MDIO_USXGMII_10HALF 0x0000
320#define MDIO_USXGMII_10FULL 0x1000
321#define MDIO_USXGMII_100 0x0200
322#define MDIO_USXGMII_100HALF 0x0200
323#define MDIO_USXGMII_100FULL 0x1200
324#define MDIO_USXGMII_1000 0x0400
325#define MDIO_USXGMII_1000HALF 0x0400
326#define MDIO_USXGMII_1000FULL 0x1400
327#define MDIO_USXGMII_10G 0x0600
328#define MDIO_USXGMII_10GHALF 0x0600
329#define MDIO_USXGMII_10GFULL 0x1600
330#define MDIO_USXGMII_2500 0x0800
331#define MDIO_USXGMII_2500HALF 0x0800
332#define MDIO_USXGMII_2500FULL 0x1800
333#define MDIO_USXGMII_5000 0x0a00
334#define MDIO_USXGMII_5000HALF 0x0a00
335#define MDIO_USXGMII_5000FULL 0x1a00
336#define MDIO_USXGMII_LINK 0x8000
Ben Cheng655a7c02013-10-16 16:09:24 -0700337#endif