blob: f07b7437cd88127690edb9b56edfb030446fc870 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef __VMWGFX_DRM_H__
8#define __VMWGFX_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -07009#include "drm.h"
10#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080011extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070012#endif
13#define DRM_VMW_MAX_SURFACE_FACES 6
Christopher Ferris38062f92014-07-09 15:33:25 -070014#define DRM_VMW_MAX_MIP_LEVELS 24
Ben Cheng655a7c02013-10-16 16:09:24 -070015#define DRM_VMW_GET_PARAM 0
16#define DRM_VMW_ALLOC_DMABUF 1
Christopher Ferris9ce28842018-10-25 12:11:39 -070017#define DRM_VMW_ALLOC_BO 1
Ben Cheng655a7c02013-10-16 16:09:24 -070018#define DRM_VMW_UNREF_DMABUF 2
Christopher Ferris525ce912017-07-26 13:12:53 -070019#define DRM_VMW_HANDLE_CLOSE 2
Christopher Ferris38062f92014-07-09 15:33:25 -070020#define DRM_VMW_CURSOR_BYPASS 3
Ben Cheng655a7c02013-10-16 16:09:24 -070021#define DRM_VMW_CONTROL_STREAM 4
22#define DRM_VMW_CLAIM_STREAM 5
23#define DRM_VMW_UNREF_STREAM 6
Christopher Ferris38062f92014-07-09 15:33:25 -070024#define DRM_VMW_CREATE_CONTEXT 7
Ben Cheng655a7c02013-10-16 16:09:24 -070025#define DRM_VMW_UNREF_CONTEXT 8
26#define DRM_VMW_CREATE_SURFACE 9
27#define DRM_VMW_UNREF_SURFACE 10
Christopher Ferris38062f92014-07-09 15:33:25 -070028#define DRM_VMW_REF_SURFACE 11
Ben Cheng655a7c02013-10-16 16:09:24 -070029#define DRM_VMW_EXECBUF 12
30#define DRM_VMW_GET_3D_CAP 13
31#define DRM_VMW_FENCE_WAIT 14
Christopher Ferris38062f92014-07-09 15:33:25 -070032#define DRM_VMW_FENCE_SIGNALED 15
Ben Cheng655a7c02013-10-16 16:09:24 -070033#define DRM_VMW_FENCE_UNREF 16
34#define DRM_VMW_FENCE_EVENT 17
35#define DRM_VMW_PRESENT 18
Christopher Ferris38062f92014-07-09 15:33:25 -070036#define DRM_VMW_PRESENT_READBACK 19
Ben Cheng655a7c02013-10-16 16:09:24 -070037#define DRM_VMW_UPDATE_LAYOUT 20
Christopher Ferris38062f92014-07-09 15:33:25 -070038#define DRM_VMW_CREATE_SHADER 21
39#define DRM_VMW_UNREF_SHADER 22
Christopher Ferris38062f92014-07-09 15:33:25 -070040#define DRM_VMW_GB_SURFACE_CREATE 23
41#define DRM_VMW_GB_SURFACE_REF 24
42#define DRM_VMW_SYNCCPU 25
Christopher Ferris05d08e92016-02-04 13:16:38 -080043#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
Christopher Ferris9ce28842018-10-25 12:11:39 -070044#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
45#define DRM_VMW_GB_SURFACE_REF_EXT 28
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070046#define DRM_VMW_MSG 29
Christopher Ferris2abfa9e2021-11-01 16:26:06 -070047#define DRM_VMW_MKSSTAT_RESET 30
48#define DRM_VMW_MKSSTAT_ADD 31
49#define DRM_VMW_MKSSTAT_REMOVE 32
Christopher Ferris05d08e92016-02-04 13:16:38 -080050#define DRM_VMW_PARAM_NUM_STREAMS 0
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
52#define DRM_VMW_PARAM_3D 2
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define DRM_VMW_PARAM_HW_CAPS 3
Christopher Ferris05d08e92016-02-04 13:16:38 -080054#define DRM_VMW_PARAM_FIFO_CAPS 4
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define DRM_VMW_PARAM_MAX_FB_SIZE 5
56#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
Christopher Ferris38062f92014-07-09 15:33:25 -070057#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
Christopher Ferris05d08e92016-02-04 13:16:38 -080058#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
Christopher Ferris38062f92014-07-09 15:33:25 -070059#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
60#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
Christopher Ferris05d08e92016-02-04 13:16:38 -080061#define DRM_VMW_PARAM_SCREEN_TARGET 11
Christopher Ferris05d08e92016-02-04 13:16:38 -080062#define DRM_VMW_PARAM_DX 12
Christopher Ferris9ce28842018-10-25 12:11:39 -070063#define DRM_VMW_PARAM_HW_CAPS2 13
64#define DRM_VMW_PARAM_SM4_1 14
Christopher Ferrisaf09c702020-06-01 20:29:29 -070065#define DRM_VMW_PARAM_SM5 15
Christopher Ferris1ed55342022-03-22 16:06:25 -070066#define DRM_VMW_PARAM_GL43 16
Christopher Ferris80ae69d2022-08-02 16:32:21 -070067#define DRM_VMW_PARAM_DEVICE_ID 17
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070068enum drm_vmw_handle_type {
Tao Baod7db5942015-01-28 10:07:51 -080069 DRM_VMW_HANDLE_LEGACY = 0,
Tao Baod7db5942015-01-28 10:07:51 -080070 DRM_VMW_HANDLE_PRIME = 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070071};
Ben Cheng655a7c02013-10-16 16:09:24 -070072struct drm_vmw_getparam_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070073 __u64 value;
74 __u32 param;
75 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070076};
77struct drm_vmw_context_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __s32 cid;
79 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070080};
81struct drm_vmw_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -070082 __u32 flags;
83 __u32 format;
84 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
Christopher Ferris106b3a82016-08-24 12:15:38 -070085 __u64 size_addr;
86 __s32 shareable;
87 __s32 scanout;
Ben Cheng655a7c02013-10-16 16:09:24 -070088};
Christopher Ferris106b3a82016-08-24 12:15:38 -070089struct drm_vmw_surface_arg {
90 __s32 sid;
Tao Baod7db5942015-01-28 10:07:51 -080091 enum drm_vmw_handle_type handle_type;
Ben Cheng655a7c02013-10-16 16:09:24 -070092};
93struct drm_vmw_size {
Christopher Ferris106b3a82016-08-24 12:15:38 -070094 __u32 width;
95 __u32 height;
96 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -070097 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070098};
99union drm_vmw_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800100 struct drm_vmw_surface_arg rep;
101 struct drm_vmw_surface_create_req req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
103union drm_vmw_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800104 struct drm_vmw_surface_create_req rep;
105 struct drm_vmw_surface_arg req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700106};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800107#define DRM_VMW_EXECBUF_VERSION 2
Christopher Ferris1308ad32017-11-14 17:32:13 -0800108#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
109#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700110struct drm_vmw_execbuf_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700111 __u64 commands;
112 __u32 command_size;
113 __u32 throttle_us;
114 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700115 __u32 version;
116 __u32 flags;
117 __u32 context_handle;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800118 __s32 imported_fence_fd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700119};
Ben Cheng655a7c02013-10-16 16:09:24 -0700120struct drm_vmw_fence_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700121 __u32 handle;
122 __u32 mask;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123 __u32 seqno;
124 __u32 passed_seqno;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800125 __s32 fd;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700126 __s32 error;
Ben Cheng655a7c02013-10-16 16:09:24 -0700127};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700128struct drm_vmw_alloc_bo_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700129 __u32 size;
130 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700131};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700132#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
133struct drm_vmw_bo_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700134 __u64 map_handle;
135 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700136 __u32 cur_gmr_id;
137 __u32 cur_gmr_offset;
138 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700139};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700140#define drm_vmw_dmabuf_rep drm_vmw_bo_rep
141union drm_vmw_alloc_bo_arg {
142 struct drm_vmw_alloc_bo_req req;
143 struct drm_vmw_bo_rep rep;
Ben Cheng655a7c02013-10-16 16:09:24 -0700144};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700145#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
Ben Cheng655a7c02013-10-16 16:09:24 -0700146struct drm_vmw_rect {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147 __s32 x;
148 __s32 y;
149 __u32 w;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700150 __u32 h;
Ben Cheng655a7c02013-10-16 16:09:24 -0700151};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800152struct drm_vmw_control_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700153 __u32 stream_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700154 __u32 enabled;
155 __u32 flags;
156 __u32 color_key;
157 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700158 __u32 offset;
159 __s32 format;
160 __u32 size;
161 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700162 __u32 height;
163 __u32 pitch[3];
164 __u32 pad64;
Tao Baod7db5942015-01-28 10:07:51 -0800165 struct drm_vmw_rect src;
166 struct drm_vmw_rect dst;
Ben Cheng655a7c02013-10-16 16:09:24 -0700167};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800168#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700169#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
170struct drm_vmw_cursor_bypass_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700171 __u32 flags;
172 __u32 crtc_id;
173 __s32 xpos;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700174 __s32 ypos;
175 __s32 xhot;
176 __s32 yhot;
Ben Cheng655a7c02013-10-16 16:09:24 -0700177};
178struct drm_vmw_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700179 __u32 stream_id;
180 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700181};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700182struct drm_vmw_get_3d_cap_arg {
183 __u64 buffer;
184 __u32 max_size;
185 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700186};
Ben Cheng655a7c02013-10-16 16:09:24 -0700187#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800188#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700189#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
190struct drm_vmw_fence_wait_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700191 __u32 handle;
192 __s32 cookie_valid;
193 __u64 kernel_cookie;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700194 __u64 timeout_us;
195 __s32 lazy;
196 __s32 flags;
197 __s32 wait_options;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700198 __s32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700199};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800200struct drm_vmw_fence_signaled_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700201 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700202 __u32 flags;
203 __s32 signaled;
204 __u32 passed_seqno;
205 __u32 signaled_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700206 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700207};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800208struct drm_vmw_fence_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700209 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700210 __u32 pad64;
211};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800212#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700213struct drm_vmw_event_fence {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700214 struct drm_event base;
215 __u64 user_data;
216 __u32 tv_sec;
217 __u32 tv_usec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700218};
Ben Cheng655a7c02013-10-16 16:09:24 -0700219#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800220struct drm_vmw_fence_event_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700221 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700222 __u64 user_data;
223 __u32 handle;
224 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700225};
226struct drm_vmw_present_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700227 __u32 fb_id;
228 __u32 sid;
229 __s32 dest_x;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700230 __s32 dest_y;
231 __u64 clips_ptr;
232 __u32 num_clips;
233 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700234};
Ben Cheng655a7c02013-10-16 16:09:24 -0700235struct drm_vmw_present_readback_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700236 __u32 fb_id;
237 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700238 __u64 clips_ptr;
239 __u64 fence_rep;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800240};
Ben Cheng655a7c02013-10-16 16:09:24 -0700241struct drm_vmw_update_layout_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700242 __u32 num_outputs;
243 __u32 pad64;
244 __u64 rects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700245};
246enum drm_vmw_shader_type {
Tao Baod7db5942015-01-28 10:07:51 -0800247 drm_vmw_shader_type_vs = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800248 drm_vmw_shader_type_ps,
Christopher Ferris38062f92014-07-09 15:33:25 -0700249};
250struct drm_vmw_shader_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800251 enum drm_vmw_shader_type shader_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700252 __u32 size;
253 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700254 __u32 shader_handle;
255 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700256};
257struct drm_vmw_shader_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700258 __u32 handle;
259 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700260};
261enum drm_vmw_surface_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800262 drm_vmw_surface_flag_shareable = (1 << 0),
263 drm_vmw_surface_flag_scanout = (1 << 1),
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800264 drm_vmw_surface_flag_create_buffer = (1 << 2),
265 drm_vmw_surface_flag_coherent = (1 << 3),
Christopher Ferris38062f92014-07-09 15:33:25 -0700266};
267struct drm_vmw_gb_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700268 __u32 svga3d_flags;
269 __u32 format;
270 __u32 mip_levels;
Tao Baod7db5942015-01-28 10:07:51 -0800271 enum drm_vmw_surface_flags drm_surface_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700272 __u32 multisample_count;
273 __u32 autogen_filter;
274 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700275 __u32 array_size;
Tao Baod7db5942015-01-28 10:07:51 -0800276 struct drm_vmw_size base_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700277};
278struct drm_vmw_gb_surface_create_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700279 __u32 handle;
280 __u32 backup_size;
281 __u32 buffer_handle;
282 __u32 buffer_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700283 __u64 buffer_map_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700284};
Christopher Ferris38062f92014-07-09 15:33:25 -0700285union drm_vmw_gb_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800286 struct drm_vmw_gb_surface_create_rep rep;
287 struct drm_vmw_gb_surface_create_req req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700288};
Christopher Ferris38062f92014-07-09 15:33:25 -0700289struct drm_vmw_gb_surface_ref_rep {
Tao Baod7db5942015-01-28 10:07:51 -0800290 struct drm_vmw_gb_surface_create_req creq;
291 struct drm_vmw_gb_surface_create_rep crep;
Christopher Ferris38062f92014-07-09 15:33:25 -0700292};
Christopher Ferris38062f92014-07-09 15:33:25 -0700293union drm_vmw_gb_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800294 struct drm_vmw_gb_surface_ref_rep rep;
295 struct drm_vmw_surface_arg req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700296};
Christopher Ferris38062f92014-07-09 15:33:25 -0700297enum drm_vmw_synccpu_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800298 drm_vmw_synccpu_read = (1 << 0),
299 drm_vmw_synccpu_write = (1 << 1),
300 drm_vmw_synccpu_dontblock = (1 << 2),
Tao Baod7db5942015-01-28 10:07:51 -0800301 drm_vmw_synccpu_allow_cs = (1 << 3)
Christopher Ferris38062f92014-07-09 15:33:25 -0700302};
303enum drm_vmw_synccpu_op {
Tao Baod7db5942015-01-28 10:07:51 -0800304 drm_vmw_synccpu_grab,
Tao Baod7db5942015-01-28 10:07:51 -0800305 drm_vmw_synccpu_release
Christopher Ferris38062f92014-07-09 15:33:25 -0700306};
307struct drm_vmw_synccpu_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800308 enum drm_vmw_synccpu_op op;
Tao Baod7db5942015-01-28 10:07:51 -0800309 enum drm_vmw_synccpu_flags flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700310 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700311 __u32 pad64;
312};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800313enum drm_vmw_extended_context {
314 drm_vmw_context_legacy,
315 drm_vmw_context_dx
316};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800317union drm_vmw_extended_context_arg {
318 enum drm_vmw_extended_context req;
319 struct drm_vmw_context_arg rep;
320};
Christopher Ferris525ce912017-07-26 13:12:53 -0700321struct drm_vmw_handle_close_arg {
322 __u32 handle;
323 __u32 pad64;
324};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700325#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
326enum drm_vmw_surface_version {
Christopher Ferrisaf09c702020-06-01 20:29:29 -0700327 drm_vmw_gb_surface_v1,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700328};
329struct drm_vmw_gb_surface_create_ext_req {
330 struct drm_vmw_gb_surface_create_req base;
331 enum drm_vmw_surface_version version;
Christopher Ferrisaf09c702020-06-01 20:29:29 -0700332 __u32 svga3d_flags_upper_32_bits;
333 __u32 multisample_pattern;
334 __u32 quality_level;
335 __u32 buffer_byte_stride;
336 __u32 must_be_zero;
Christopher Ferris9ce28842018-10-25 12:11:39 -0700337};
338union drm_vmw_gb_surface_create_ext_arg {
339 struct drm_vmw_gb_surface_create_rep rep;
340 struct drm_vmw_gb_surface_create_ext_req req;
341};
342struct drm_vmw_gb_surface_ref_ext_rep {
343 struct drm_vmw_gb_surface_create_ext_req creq;
344 struct drm_vmw_gb_surface_create_rep crep;
345};
346union drm_vmw_gb_surface_reference_ext_arg {
347 struct drm_vmw_gb_surface_ref_ext_rep rep;
348 struct drm_vmw_surface_arg req;
349};
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700350struct drm_vmw_msg_arg {
351 __u64 send;
352 __u64 receive;
353 __s32 send_only;
354 __u32 receive_len;
355};
Christopher Ferris2abfa9e2021-11-01 16:26:06 -0700356struct drm_vmw_mksstat_add_arg {
357 __u64 stat;
358 __u64 info;
359 __u64 strs;
360 __u64 stat_len;
361 __u64 info_len;
362 __u64 strs_len;
363 __u64 description;
364 __u64 id;
365};
366struct drm_vmw_mksstat_remove_arg {
367 __u64 id;
368};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700369#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800370}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700371#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700372#endif