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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / vmwgfx_drm.h
blob: ead603454b2117ae42d6dd9b839d9a1967d90880 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMWGFX_DRM_H__
20#define __VMWGFX_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
25#define DRM_VMW_MAX_SURFACE_FACES 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]26#define DRM_VMW_MAX_MIP_LEVELS 24
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define DRM_VMW_GET_PARAM 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]29#define DRM_VMW_ALLOC_DMABUF 1
30#define DRM_VMW_UNREF_DMABUF 2
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]31#define DRM_VMW_CURSOR_BYPASS 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32#define DRM_VMW_CONTROL_STREAM 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define DRM_VMW_CLAIM_STREAM 5
35#define DRM_VMW_UNREF_STREAM 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]36#define DRM_VMW_CREATE_CONTEXT 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37#define DRM_VMW_UNREF_CONTEXT 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define DRM_VMW_CREATE_SURFACE 9
40#define DRM_VMW_UNREF_SURFACE 10
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]41#define DRM_VMW_REF_SURFACE 11
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]42#define DRM_VMW_EXECBUF 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44#define DRM_VMW_GET_3D_CAP 13
45#define DRM_VMW_FENCE_WAIT 14
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]46#define DRM_VMW_FENCE_SIGNALED 15
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47#define DRM_VMW_FENCE_UNREF 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define DRM_VMW_FENCE_EVENT 17
50#define DRM_VMW_PRESENT 18
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]51#define DRM_VMW_PRESENT_READBACK 19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]52#define DRM_VMW_UPDATE_LAYOUT 20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]54#define DRM_VMW_CREATE_SHADER 21
55#define DRM_VMW_UNREF_SHADER 22
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]56#define DRM_VMW_GB_SURFACE_CREATE 23
57#define DRM_VMW_GB_SURFACE_REF 24
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]59#define DRM_VMW_SYNCCPU 25
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]60#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]61#define DRM_VMW_PARAM_NUM_STREAMS 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]62#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#define DRM_VMW_PARAM_3D 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65#define DRM_VMW_PARAM_HW_CAPS 3
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]66#define DRM_VMW_PARAM_FIFO_CAPS 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]67#define DRM_VMW_PARAM_MAX_FB_SIZE 5
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]70#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]71#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]72#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]74#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]75#define DRM_VMW_PARAM_SCREEN_TARGET 11
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]76#define DRM_VMW_PARAM_DX 12
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]77enum drm_vmw_handle_type {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 DRM_VMW_HANDLE_LEGACY = 0,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]80 DRM_VMW_HANDLE_PRIME = 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700[diff] [blame]81};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82struct drm_vmw_getparam_arg {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]84 __u64 value;
85 __u32 param;
86 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89struct drm_vmw_context_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]90 __s32 cid;
91 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94struct drm_vmw_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]95 __u32 flags;
96 __u32 format;
97 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]99 __u64 size_addr;
100 __s32 shareable;
101 __s32 scanout;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]102};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]104struct drm_vmw_surface_arg {
105 __s32 sid;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]106 enum drm_vmw_handle_type handle_type;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109struct drm_vmw_size {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]110 __u32 width;
111 __u32 height;
112 __u32 depth;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]114 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115};
116union drm_vmw_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 struct drm_vmw_surface_arg rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 struct drm_vmw_surface_create_req req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]120};
121union drm_vmw_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]122 struct drm_vmw_surface_create_req rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]124 struct drm_vmw_surface_arg req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]125};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]126#define DRM_VMW_EXECBUF_VERSION 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127struct drm_vmw_execbuf_arg {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]129 __u64 commands;
130 __u32 command_size;
131 __u32 throttle_us;
132 __u64 fence_rep;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]134 __u32 version;
135 __u32 flags;
136 __u32 context_handle;
137 __u32 pad64;
138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]139};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]140struct drm_vmw_fence_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]141 __u32 handle;
142 __u32 mask;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]144 __u32 seqno;
145 __u32 passed_seqno;
146 __u32 pad64;
147 __s32 error;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]149};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150struct drm_vmw_alloc_dmabuf_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]151 __u32 size;
152 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]155struct drm_vmw_dmabuf_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]156 __u64 map_handle;
157 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]159 __u32 cur_gmr_id;
160 __u32 cur_gmr_offset;
161 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]162};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]164union drm_vmw_alloc_dmabuf_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 struct drm_vmw_alloc_dmabuf_req req;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]166 struct drm_vmw_dmabuf_rep rep;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]167};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169struct drm_vmw_unref_dmabuf_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]170 __u32 handle;
171 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174struct drm_vmw_rect {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]175 __s32 x;
176 __s32 y;
177 __u32 w;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]179 __u32 h;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]181struct drm_vmw_control_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]182 __u32 stream_id;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]184 __u32 enabled;
185 __u32 flags;
186 __u32 color_key;
187 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]189 __u32 offset;
190 __s32 format;
191 __u32 size;
192 __u32 width;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]194 __u32 height;
195 __u32 pitch[3];
196 __u32 pad64;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]197 struct drm_vmw_rect src;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]199 struct drm_vmw_rect dst;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]200};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]201#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]202#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]204struct drm_vmw_cursor_bypass_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]205 __u32 flags;
206 __u32 crtc_id;
207 __s32 xpos;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]209 __s32 ypos;
210 __s32 xhot;
211 __s32 yhot;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]212};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214struct drm_vmw_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]215 __u32 stream_id;
216 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]217};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]219struct drm_vmw_get_3d_cap_arg {
220 __u64 buffer;
221 __u32 max_size;
222 __u32 pad64;
223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]224};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]225#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]226#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]227#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]229struct drm_vmw_fence_wait_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]230 __u32 handle;
231 __s32 cookie_valid;
232 __u64 kernel_cookie;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]234 __u64 timeout_us;
235 __s32 lazy;
236 __s32 flags;
237 __s32 wait_options;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]239 __s32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]240};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]241struct drm_vmw_fence_signaled_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]242 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]244 __u32 flags;
245 __s32 signaled;
246 __u32 passed_seqno;
247 __u32 signaled_flags;
248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
249 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]250};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]251struct drm_vmw_fence_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]252 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]254 __u32 pad64;
255};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]256#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]257struct drm_vmw_event_fence {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]259 struct drm_event base;
260 __u64 user_data;
261 __u32 tv_sec;
262 __u32 tv_usec;
263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]265#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]266struct drm_vmw_fence_event_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]267 __u64 fence_rep;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]269 __u64 user_data;
270 __u32 handle;
271 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]272};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]273/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]274struct drm_vmw_present_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]275 __u32 fb_id;
276 __u32 sid;
277 __s32 dest_x;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]278/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]279 __s32 dest_y;
280 __u64 clips_ptr;
281 __u32 num_clips;
282 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]283/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]284};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]285struct drm_vmw_present_readback_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]286 __u32 fb_id;
287 __u32 num_clips;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]288/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]289 __u64 clips_ptr;
290 __u64 fence_rep;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]291};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]292struct drm_vmw_update_layout_arg {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]293/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]294 __u32 num_outputs;
295 __u32 pad64;
296 __u64 rects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]297};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]298/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]299enum drm_vmw_shader_type {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]300 drm_vmw_shader_type_vs = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]301 drm_vmw_shader_type_ps,
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]302};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]303/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]304struct drm_vmw_shader_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]305 enum drm_vmw_shader_type shader_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]306 __u32 size;
307 __u32 buffer_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]308/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]309 __u32 shader_handle;
310 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]311};
312struct drm_vmw_shader_arg {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]313/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]314 __u32 handle;
315 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]316};
317enum drm_vmw_surface_flags {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]318/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]319 drm_vmw_surface_flag_shareable = (1 << 0),
320 drm_vmw_surface_flag_scanout = (1 << 1),
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]321 drm_vmw_surface_flag_create_buffer = (1 << 2)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]322};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]323/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]324struct drm_vmw_gb_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]325 __u32 svga3d_flags;
326 __u32 format;
327 __u32 mip_levels;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]328/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]329 enum drm_vmw_surface_flags drm_surface_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]330 __u32 multisample_count;
331 __u32 autogen_filter;
332 __u32 buffer_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]333/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]334 __u32 array_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]335 struct drm_vmw_size base_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]336};
337struct drm_vmw_gb_surface_create_rep {
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]338/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]339 __u32 handle;
340 __u32 backup_size;
341 __u32 buffer_handle;
342 __u32 buffer_size;
343/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
344 __u64 buffer_map_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]345};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]346union drm_vmw_gb_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]347 struct drm_vmw_gb_surface_create_rep rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]348/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]349 struct drm_vmw_gb_surface_create_req req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]350};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]351struct drm_vmw_gb_surface_ref_rep {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]352 struct drm_vmw_gb_surface_create_req creq;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]353/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]354 struct drm_vmw_gb_surface_create_rep crep;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]355};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]356union drm_vmw_gb_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]357 struct drm_vmw_gb_surface_ref_rep rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]358/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]359 struct drm_vmw_surface_arg req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]360};
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]361enum drm_vmw_synccpu_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]362 drm_vmw_synccpu_read = (1 << 0),
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]363/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]364 drm_vmw_synccpu_write = (1 << 1),
365 drm_vmw_synccpu_dontblock = (1 << 2),
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]366 drm_vmw_synccpu_allow_cs = (1 << 3)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]367};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]368/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]369enum drm_vmw_synccpu_op {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]370 drm_vmw_synccpu_grab,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]371 drm_vmw_synccpu_release
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]372};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]373/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]374struct drm_vmw_synccpu_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]375 enum drm_vmw_synccpu_op op;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]376 enum drm_vmw_synccpu_flags flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]377 __u32 handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]378/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]379 __u32 pad64;
380};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]381enum drm_vmw_extended_context {
382 drm_vmw_context_legacy,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]383/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]384 drm_vmw_context_dx
385};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]386union drm_vmw_extended_context_arg {
387 enum drm_vmw_extended_context req;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]388/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]389 struct drm_vmw_context_arg rep;
390};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]391#ifdef __cplusplus
392#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]393/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]394#endif