blob: 04d30810a4b252bd77594fbbe176f17428dfa4aa [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __VMWGFX_DRM_H__
20#define __VMWGFX_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#define DRM_VMW_MAX_SURFACE_FACES 6
Christopher Ferris38062f92014-07-09 15:33:25 -070026#define DRM_VMW_MAX_MIP_LEVELS 24
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define DRM_VMW_GET_PARAM 0
28#define DRM_VMW_ALLOC_DMABUF 1
Christopher Ferris9ce28842018-10-25 12:11:39 -070029#define DRM_VMW_ALLOC_BO 1
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define DRM_VMW_UNREF_DMABUF 2
Christopher Ferris525ce912017-07-26 13:12:53 -070031#define DRM_VMW_HANDLE_CLOSE 2
Christopher Ferris38062f92014-07-09 15:33:25 -070032#define DRM_VMW_CURSOR_BYPASS 3
Ben Cheng655a7c02013-10-16 16:09:24 -070033#define DRM_VMW_CONTROL_STREAM 4
34#define DRM_VMW_CLAIM_STREAM 5
35#define DRM_VMW_UNREF_STREAM 6
Christopher Ferris38062f92014-07-09 15:33:25 -070036#define DRM_VMW_CREATE_CONTEXT 7
Ben Cheng655a7c02013-10-16 16:09:24 -070037#define DRM_VMW_UNREF_CONTEXT 8
38#define DRM_VMW_CREATE_SURFACE 9
39#define DRM_VMW_UNREF_SURFACE 10
Christopher Ferris38062f92014-07-09 15:33:25 -070040#define DRM_VMW_REF_SURFACE 11
Ben Cheng655a7c02013-10-16 16:09:24 -070041#define DRM_VMW_EXECBUF 12
42#define DRM_VMW_GET_3D_CAP 13
43#define DRM_VMW_FENCE_WAIT 14
Christopher Ferris38062f92014-07-09 15:33:25 -070044#define DRM_VMW_FENCE_SIGNALED 15
Ben Cheng655a7c02013-10-16 16:09:24 -070045#define DRM_VMW_FENCE_UNREF 16
46#define DRM_VMW_FENCE_EVENT 17
47#define DRM_VMW_PRESENT 18
Christopher Ferris38062f92014-07-09 15:33:25 -070048#define DRM_VMW_PRESENT_READBACK 19
Ben Cheng655a7c02013-10-16 16:09:24 -070049#define DRM_VMW_UPDATE_LAYOUT 20
Christopher Ferris38062f92014-07-09 15:33:25 -070050#define DRM_VMW_CREATE_SHADER 21
51#define DRM_VMW_UNREF_SHADER 22
Christopher Ferris38062f92014-07-09 15:33:25 -070052#define DRM_VMW_GB_SURFACE_CREATE 23
53#define DRM_VMW_GB_SURFACE_REF 24
54#define DRM_VMW_SYNCCPU 25
Christopher Ferris05d08e92016-02-04 13:16:38 -080055#define DRM_VMW_CREATE_EXTENDED_CONTEXT 26
Christopher Ferris9ce28842018-10-25 12:11:39 -070056#define DRM_VMW_GB_SURFACE_CREATE_EXT 27
57#define DRM_VMW_GB_SURFACE_REF_EXT 28
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070058#define DRM_VMW_MSG 29
Christopher Ferris05d08e92016-02-04 13:16:38 -080059#define DRM_VMW_PARAM_NUM_STREAMS 0
Ben Cheng655a7c02013-10-16 16:09:24 -070060#define DRM_VMW_PARAM_NUM_FREE_STREAMS 1
61#define DRM_VMW_PARAM_3D 2
Ben Cheng655a7c02013-10-16 16:09:24 -070062#define DRM_VMW_PARAM_HW_CAPS 3
Christopher Ferris05d08e92016-02-04 13:16:38 -080063#define DRM_VMW_PARAM_FIFO_CAPS 4
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define DRM_VMW_PARAM_MAX_FB_SIZE 5
65#define DRM_VMW_PARAM_FIFO_HW_VERSION 6
Christopher Ferris38062f92014-07-09 15:33:25 -070066#define DRM_VMW_PARAM_MAX_SURF_MEMORY 7
Christopher Ferris05d08e92016-02-04 13:16:38 -080067#define DRM_VMW_PARAM_3D_CAPS_SIZE 8
Christopher Ferris38062f92014-07-09 15:33:25 -070068#define DRM_VMW_PARAM_MAX_MOB_MEMORY 9
69#define DRM_VMW_PARAM_MAX_MOB_SIZE 10
Christopher Ferris05d08e92016-02-04 13:16:38 -080070#define DRM_VMW_PARAM_SCREEN_TARGET 11
Christopher Ferris05d08e92016-02-04 13:16:38 -080071#define DRM_VMW_PARAM_DX 12
Christopher Ferris9ce28842018-10-25 12:11:39 -070072#define DRM_VMW_PARAM_HW_CAPS2 13
73#define DRM_VMW_PARAM_SM4_1 14
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070074enum drm_vmw_handle_type {
Tao Baod7db5942015-01-28 10:07:51 -080075 DRM_VMW_HANDLE_LEGACY = 0,
Tao Baod7db5942015-01-28 10:07:51 -080076 DRM_VMW_HANDLE_PRIME = 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070077};
Ben Cheng655a7c02013-10-16 16:09:24 -070078struct drm_vmw_getparam_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070079 __u64 value;
80 __u32 param;
81 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070082};
83struct drm_vmw_context_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -070084 __s32 cid;
85 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -070086};
87struct drm_vmw_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -070088 __u32 flags;
89 __u32 format;
90 __u32 mip_levels[DRM_VMW_MAX_SURFACE_FACES];
Christopher Ferris106b3a82016-08-24 12:15:38 -070091 __u64 size_addr;
92 __s32 shareable;
93 __s32 scanout;
Ben Cheng655a7c02013-10-16 16:09:24 -070094};
Christopher Ferris106b3a82016-08-24 12:15:38 -070095struct drm_vmw_surface_arg {
96 __s32 sid;
Tao Baod7db5942015-01-28 10:07:51 -080097 enum drm_vmw_handle_type handle_type;
Ben Cheng655a7c02013-10-16 16:09:24 -070098};
99struct drm_vmw_size {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700100 __u32 width;
101 __u32 height;
102 __u32 depth;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700103 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700104};
105union drm_vmw_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800106 struct drm_vmw_surface_arg rep;
107 struct drm_vmw_surface_create_req req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700108};
109union drm_vmw_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800110 struct drm_vmw_surface_create_req rep;
111 struct drm_vmw_surface_arg req;
Ben Cheng655a7c02013-10-16 16:09:24 -0700112};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113#define DRM_VMW_EXECBUF_VERSION 2
Christopher Ferris1308ad32017-11-14 17:32:13 -0800114#define DRM_VMW_EXECBUF_FLAG_IMPORT_FENCE_FD (1 << 0)
115#define DRM_VMW_EXECBUF_FLAG_EXPORT_FENCE_FD (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700116struct drm_vmw_execbuf_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700117 __u64 commands;
118 __u32 command_size;
119 __u32 throttle_us;
120 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700121 __u32 version;
122 __u32 flags;
123 __u32 context_handle;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800124 __s32 imported_fence_fd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700125};
Ben Cheng655a7c02013-10-16 16:09:24 -0700126struct drm_vmw_fence_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127 __u32 handle;
128 __u32 mask;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700129 __u32 seqno;
130 __u32 passed_seqno;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800131 __s32 fd;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700132 __s32 error;
Ben Cheng655a7c02013-10-16 16:09:24 -0700133};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700134struct drm_vmw_alloc_bo_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700135 __u32 size;
136 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700137};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700138#define drm_vmw_alloc_dmabuf_req drm_vmw_alloc_bo_req
139struct drm_vmw_bo_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700140 __u64 map_handle;
141 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700142 __u32 cur_gmr_id;
143 __u32 cur_gmr_offset;
144 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700145};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700146#define drm_vmw_dmabuf_rep drm_vmw_bo_rep
147union drm_vmw_alloc_bo_arg {
148 struct drm_vmw_alloc_bo_req req;
149 struct drm_vmw_bo_rep rep;
Ben Cheng655a7c02013-10-16 16:09:24 -0700150};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700151#define drm_vmw_alloc_dmabuf_arg drm_vmw_alloc_bo_arg
Ben Cheng655a7c02013-10-16 16:09:24 -0700152struct drm_vmw_rect {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700153 __s32 x;
154 __s32 y;
155 __u32 w;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700156 __u32 h;
Ben Cheng655a7c02013-10-16 16:09:24 -0700157};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800158struct drm_vmw_control_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700159 __u32 stream_id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700160 __u32 enabled;
161 __u32 flags;
162 __u32 color_key;
163 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700164 __u32 offset;
165 __s32 format;
166 __u32 size;
167 __u32 width;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700168 __u32 height;
169 __u32 pitch[3];
170 __u32 pad64;
Tao Baod7db5942015-01-28 10:07:51 -0800171 struct drm_vmw_rect src;
172 struct drm_vmw_rect dst;
Ben Cheng655a7c02013-10-16 16:09:24 -0700173};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800174#define DRM_VMW_CURSOR_BYPASS_ALL (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700175#define DRM_VMW_CURSOR_BYPASS_FLAGS (1)
176struct drm_vmw_cursor_bypass_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700177 __u32 flags;
178 __u32 crtc_id;
179 __s32 xpos;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700180 __s32 ypos;
181 __s32 xhot;
182 __s32 yhot;
Ben Cheng655a7c02013-10-16 16:09:24 -0700183};
184struct drm_vmw_stream_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700185 __u32 stream_id;
186 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700187};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700188struct drm_vmw_get_3d_cap_arg {
189 __u64 buffer;
190 __u32 max_size;
191 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700192};
Ben Cheng655a7c02013-10-16 16:09:24 -0700193#define DRM_VMW_FENCE_FLAG_EXEC (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800194#define DRM_VMW_FENCE_FLAG_QUERY (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700195#define DRM_VMW_WAIT_OPTION_UNREF (1 << 0)
196struct drm_vmw_fence_wait_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700197 __u32 handle;
198 __s32 cookie_valid;
199 __u64 kernel_cookie;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700200 __u64 timeout_us;
201 __s32 lazy;
202 __s32 flags;
203 __s32 wait_options;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700204 __s32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700205};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800206struct drm_vmw_fence_signaled_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700207 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700208 __u32 flags;
209 __s32 signaled;
210 __u32 passed_seqno;
211 __u32 signaled_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700212 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700213};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800214struct drm_vmw_fence_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700215 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700216 __u32 pad64;
217};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800218#define DRM_VMW_EVENT_FENCE_SIGNALED 0x80000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700219struct drm_vmw_event_fence {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700220 struct drm_event base;
221 __u64 user_data;
222 __u32 tv_sec;
223 __u32 tv_usec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700224};
Ben Cheng655a7c02013-10-16 16:09:24 -0700225#define DRM_VMW_FE_FLAG_REQ_TIME (1 << 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800226struct drm_vmw_fence_event_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700227 __u64 fence_rep;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700228 __u64 user_data;
229 __u32 handle;
230 __u32 flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700231};
232struct drm_vmw_present_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700233 __u32 fb_id;
234 __u32 sid;
235 __s32 dest_x;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700236 __s32 dest_y;
237 __u64 clips_ptr;
238 __u32 num_clips;
239 __u32 pad64;
Ben Cheng655a7c02013-10-16 16:09:24 -0700240};
Ben Cheng655a7c02013-10-16 16:09:24 -0700241struct drm_vmw_present_readback_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700242 __u32 fb_id;
243 __u32 num_clips;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700244 __u64 clips_ptr;
245 __u64 fence_rep;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800246};
Ben Cheng655a7c02013-10-16 16:09:24 -0700247struct drm_vmw_update_layout_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700248 __u32 num_outputs;
249 __u32 pad64;
250 __u64 rects;
Christopher Ferris38062f92014-07-09 15:33:25 -0700251};
252enum drm_vmw_shader_type {
Tao Baod7db5942015-01-28 10:07:51 -0800253 drm_vmw_shader_type_vs = 0,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800254 drm_vmw_shader_type_ps,
Christopher Ferris38062f92014-07-09 15:33:25 -0700255};
256struct drm_vmw_shader_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800257 enum drm_vmw_shader_type shader_type;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700258 __u32 size;
259 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700260 __u32 shader_handle;
261 __u64 offset;
Christopher Ferris38062f92014-07-09 15:33:25 -0700262};
263struct drm_vmw_shader_arg {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700264 __u32 handle;
265 __u32 pad64;
Christopher Ferris38062f92014-07-09 15:33:25 -0700266};
267enum drm_vmw_surface_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800268 drm_vmw_surface_flag_shareable = (1 << 0),
269 drm_vmw_surface_flag_scanout = (1 << 1),
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800270 drm_vmw_surface_flag_create_buffer = (1 << 2),
271 drm_vmw_surface_flag_coherent = (1 << 3),
Christopher Ferris38062f92014-07-09 15:33:25 -0700272};
273struct drm_vmw_gb_surface_create_req {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700274 __u32 svga3d_flags;
275 __u32 format;
276 __u32 mip_levels;
Tao Baod7db5942015-01-28 10:07:51 -0800277 enum drm_vmw_surface_flags drm_surface_flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700278 __u32 multisample_count;
279 __u32 autogen_filter;
280 __u32 buffer_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700281 __u32 array_size;
Tao Baod7db5942015-01-28 10:07:51 -0800282 struct drm_vmw_size base_size;
Christopher Ferris38062f92014-07-09 15:33:25 -0700283};
284struct drm_vmw_gb_surface_create_rep {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700285 __u32 handle;
286 __u32 backup_size;
287 __u32 buffer_handle;
288 __u32 buffer_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700289 __u64 buffer_map_handle;
Christopher Ferris38062f92014-07-09 15:33:25 -0700290};
Christopher Ferris38062f92014-07-09 15:33:25 -0700291union drm_vmw_gb_surface_create_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800292 struct drm_vmw_gb_surface_create_rep rep;
293 struct drm_vmw_gb_surface_create_req req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700294};
Christopher Ferris38062f92014-07-09 15:33:25 -0700295struct drm_vmw_gb_surface_ref_rep {
Tao Baod7db5942015-01-28 10:07:51 -0800296 struct drm_vmw_gb_surface_create_req creq;
297 struct drm_vmw_gb_surface_create_rep crep;
Christopher Ferris38062f92014-07-09 15:33:25 -0700298};
Christopher Ferris38062f92014-07-09 15:33:25 -0700299union drm_vmw_gb_surface_reference_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800300 struct drm_vmw_gb_surface_ref_rep rep;
301 struct drm_vmw_surface_arg req;
Christopher Ferris38062f92014-07-09 15:33:25 -0700302};
Christopher Ferris38062f92014-07-09 15:33:25 -0700303enum drm_vmw_synccpu_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800304 drm_vmw_synccpu_read = (1 << 0),
305 drm_vmw_synccpu_write = (1 << 1),
306 drm_vmw_synccpu_dontblock = (1 << 2),
Tao Baod7db5942015-01-28 10:07:51 -0800307 drm_vmw_synccpu_allow_cs = (1 << 3)
Christopher Ferris38062f92014-07-09 15:33:25 -0700308};
309enum drm_vmw_synccpu_op {
Tao Baod7db5942015-01-28 10:07:51 -0800310 drm_vmw_synccpu_grab,
Tao Baod7db5942015-01-28 10:07:51 -0800311 drm_vmw_synccpu_release
Christopher Ferris38062f92014-07-09 15:33:25 -0700312};
313struct drm_vmw_synccpu_arg {
Tao Baod7db5942015-01-28 10:07:51 -0800314 enum drm_vmw_synccpu_op op;
Tao Baod7db5942015-01-28 10:07:51 -0800315 enum drm_vmw_synccpu_flags flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700316 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700317 __u32 pad64;
318};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800319enum drm_vmw_extended_context {
320 drm_vmw_context_legacy,
321 drm_vmw_context_dx
322};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800323union drm_vmw_extended_context_arg {
324 enum drm_vmw_extended_context req;
325 struct drm_vmw_context_arg rep;
326};
Christopher Ferris525ce912017-07-26 13:12:53 -0700327struct drm_vmw_handle_close_arg {
328 __u32 handle;
329 __u32 pad64;
330};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700331#define drm_vmw_unref_dmabuf_arg drm_vmw_handle_close_arg
332enum drm_vmw_surface_version {
333 drm_vmw_gb_surface_v1
334};
335struct drm_vmw_gb_surface_create_ext_req {
336 struct drm_vmw_gb_surface_create_req base;
337 enum drm_vmw_surface_version version;
338 uint32_t svga3d_flags_upper_32_bits;
339 SVGA3dMSPattern multisample_pattern;
340 SVGA3dMSQualityLevel quality_level;
341 uint64_t must_be_zero;
342};
343union drm_vmw_gb_surface_create_ext_arg {
344 struct drm_vmw_gb_surface_create_rep rep;
345 struct drm_vmw_gb_surface_create_ext_req req;
346};
347struct drm_vmw_gb_surface_ref_ext_rep {
348 struct drm_vmw_gb_surface_create_ext_req creq;
349 struct drm_vmw_gb_surface_create_rep crep;
350};
351union drm_vmw_gb_surface_reference_ext_arg {
352 struct drm_vmw_gb_surface_ref_ext_rep rep;
353 struct drm_vmw_surface_arg req;
354};
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -0700355struct drm_vmw_msg_arg {
356 __u64 send;
357 __u64 receive;
358 __s32 send_only;
359 __u32 receive_len;
360};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700361#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800362}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700363#endif
Christopher Ferris38062f92014-07-09 15:33:25 -0700364#endif