blob: 2fe61d6565ace87a4341d218ceea0ac338012866 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Christopher Ferris106b3a82016-08-24 12:15:38 -07007#ifndef __ETNAVIV_DRM_H__
8#define __ETNAVIV_DRM_H__
9#include "drm.h"
10#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080011extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070012#endif
13struct drm_etnaviv_timespec {
14 __s64 tv_sec;
15 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070016};
17#define ETNAVIV_PARAM_GPU_MODEL 0x01
18#define ETNAVIV_PARAM_GPU_REVISION 0x02
19#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070020#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
21#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
22#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
23#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
25#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
Christopher Ferris76a1d452018-06-27 14:12:29 -070026#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
27#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
28#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
29#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
30#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
31#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
33#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
Christopher Ferris106b3a82016-08-24 12:15:38 -070034#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
35#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
36#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
37#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
Christopher Ferris106b3a82016-08-24 12:15:38 -070038#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
39#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
40#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
41#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
Christopher Ferris106b3a82016-08-24 12:15:38 -070042#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
Christopher Ferris9584fa42019-12-09 15:36:13 -080043#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
Christopher Ferris3a39c0b2021-09-02 00:03:38 +000044#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
45#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
46#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
Christopher Ferris106b3a82016-08-24 12:15:38 -070047#define ETNA_MAX_PIPES 4
48struct drm_etnaviv_param {
49 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -070050 __u32 param;
51 __u64 value;
52};
53#define ETNA_BO_CACHE_MASK 0x000f0000
Christopher Ferris106b3a82016-08-24 12:15:38 -070054#define ETNA_BO_CACHED 0x00010000
55#define ETNA_BO_WC 0x00020000
56#define ETNA_BO_UNCACHED 0x00040000
57#define ETNA_BO_FORCE_MMU 0x00100000
Christopher Ferris106b3a82016-08-24 12:15:38 -070058struct drm_etnaviv_gem_new {
59 __u64 size;
60 __u32 flags;
61 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070062};
63struct drm_etnaviv_gem_info {
64 __u32 handle;
65 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -070066 __u64 offset;
67};
68#define ETNA_PREP_READ 0x01
69#define ETNA_PREP_WRITE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070070#define ETNA_PREP_NOSYNC 0x04
71struct drm_etnaviv_gem_cpu_prep {
72 __u32 handle;
73 __u32 op;
Christopher Ferris106b3a82016-08-24 12:15:38 -070074 struct drm_etnaviv_timespec timeout;
75};
76struct drm_etnaviv_gem_cpu_fini {
77 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u32 flags;
79};
80struct drm_etnaviv_gem_submit_reloc {
81 __u32 submit_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070082 __u32 reloc_idx;
83 __u64 reloc_offset;
84 __u32 flags;
85};
Christopher Ferris106b3a82016-08-24 12:15:38 -070086#define ETNA_SUBMIT_BO_READ 0x0001
87#define ETNA_SUBMIT_BO_WRITE 0x0002
88struct drm_etnaviv_gem_submit_bo {
89 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -070090 __u32 handle;
91 __u64 presumed;
92};
Christopher Ferris934ec942018-01-31 15:29:16 -080093#define ETNA_PM_PROCESS_PRE 0x0001
94#define ETNA_PM_PROCESS_POST 0x0002
95struct drm_etnaviv_gem_submit_pmr {
96 __u32 flags;
97 __u8 domain;
98 __u8 pad;
99 __u16 signal;
100 __u32 sequence;
101 __u32 read_offset;
102 __u32 read_idx;
103};
Christopher Ferris525ce912017-07-26 13:12:53 -0700104#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
105#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
106#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
Christopher Ferris9584fa42019-12-09 15:36:13 -0800107#define ETNA_SUBMIT_SOFTPIN 0x0008
108#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700109#define ETNA_PIPE_3D 0x00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700110#define ETNA_PIPE_2D 0x01
111#define ETNA_PIPE_VG 0x02
112struct drm_etnaviv_gem_submit {
113 __u32 fence;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700114 __u32 pipe;
115 __u32 exec_state;
116 __u32 nr_bos;
117 __u32 nr_relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118 __u32 stream_size;
119 __u64 bos;
120 __u64 relocs;
121 __u64 stream;
Christopher Ferris525ce912017-07-26 13:12:53 -0700122 __u32 flags;
123 __s32 fence_fd;
Christopher Ferris934ec942018-01-31 15:29:16 -0800124 __u64 pmrs;
125 __u32 nr_pmrs;
126 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127};
128#define ETNA_WAIT_NONBLOCK 0x01
129struct drm_etnaviv_wait_fence {
130 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700131 __u32 fence;
132 __u32 flags;
133 __u32 pad;
134 struct drm_etnaviv_timespec timeout;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700135};
136#define ETNA_USERPTR_READ 0x01
137#define ETNA_USERPTR_WRITE 0x02
138struct drm_etnaviv_gem_userptr {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700139 __u64 user_ptr;
140 __u64 user_size;
141 __u32 flags;
142 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700143};
144struct drm_etnaviv_gem_wait {
145 __u32 pipe;
146 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147 __u32 flags;
148 __u32 pad;
149 struct drm_etnaviv_timespec timeout;
150};
Christopher Ferris934ec942018-01-31 15:29:16 -0800151struct drm_etnaviv_pm_domain {
152 __u32 pipe;
153 __u8 iter;
154 __u8 id;
155 __u16 nr_signals;
156 char name[64];
157};
158struct drm_etnaviv_pm_signal {
159 __u32 pipe;
160 __u8 domain;
161 __u8 pad;
162 __u16 iter;
163 __u16 id;
164 char name[64];
165};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700166#define DRM_ETNAVIV_GET_PARAM 0x00
167#define DRM_ETNAVIV_GEM_NEW 0x02
168#define DRM_ETNAVIV_GEM_INFO 0x03
169#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -0700170#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
171#define DRM_ETNAVIV_GEM_SUBMIT 0x06
172#define DRM_ETNAVIV_WAIT_FENCE 0x07
173#define DRM_ETNAVIV_GEM_USERPTR 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -0700174#define DRM_ETNAVIV_GEM_WAIT 0x09
Christopher Ferris934ec942018-01-31 15:29:16 -0800175#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
176#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
177#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
Christopher Ferris106b3a82016-08-24 12:15:38 -0700178#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
179#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700180#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
181#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
182#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
183#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700184#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
185#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
186#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
Christopher Ferris934ec942018-01-31 15:29:16 -0800187#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
188#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700189#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800190}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700191#endif
192#endif