Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame^] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef __ETNAVIV_DRM_H__ |
| 20 | #define __ETNAVIV_DRM_H__ |
| 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
| 23 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 24 | #endif |
| 25 | struct drm_etnaviv_timespec { |
| 26 | __s64 tv_sec; |
| 27 | __s64 tv_nsec; |
| 28 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 29 | }; |
| 30 | #define ETNAVIV_PARAM_GPU_MODEL 0x01 |
| 31 | #define ETNAVIV_PARAM_GPU_REVISION 0x02 |
| 32 | #define ETNAVIV_PARAM_GPU_FEATURES_0 0x03 |
| 33 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 34 | #define ETNAVIV_PARAM_GPU_FEATURES_1 0x04 |
| 35 | #define ETNAVIV_PARAM_GPU_FEATURES_2 0x05 |
| 36 | #define ETNAVIV_PARAM_GPU_FEATURES_3 0x06 |
| 37 | #define ETNAVIV_PARAM_GPU_FEATURES_4 0x07 |
| 38 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 39 | #define ETNAVIV_PARAM_GPU_FEATURES_5 0x08 |
| 40 | #define ETNAVIV_PARAM_GPU_FEATURES_6 0x09 |
| 41 | #define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10 |
| 42 | #define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11 |
| 43 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 44 | #define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12 |
| 45 | #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13 |
| 46 | #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14 |
| 47 | #define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15 |
| 48 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 49 | #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16 |
| 50 | #define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17 |
| 51 | #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18 |
| 52 | #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19 |
| 53 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 54 | #define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a |
| 55 | #define ETNA_MAX_PIPES 4 |
| 56 | struct drm_etnaviv_param { |
| 57 | __u32 pipe; |
| 58 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 59 | __u32 param; |
| 60 | __u64 value; |
| 61 | }; |
| 62 | #define ETNA_BO_CACHE_MASK 0x000f0000 |
| 63 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 64 | #define ETNA_BO_CACHED 0x00010000 |
| 65 | #define ETNA_BO_WC 0x00020000 |
| 66 | #define ETNA_BO_UNCACHED 0x00040000 |
| 67 | #define ETNA_BO_FORCE_MMU 0x00100000 |
| 68 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 69 | struct drm_etnaviv_gem_new { |
| 70 | __u64 size; |
| 71 | __u32 flags; |
| 72 | __u32 handle; |
| 73 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 74 | }; |
| 75 | struct drm_etnaviv_gem_info { |
| 76 | __u32 handle; |
| 77 | __u32 pad; |
| 78 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 79 | __u64 offset; |
| 80 | }; |
| 81 | #define ETNA_PREP_READ 0x01 |
| 82 | #define ETNA_PREP_WRITE 0x02 |
| 83 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 84 | #define ETNA_PREP_NOSYNC 0x04 |
| 85 | struct drm_etnaviv_gem_cpu_prep { |
| 86 | __u32 handle; |
| 87 | __u32 op; |
| 88 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 89 | struct drm_etnaviv_timespec timeout; |
| 90 | }; |
| 91 | struct drm_etnaviv_gem_cpu_fini { |
| 92 | __u32 handle; |
| 93 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 94 | __u32 flags; |
| 95 | }; |
| 96 | struct drm_etnaviv_gem_submit_reloc { |
| 97 | __u32 submit_offset; |
| 98 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 99 | __u32 reloc_idx; |
| 100 | __u64 reloc_offset; |
| 101 | __u32 flags; |
| 102 | }; |
| 103 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 104 | #define ETNA_SUBMIT_BO_READ 0x0001 |
| 105 | #define ETNA_SUBMIT_BO_WRITE 0x0002 |
| 106 | struct drm_etnaviv_gem_submit_bo { |
| 107 | __u32 flags; |
| 108 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 109 | __u32 handle; |
| 110 | __u64 presumed; |
| 111 | }; |
| 112 | #define ETNA_PIPE_3D 0x00 |
| 113 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 114 | #define ETNA_PIPE_2D 0x01 |
| 115 | #define ETNA_PIPE_VG 0x02 |
| 116 | struct drm_etnaviv_gem_submit { |
| 117 | __u32 fence; |
| 118 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 119 | __u32 pipe; |
| 120 | __u32 exec_state; |
| 121 | __u32 nr_bos; |
| 122 | __u32 nr_relocs; |
| 123 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 124 | __u32 stream_size; |
| 125 | __u64 bos; |
| 126 | __u64 relocs; |
| 127 | __u64 stream; |
| 128 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 129 | }; |
| 130 | #define ETNA_WAIT_NONBLOCK 0x01 |
| 131 | struct drm_etnaviv_wait_fence { |
| 132 | __u32 pipe; |
| 133 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 134 | __u32 fence; |
| 135 | __u32 flags; |
| 136 | __u32 pad; |
| 137 | struct drm_etnaviv_timespec timeout; |
| 138 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 139 | }; |
| 140 | #define ETNA_USERPTR_READ 0x01 |
| 141 | #define ETNA_USERPTR_WRITE 0x02 |
| 142 | struct drm_etnaviv_gem_userptr { |
| 143 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 144 | __u64 user_ptr; |
| 145 | __u64 user_size; |
| 146 | __u32 flags; |
| 147 | __u32 handle; |
| 148 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 149 | }; |
| 150 | struct drm_etnaviv_gem_wait { |
| 151 | __u32 pipe; |
| 152 | __u32 handle; |
| 153 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 154 | __u32 flags; |
| 155 | __u32 pad; |
| 156 | struct drm_etnaviv_timespec timeout; |
| 157 | }; |
| 158 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 159 | #define DRM_ETNAVIV_GET_PARAM 0x00 |
| 160 | #define DRM_ETNAVIV_GEM_NEW 0x02 |
| 161 | #define DRM_ETNAVIV_GEM_INFO 0x03 |
| 162 | #define DRM_ETNAVIV_GEM_CPU_PREP 0x04 |
| 163 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 164 | #define DRM_ETNAVIV_GEM_CPU_FINI 0x05 |
| 165 | #define DRM_ETNAVIV_GEM_SUBMIT 0x06 |
| 166 | #define DRM_ETNAVIV_WAIT_FENCE 0x07 |
| 167 | #define DRM_ETNAVIV_GEM_USERPTR 0x08 |
| 168 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 169 | #define DRM_ETNAVIV_GEM_WAIT 0x09 |
| 170 | #define DRM_ETNAVIV_NUM_IOCTLS 0x0a |
| 171 | #define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param) |
| 172 | #define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new) |
| 173 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 174 | #define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info) |
| 175 | #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep) |
| 176 | #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini) |
| 177 | #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit) |
| 178 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 179 | #define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence) |
| 180 | #define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr) |
| 181 | #define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait) |
| 182 | #ifdef __cplusplus |
| 183 | /* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */ |
| 184 | #endif |
| 185 | #endif |