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Christopher Ferris106b3a82016-08-24 12:15:38 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __ETNAVIV_DRM_H__
20#define __ETNAVIV_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25struct drm_etnaviv_timespec {
26 __s64 tv_sec;
27 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070028};
29#define ETNAVIV_PARAM_GPU_MODEL 0x01
30#define ETNAVIV_PARAM_GPU_REVISION 0x02
31#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
33#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
34#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
35#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
Christopher Ferris106b3a82016-08-24 12:15:38 -070036#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
37#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
Christopher Ferris76a1d452018-06-27 14:12:29 -070038#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
39#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
40#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
41#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
42#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
43#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
Christopher Ferris106b3a82016-08-24 12:15:38 -070044#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
45#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
Christopher Ferris106b3a82016-08-24 12:15:38 -070046#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
47#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
48#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
49#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
Christopher Ferris106b3a82016-08-24 12:15:38 -070050#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
51#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
52#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
53#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
Christopher Ferris106b3a82016-08-24 12:15:38 -070054#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
Christopher Ferris9584fa42019-12-09 15:36:13 -080055#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
Christopher Ferris106b3a82016-08-24 12:15:38 -070056#define ETNA_MAX_PIPES 4
57struct drm_etnaviv_param {
58 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -070059 __u32 param;
60 __u64 value;
61};
62#define ETNA_BO_CACHE_MASK 0x000f0000
Christopher Ferris106b3a82016-08-24 12:15:38 -070063#define ETNA_BO_CACHED 0x00010000
64#define ETNA_BO_WC 0x00020000
65#define ETNA_BO_UNCACHED 0x00040000
66#define ETNA_BO_FORCE_MMU 0x00100000
Christopher Ferris106b3a82016-08-24 12:15:38 -070067struct drm_etnaviv_gem_new {
68 __u64 size;
69 __u32 flags;
70 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070071};
72struct drm_etnaviv_gem_info {
73 __u32 handle;
74 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -070075 __u64 offset;
76};
77#define ETNA_PREP_READ 0x01
78#define ETNA_PREP_WRITE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070079#define ETNA_PREP_NOSYNC 0x04
80struct drm_etnaviv_gem_cpu_prep {
81 __u32 handle;
82 __u32 op;
Christopher Ferris106b3a82016-08-24 12:15:38 -070083 struct drm_etnaviv_timespec timeout;
84};
85struct drm_etnaviv_gem_cpu_fini {
86 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070087 __u32 flags;
88};
89struct drm_etnaviv_gem_submit_reloc {
90 __u32 submit_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070091 __u32 reloc_idx;
92 __u64 reloc_offset;
93 __u32 flags;
94};
Christopher Ferris106b3a82016-08-24 12:15:38 -070095#define ETNA_SUBMIT_BO_READ 0x0001
96#define ETNA_SUBMIT_BO_WRITE 0x0002
97struct drm_etnaviv_gem_submit_bo {
98 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -070099 __u32 handle;
100 __u64 presumed;
101};
Christopher Ferris934ec942018-01-31 15:29:16 -0800102#define ETNA_PM_PROCESS_PRE 0x0001
103#define ETNA_PM_PROCESS_POST 0x0002
104struct drm_etnaviv_gem_submit_pmr {
105 __u32 flags;
106 __u8 domain;
107 __u8 pad;
108 __u16 signal;
109 __u32 sequence;
110 __u32 read_offset;
111 __u32 read_idx;
112};
Christopher Ferris525ce912017-07-26 13:12:53 -0700113#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
114#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
115#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
Christopher Ferris9584fa42019-12-09 15:36:13 -0800116#define ETNA_SUBMIT_SOFTPIN 0x0008
117#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118#define ETNA_PIPE_3D 0x00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700119#define ETNA_PIPE_2D 0x01
120#define ETNA_PIPE_VG 0x02
121struct drm_etnaviv_gem_submit {
122 __u32 fence;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700123 __u32 pipe;
124 __u32 exec_state;
125 __u32 nr_bos;
126 __u32 nr_relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700127 __u32 stream_size;
128 __u64 bos;
129 __u64 relocs;
130 __u64 stream;
Christopher Ferris525ce912017-07-26 13:12:53 -0700131 __u32 flags;
132 __s32 fence_fd;
Christopher Ferris934ec942018-01-31 15:29:16 -0800133 __u64 pmrs;
134 __u32 nr_pmrs;
135 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700136};
137#define ETNA_WAIT_NONBLOCK 0x01
138struct drm_etnaviv_wait_fence {
139 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700140 __u32 fence;
141 __u32 flags;
142 __u32 pad;
143 struct drm_etnaviv_timespec timeout;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700144};
145#define ETNA_USERPTR_READ 0x01
146#define ETNA_USERPTR_WRITE 0x02
147struct drm_etnaviv_gem_userptr {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700148 __u64 user_ptr;
149 __u64 user_size;
150 __u32 flags;
151 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700152};
153struct drm_etnaviv_gem_wait {
154 __u32 pipe;
155 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700156 __u32 flags;
157 __u32 pad;
158 struct drm_etnaviv_timespec timeout;
159};
Christopher Ferris934ec942018-01-31 15:29:16 -0800160struct drm_etnaviv_pm_domain {
161 __u32 pipe;
162 __u8 iter;
163 __u8 id;
164 __u16 nr_signals;
165 char name[64];
166};
167struct drm_etnaviv_pm_signal {
168 __u32 pipe;
169 __u8 domain;
170 __u8 pad;
171 __u16 iter;
172 __u16 id;
173 char name[64];
174};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700175#define DRM_ETNAVIV_GET_PARAM 0x00
176#define DRM_ETNAVIV_GEM_NEW 0x02
177#define DRM_ETNAVIV_GEM_INFO 0x03
178#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -0700179#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
180#define DRM_ETNAVIV_GEM_SUBMIT 0x06
181#define DRM_ETNAVIV_WAIT_FENCE 0x07
182#define DRM_ETNAVIV_GEM_USERPTR 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -0700183#define DRM_ETNAVIV_GEM_WAIT 0x09
Christopher Ferris934ec942018-01-31 15:29:16 -0800184#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
185#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
186#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
Christopher Ferris106b3a82016-08-24 12:15:38 -0700187#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
188#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700189#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
190#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
191#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
192#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700193#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
194#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
195#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
Christopher Ferris934ec942018-01-31 15:29:16 -0800196#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
197#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700198#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800199}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700200#endif
201#endif