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Christopher Ferris106b3a82016-08-24 12:15:38 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __ETNAVIV_DRM_H__
20#define __ETNAVIV_DRM_H__
21#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25struct drm_etnaviv_timespec {
26 __s64 tv_sec;
27 __s64 tv_nsec;
Christopher Ferris106b3a82016-08-24 12:15:38 -070028};
29#define ETNAVIV_PARAM_GPU_MODEL 0x01
30#define ETNAVIV_PARAM_GPU_REVISION 0x02
31#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
33#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
34#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
35#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
Christopher Ferris106b3a82016-08-24 12:15:38 -070036#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
37#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
Christopher Ferris76a1d452018-06-27 14:12:29 -070038#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
39#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
40#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
41#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
42#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
43#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
Christopher Ferris106b3a82016-08-24 12:15:38 -070044#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
45#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
Christopher Ferris106b3a82016-08-24 12:15:38 -070046#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
47#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
48#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
49#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
Christopher Ferris106b3a82016-08-24 12:15:38 -070050#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
51#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
52#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
53#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
Christopher Ferris106b3a82016-08-24 12:15:38 -070054#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
Christopher Ferris9584fa42019-12-09 15:36:13 -080055#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
Christopher Ferris3a39c0b2021-09-02 00:03:38 +000056#define ETNAVIV_PARAM_GPU_PRODUCT_ID 0x1c
57#define ETNAVIV_PARAM_GPU_CUSTOMER_ID 0x1d
58#define ETNAVIV_PARAM_GPU_ECO_ID 0x1e
Christopher Ferris106b3a82016-08-24 12:15:38 -070059#define ETNA_MAX_PIPES 4
60struct drm_etnaviv_param {
61 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -070062 __u32 param;
63 __u64 value;
64};
65#define ETNA_BO_CACHE_MASK 0x000f0000
Christopher Ferris106b3a82016-08-24 12:15:38 -070066#define ETNA_BO_CACHED 0x00010000
67#define ETNA_BO_WC 0x00020000
68#define ETNA_BO_UNCACHED 0x00040000
69#define ETNA_BO_FORCE_MMU 0x00100000
Christopher Ferris106b3a82016-08-24 12:15:38 -070070struct drm_etnaviv_gem_new {
71 __u64 size;
72 __u32 flags;
73 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070074};
75struct drm_etnaviv_gem_info {
76 __u32 handle;
77 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u64 offset;
79};
80#define ETNA_PREP_READ 0x01
81#define ETNA_PREP_WRITE 0x02
Christopher Ferris106b3a82016-08-24 12:15:38 -070082#define ETNA_PREP_NOSYNC 0x04
83struct drm_etnaviv_gem_cpu_prep {
84 __u32 handle;
85 __u32 op;
Christopher Ferris106b3a82016-08-24 12:15:38 -070086 struct drm_etnaviv_timespec timeout;
87};
88struct drm_etnaviv_gem_cpu_fini {
89 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070090 __u32 flags;
91};
92struct drm_etnaviv_gem_submit_reloc {
93 __u32 submit_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070094 __u32 reloc_idx;
95 __u64 reloc_offset;
96 __u32 flags;
97};
Christopher Ferris106b3a82016-08-24 12:15:38 -070098#define ETNA_SUBMIT_BO_READ 0x0001
99#define ETNA_SUBMIT_BO_WRITE 0x0002
100struct drm_etnaviv_gem_submit_bo {
101 __u32 flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700102 __u32 handle;
103 __u64 presumed;
104};
Christopher Ferris934ec942018-01-31 15:29:16 -0800105#define ETNA_PM_PROCESS_PRE 0x0001
106#define ETNA_PM_PROCESS_POST 0x0002
107struct drm_etnaviv_gem_submit_pmr {
108 __u32 flags;
109 __u8 domain;
110 __u8 pad;
111 __u16 signal;
112 __u32 sequence;
113 __u32 read_offset;
114 __u32 read_idx;
115};
Christopher Ferris525ce912017-07-26 13:12:53 -0700116#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
117#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
118#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
Christopher Ferris9584fa42019-12-09 15:36:13 -0800119#define ETNA_SUBMIT_SOFTPIN 0x0008
120#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | ETNA_SUBMIT_FENCE_FD_IN | ETNA_SUBMIT_FENCE_FD_OUT | ETNA_SUBMIT_SOFTPIN)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700121#define ETNA_PIPE_3D 0x00
Christopher Ferris106b3a82016-08-24 12:15:38 -0700122#define ETNA_PIPE_2D 0x01
123#define ETNA_PIPE_VG 0x02
124struct drm_etnaviv_gem_submit {
125 __u32 fence;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700126 __u32 pipe;
127 __u32 exec_state;
128 __u32 nr_bos;
129 __u32 nr_relocs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700130 __u32 stream_size;
131 __u64 bos;
132 __u64 relocs;
133 __u64 stream;
Christopher Ferris525ce912017-07-26 13:12:53 -0700134 __u32 flags;
135 __s32 fence_fd;
Christopher Ferris934ec942018-01-31 15:29:16 -0800136 __u64 pmrs;
137 __u32 nr_pmrs;
138 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700139};
140#define ETNA_WAIT_NONBLOCK 0x01
141struct drm_etnaviv_wait_fence {
142 __u32 pipe;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700143 __u32 fence;
144 __u32 flags;
145 __u32 pad;
146 struct drm_etnaviv_timespec timeout;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700147};
148#define ETNA_USERPTR_READ 0x01
149#define ETNA_USERPTR_WRITE 0x02
150struct drm_etnaviv_gem_userptr {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700151 __u64 user_ptr;
152 __u64 user_size;
153 __u32 flags;
154 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700155};
156struct drm_etnaviv_gem_wait {
157 __u32 pipe;
158 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700159 __u32 flags;
160 __u32 pad;
161 struct drm_etnaviv_timespec timeout;
162};
Christopher Ferris934ec942018-01-31 15:29:16 -0800163struct drm_etnaviv_pm_domain {
164 __u32 pipe;
165 __u8 iter;
166 __u8 id;
167 __u16 nr_signals;
168 char name[64];
169};
170struct drm_etnaviv_pm_signal {
171 __u32 pipe;
172 __u8 domain;
173 __u8 pad;
174 __u16 iter;
175 __u16 id;
176 char name[64];
177};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700178#define DRM_ETNAVIV_GET_PARAM 0x00
179#define DRM_ETNAVIV_GEM_NEW 0x02
180#define DRM_ETNAVIV_GEM_INFO 0x03
181#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
Christopher Ferris106b3a82016-08-24 12:15:38 -0700182#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
183#define DRM_ETNAVIV_GEM_SUBMIT 0x06
184#define DRM_ETNAVIV_WAIT_FENCE 0x07
185#define DRM_ETNAVIV_GEM_USERPTR 0x08
Christopher Ferris106b3a82016-08-24 12:15:38 -0700186#define DRM_ETNAVIV_GEM_WAIT 0x09
Christopher Ferris934ec942018-01-31 15:29:16 -0800187#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
188#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
189#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
Christopher Ferris106b3a82016-08-24 12:15:38 -0700190#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
191#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700192#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
193#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
194#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
195#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700196#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
197#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
198#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
Christopher Ferris934ec942018-01-31 15:29:16 -0800199#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
200#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700201#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800202}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700203#endif
204#endif