blob: f1d1e1ef1b2ff9eda0bee5b0c7cea544b3915714 [file] [log] [blame]
Sean Paule0c4c3d2015-01-20 16:56:04 -05001/*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#define LOG_TAG "hwcomposer-drm"
18
Sean Paulef8f1f92015-04-29 16:05:23 -040019#include "drm_hwcomposer.h"
Sean Paul6a55e9f2015-04-30 15:31:06 -040020#include "drmresources.h"
Zach Reizner45624d32015-06-10 16:03:01 -070021#include "gl_compositor.h"
Sean Paulda6270d2015-06-01 14:11:52 -040022#include "importer.h"
Sean Paul4057be32015-05-13 06:23:09 -070023#include "vsyncworker.h"
Sean Paulef8f1f92015-04-29 16:05:23 -040024
Sean Paule0c4c3d2015-01-20 16:56:04 -050025#include <errno.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040026#include <fcntl.h>
Sean Paul5ad302c2015-05-11 10:43:31 -070027#include <list>
Sean Paule42febf2015-05-07 11:35:29 -070028#include <map>
Sean Paulef8f1f92015-04-29 16:05:23 -040029#include <pthread.h>
Dan Albertc5255b32015-05-07 23:42:54 -070030#include <stdlib.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050031#include <sys/param.h>
Sean Paul9aa5ad32015-01-22 15:47:54 -050032#include <sys/resource.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050033#include <xf86drm.h>
34#include <xf86drmMode.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050035
Sean Paulef8f1f92015-04-29 16:05:23 -040036#include <cutils/log.h>
37#include <cutils/properties.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050038#include <hardware/hardware.h>
39#include <hardware/hwcomposer.h>
Sean Paulf1dc1912015-01-24 01:34:31 -050040#include <sw_sync.h>
Sean Paulef8f1f92015-04-29 16:05:23 -040041#include <sync/sync.h>
Zach Reizner45624d32015-06-10 16:03:01 -070042#include <ui/GraphicBuffer.h>
43#include <ui/PixelFormat.h>
Sean Paule0c4c3d2015-01-20 16:56:04 -050044
Sean Paule0c4c3d2015-01-20 16:56:04 -050045#define UM_PER_INCH 25400
Zach Reizner45624d32015-06-10 16:03:01 -070046#define HWC_FB_BUFFERS 2
Sean Paule0c4c3d2015-01-20 16:56:04 -050047
Sean Paul6a55e9f2015-04-30 15:31:06 -040048namespace android {
Sean Paule0c4c3d2015-01-20 16:56:04 -050049
Zach Reizner45624d32015-06-10 16:03:01 -070050struct hwc_drm_display_framebuffer {
51 hwc_drm_display_framebuffer() : release_fence_fd_(-1) {
52 }
53
54 ~hwc_drm_display_framebuffer() {
55 if (release_fence_fd() >= 0)
56 close(release_fence_fd());
57 }
58
59 bool is_valid() {
60 return buffer_ != NULL;
61 }
62
63 sp<GraphicBuffer> buffer() {
64 return buffer_;
65 }
66
67 int release_fence_fd() {
68 return release_fence_fd_;
69 }
70
71 void set_release_fence_fd(int fd) {
72 if (release_fence_fd_ >= 0)
73 close(release_fence_fd_);
74 release_fence_fd_ = fd;
75 }
76
77 bool Allocate(uint32_t w, uint32_t h) {
78 if (is_valid()) {
79 if (buffer_->getWidth() == w && buffer_->getHeight() == h)
80 return true;
81
82 if (release_fence_fd_ >= 0) {
83 if (sync_wait(release_fence_fd_, -1) != 0) {
84 return false;
85 }
86 }
87 Clear();
88 }
89 buffer_ = new GraphicBuffer(w, h, android::PIXEL_FORMAT_RGBA_8888,
90 GRALLOC_USAGE_HW_FB | GRALLOC_USAGE_HW_RENDER |
91 GRALLOC_USAGE_HW_COMPOSER);
92 release_fence_fd_ = -1;
93 return is_valid();
94 }
95
96 void Clear() {
97 if (!is_valid())
98 return;
99
100 if (release_fence_fd_ >= 0) {
101 close(release_fence_fd_);
102 release_fence_fd_ = -1;
103 }
104
105 buffer_.clear();
106 }
107
108 int WaitReleased(int timeout_milliseconds) {
109 if (!is_valid())
110 return 0;
111 if (release_fence_fd_ < 0)
112 return 0;
113
114 int ret = sync_wait(release_fence_fd_, timeout_milliseconds);
115 return ret;
116 }
117
118 private:
119 sp<GraphicBuffer> buffer_;
120 int release_fence_fd_;
121};
122
123
Sean Paule42febf2015-05-07 11:35:29 -0700124typedef struct hwc_drm_display {
Sean Paulef8f1f92015-04-29 16:05:23 -0400125 struct hwc_context_t *ctx;
126 int display;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500127
Sean Paul6a55e9f2015-04-30 15:31:06 -0400128 std::vector<uint32_t> config_ids;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500129
Sean Paul4057be32015-05-13 06:23:09 -0700130 VSyncWorker vsync_worker;
Zach Reizner45624d32015-06-10 16:03:01 -0700131
132 hwc_drm_display_framebuffer fb_chain[HWC_FB_BUFFERS];
133 int fb_idx;
Sean Paule42febf2015-05-07 11:35:29 -0700134} hwc_drm_display_t;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500135
136struct hwc_context_t {
Sean Paule42febf2015-05-07 11:35:29 -0700137 // map of display:hwc_drm_display_t
138 typedef std::map<int, hwc_drm_display_t> DisplayMap;
139 typedef DisplayMap::iterator DisplayMapIter;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500140
Sean Paulda6270d2015-06-01 14:11:52 -0400141 hwc_context_t() : procs(NULL), importer(NULL) {
142 }
143
144 ~hwc_context_t() {
145 delete importer;
146 }
147
Sean Paule42febf2015-05-07 11:35:29 -0700148 hwc_composer_device_1_t device;
Sean Paulef8f1f92015-04-29 16:05:23 -0400149 hwc_procs_t const *procs;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500150
Sean Paule42febf2015-05-07 11:35:29 -0700151 DisplayMap displays;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400152 DrmResources drm;
Sean Paulda6270d2015-06-01 14:11:52 -0400153 Importer *importer;
Zach Reizner45624d32015-06-10 16:03:01 -0700154 GLCompositor pre_compositor;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500155};
156
Sean Paulb386f1b2015-05-13 06:33:23 -0700157static int hwc_prepare(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400158 hwc_display_contents_1_t **display_contents) {
Sean Paulb386f1b2015-05-13 06:33:23 -0700159 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700160 for (int i = 0; i < (int)num_displays; ++i) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400161 if (!display_contents[i])
162 continue;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500163
Sean Paulb386f1b2015-05-13 06:33:23 -0700164 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(i);
165 if (!crtc) {
166 ALOGE("No crtc for display %d", i);
Sean Paulb386f1b2015-05-13 06:33:23 -0700167 return -ENODEV;
168 }
Sean Paulb386f1b2015-05-13 06:33:23 -0700169
Zach Reizner45624d32015-06-10 16:03:01 -0700170 int num_layers = display_contents[i]->numHwLayers;
171 for (int j = 0; j < num_layers; j++) {
Sean Paulb386f1b2015-05-13 06:33:23 -0700172 hwc_layer_1_t *layer = &display_contents[i]->hwLayers[j];
Zach Reizner45624d32015-06-10 16:03:01 -0700173
174 if (crtc->requires_modeset()) {
175 if (layer->compositionType == HWC_OVERLAY)
176 layer->compositionType = HWC_FRAMEBUFFER;
177 } else {
178 if (layer->compositionType == HWC_FRAMEBUFFER)
179 layer->compositionType = HWC_OVERLAY;
180 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400181 }
182 }
Sean Pauldffca952015-02-04 10:19:55 -0800183
Sean Paulef8f1f92015-04-29 16:05:23 -0400184 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500185}
186
Sean Paulb386f1b2015-05-13 06:33:23 -0700187static void hwc_set_cleanup(size_t num_displays,
188 hwc_display_contents_1_t **display_contents,
189 Composition *composition) {
190 for (int i = 0; i < (int)num_displays; ++i) {
191 if (!display_contents[i])
192 continue;
193
194 hwc_display_contents_1_t *dc = display_contents[i];
195 for (size_t j = 0; j < dc->numHwLayers; ++j) {
196 hwc_layer_1_t *layer = &dc->hwLayers[j];
197 if (layer->acquireFenceFd >= 0) {
198 close(layer->acquireFenceFd);
199 layer->acquireFenceFd = -1;
200 }
201 }
202 if (dc->outbufAcquireFenceFd >= 0) {
203 close(dc->outbufAcquireFenceFd);
204 dc->outbufAcquireFenceFd = -1;
205 }
206 }
207
208 delete composition;
209}
210
Sean Paulb386f1b2015-05-13 06:33:23 -0700211static int hwc_add_layer(int display, hwc_context_t *ctx, hwc_layer_1_t *layer,
212 Composition *composition) {
213 hwc_drm_bo_t bo;
214 int ret = ctx->importer->ImportBuffer(layer->handle, &bo);
215 if (ret) {
216 ALOGE("Failed to import handle to bo %d", ret);
217 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400218 }
Sean Paulefb20cb2015-02-04 09:29:15 -0800219
Sean Paulb386f1b2015-05-13 06:33:23 -0700220 ret = composition->AddLayer(display, layer, &bo);
221 if (!ret)
Sean Paulef8f1f92015-04-29 16:05:23 -0400222 return 0;
Sean Paul9aa5ad32015-01-22 15:47:54 -0500223
Sean Paulb386f1b2015-05-13 06:33:23 -0700224 int destroy_ret = ctx->importer->ReleaseBuffer(&bo);
225 if (destroy_ret)
226 ALOGE("Failed to destroy buffer %d", destroy_ret);
Sean Paul9aa5ad32015-01-22 15:47:54 -0500227
Sean Paulef8f1f92015-04-29 16:05:23 -0400228 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500229}
230
231static int hwc_set(hwc_composer_device_1_t *dev, size_t num_displays,
Sean Paulef8f1f92015-04-29 16:05:23 -0400232 hwc_display_contents_1_t **display_contents) {
233 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paulb386f1b2015-05-13 06:33:23 -0700234 Composition *composition =
235 ctx->drm.compositor()->CreateComposition(ctx->importer);
236 if (!composition) {
237 ALOGE("Drm composition init failed");
238 hwc_set_cleanup(num_displays, display_contents, NULL);
239 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400240 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500241
Sean Paulb386f1b2015-05-13 06:33:23 -0700242 int ret;
243 for (int i = 0; i < (int)num_displays; ++i) {
244 if (!display_contents[i])
245 continue;
246
247 DrmCrtc *crtc = ctx->drm.GetCrtcForDisplay(i);
248 if (!crtc) {
249 ALOGE("No crtc for display %d", i);
250 hwc_set_cleanup(num_displays, display_contents, composition);
251 return -ENODEV;
252 }
Sean Paulb386f1b2015-05-13 06:33:23 -0700253 bool use_target = false;
Zach Reizner45624d32015-06-10 16:03:01 -0700254 if (crtc->requires_modeset()) {
Sean Paulb386f1b2015-05-13 06:33:23 -0700255 use_target = true;
Sean Paulb386f1b2015-05-13 06:33:23 -0700256 }
257
Zach Reizner45624d32015-06-10 16:03:01 -0700258 hwc_display_contents_1_t *dc = display_contents[i];
259 int j;
260 unsigned num_layers = 0;
261 unsigned num_dc_layers = dc->numHwLayers;
262 for (j = 0; j < (int)num_dc_layers; ++j) {
Sean Paulb386f1b2015-05-13 06:33:23 -0700263 hwc_layer_1_t *layer = &dc->hwLayers[j];
Zach Reizner45624d32015-06-10 16:03:01 -0700264 if (layer->flags & HWC_SKIP_LAYER)
Sean Paulb386f1b2015-05-13 06:33:23 -0700265 continue;
Zach Reizner45624d32015-06-10 16:03:01 -0700266 if ((use_target && layer->compositionType == HWC_FRAMEBUFFER_TARGET) ||
267 layer->compositionType == HWC_OVERLAY) {
268 num_layers++;
269 }
270 }
271
272 unsigned num_planes = composition->GetRemainingLayers(i, num_layers);
273 bool use_pre_compositor = false;
274
275 if (!use_target && num_layers > num_planes) {
276 use_pre_compositor = true;
277 // Reserve one of the planes for the result of the pre compositor.
278 num_planes--;
279 }
280
281 for (j = 0; num_planes && j < (int)num_dc_layers; ++j) {
282 hwc_layer_1_t *layer = &dc->hwLayers[j];
283 if (layer->flags & HWC_SKIP_LAYER)
284 continue;
285 if (use_target) {
286 if (layer->compositionType != HWC_FRAMEBUFFER_TARGET)
287 continue;
288 } else {
289 if (layer->compositionType != HWC_OVERLAY)
290 continue;
291 }
Sean Paulb386f1b2015-05-13 06:33:23 -0700292
293 ret = hwc_add_layer(i, ctx, layer, composition);
294 if (ret) {
295 ALOGE("Add layer failed %d", ret);
296 hwc_set_cleanup(num_displays, display_contents, composition);
297 return ret;
298 }
299 --num_planes;
300 }
Zach Reizner45624d32015-06-10 16:03:01 -0700301
302 int last_comp_layer = j;
303
304 if (use_pre_compositor) {
305 hwc_drm_display_t *hd = &ctx->displays[i];
306 struct hwc_drm_display_framebuffer *fb = &hd->fb_chain[hd->fb_idx];
307 ret = fb->WaitReleased(-1);
308 if (ret) {
309 ALOGE("Failed to wait for framebuffer %d", ret);
310 hwc_set_cleanup(num_displays, display_contents, composition);
311 return ret;
312 }
313
314 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(i);
315 if (!connector) {
316 ALOGE("No connector for display %d", i);
317 hwc_set_cleanup(num_displays, display_contents, composition);
318 return -ENODEV;
319 }
320
321 const DrmMode &mode = connector->active_mode();
322 if (!fb->Allocate(mode.h_display(), mode.v_display())) {
323 ALOGE("Failed to allocate framebuffer with size %dx%d",
324 mode.h_display(), mode.v_display());
325 hwc_set_cleanup(num_displays, display_contents, composition);
326 return -EINVAL;
327 }
328
329 sp<GraphicBuffer> fb_buffer = fb->buffer();
330 if (fb_buffer == NULL) {
331 ALOGE("Framebuffer is NULL");
332 hwc_set_cleanup(num_displays, display_contents, composition);
333 return -EINVAL;
334 }
335
336 Targeting *targeting = ctx->pre_compositor.targeting();
337 if (targeting == NULL) {
338 ALOGE("Pre-compositor does not support targeting");
339 hwc_set_cleanup(num_displays, display_contents, composition);
340 return -EINVAL;
341 }
342
343 int target = targeting->CreateTarget(fb_buffer);
344 targeting->SetTarget(target);
345
346 Composition *pre_composition = ctx->pre_compositor.CreateComposition(ctx->importer);
347 if (pre_composition == NULL) {
348 ALOGE("Failed to create pre-composition");
349 targeting->ForgetTarget(target);
350 hwc_set_cleanup(num_displays, display_contents, composition);
351 return -EINVAL;
352 }
353
354 for (j = last_comp_layer; j < (int)num_dc_layers; ++j) {
355 hwc_layer_1_t *layer = &dc->hwLayers[j];
356 if (layer->flags & HWC_SKIP_LAYER)
357 continue;
358 if (layer->compositionType != HWC_OVERLAY)
359 continue;
360 ret = hwc_add_layer(i, ctx, layer, pre_composition);
361 if (ret) {
362 ALOGE("Add layer failed %d", ret);
363 delete pre_composition;
364 targeting->ForgetTarget(target);
365 hwc_set_cleanup(num_displays, display_contents, composition);
366 return ret;
367 }
368 }
369
370 ret = ctx->pre_compositor.QueueComposition(pre_composition);
371 pre_composition = NULL;
372
373 targeting->ForgetTarget(target);
374 if (ret < 0 && ret != -EALREADY) {
375 ALOGE("Pre-composition failed %d", ret);
376 hwc_set_cleanup(num_displays, display_contents, composition);
377 return ret;
378 }
379
380 for (j = last_comp_layer; j < (int)num_dc_layers; ++j) {
381 hwc_layer_1_t *layer = &dc->hwLayers[j];
382 if (layer->flags & HWC_SKIP_LAYER)
383 continue;
384 if (layer->compositionType != HWC_OVERLAY)
385 continue;
386 layer->acquireFenceFd = -1;
387 }
388
389 hwc_layer_1_t composite_layer;
390 hwc_rect_t visible_rect;
391 memset(&composite_layer, 0, sizeof(composite_layer));
392 memset(&visible_rect, 0, sizeof(visible_rect));
393
394 composite_layer.compositionType = HWC_OVERLAY;
395 composite_layer.handle = fb_buffer->getNativeBuffer()->handle;
396 composite_layer.sourceCropf.right = composite_layer.displayFrame.right =
397 visible_rect.right = fb_buffer->getWidth();
398 composite_layer.sourceCropf.bottom = composite_layer.displayFrame.bottom =
399 visible_rect.bottom = fb_buffer->getHeight();
400 composite_layer.visibleRegionScreen.numRects = 1;
401 composite_layer.visibleRegionScreen.rects = &visible_rect;
402 composite_layer.acquireFenceFd = ret == -EALREADY ? -1 : ret;
403 // A known invalid fd in case AddLayer does not modify this field.
404 composite_layer.releaseFenceFd = -1;
405 composite_layer.planeAlpha = 0xff;
406
407 ret = hwc_add_layer(i, ctx, &composite_layer, composition);
408 if (ret) {
409 ALOGE("Add layer failed %d", ret);
410 hwc_set_cleanup(num_displays, display_contents, composition);
411 return ret;
412 }
413
414 fb->set_release_fence_fd(composite_layer.releaseFenceFd);
415 hd->fb_idx = (hd->fb_idx + 1) % HWC_FB_BUFFERS;
416 }
Sean Paulb386f1b2015-05-13 06:33:23 -0700417 }
418
419 ret = ctx->drm.compositor()->QueueComposition(composition);
420 if (ret) {
421 ALOGE("Failed to queue the composition");
422 hwc_set_cleanup(num_displays, display_contents, composition);
423 return ret;
424 }
425 hwc_set_cleanup(num_displays, display_contents, NULL);
Sean Paulef8f1f92015-04-29 16:05:23 -0400426 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500427}
428
Sean Paulef8f1f92015-04-29 16:05:23 -0400429static int hwc_event_control(struct hwc_composer_device_1 *dev, int display,
430 int event, int enabled) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400431 if (event != HWC_EVENT_VSYNC || (enabled != 0 && enabled != 1))
432 return -EINVAL;
Sean Pauleb9e75c2015-01-25 23:31:30 -0500433
Sean Paul4057be32015-05-13 06:23:09 -0700434 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
435 hwc_drm_display_t *hd = &ctx->displays[display];
436 return hd->vsync_worker.VSyncControl(enabled);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500437}
438
Sean Paulef8f1f92015-04-29 16:05:23 -0400439static int hwc_set_power_mode(struct hwc_composer_device_1 *dev, int display,
440 int mode) {
441 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500442
Sean Paul6a55e9f2015-04-30 15:31:06 -0400443 uint64_t dpmsValue = 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400444 switch (mode) {
445 case HWC_POWER_MODE_OFF:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400446 dpmsValue = DRM_MODE_DPMS_OFF;
Sean Paulef8f1f92015-04-29 16:05:23 -0400447 break;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500448
Sean Paulef8f1f92015-04-29 16:05:23 -0400449 /* We can't support dozing right now, so go full on */
450 case HWC_POWER_MODE_DOZE:
451 case HWC_POWER_MODE_DOZE_SUSPEND:
452 case HWC_POWER_MODE_NORMAL:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400453 dpmsValue = DRM_MODE_DPMS_ON;
Sean Paulef8f1f92015-04-29 16:05:23 -0400454 break;
455 };
Sean Paul6a55e9f2015-04-30 15:31:06 -0400456 return ctx->drm.SetDpmsMode(display, dpmsValue);
Sean Paule0c4c3d2015-01-20 16:56:04 -0500457}
458
Sean Paulef8f1f92015-04-29 16:05:23 -0400459static int hwc_query(struct hwc_composer_device_1 * /* dev */, int what,
460 int *value) {
461 switch (what) {
462 case HWC_BACKGROUND_LAYER_SUPPORTED:
463 *value = 0; /* TODO: We should do this */
464 break;
465 case HWC_VSYNC_PERIOD:
466 ALOGW("Query for deprecated vsync value, returning 60Hz");
467 *value = 1000 * 1000 * 1000 / 60;
468 break;
469 case HWC_DISPLAY_TYPES_SUPPORTED:
470 *value = HWC_DISPLAY_PRIMARY | HWC_DISPLAY_EXTERNAL;
471 break;
472 }
473 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500474}
475
Sean Paulef8f1f92015-04-29 16:05:23 -0400476static void hwc_register_procs(struct hwc_composer_device_1 *dev,
477 hwc_procs_t const *procs) {
478 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500479
Sean Paulef8f1f92015-04-29 16:05:23 -0400480 ctx->procs = procs;
Sean Paul4057be32015-05-13 06:23:09 -0700481
482 for (hwc_context_t::DisplayMapIter iter = ctx->displays.begin();
483 iter != ctx->displays.end(); ++iter) {
484 iter->second.vsync_worker.SetProcs(procs);
485 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500486}
487
Sean Paulef8f1f92015-04-29 16:05:23 -0400488static int hwc_get_display_configs(struct hwc_composer_device_1 *dev,
489 int display, uint32_t *configs,
Sean Paul6a55e9f2015-04-30 15:31:06 -0400490 size_t *num_configs) {
491 if (!*num_configs)
Sean Paulef8f1f92015-04-29 16:05:23 -0400492 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500493
Sean Paulef8f1f92015-04-29 16:05:23 -0400494 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700495 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400496 hd->config_ids.clear();
497
498 DrmConnector *connector = ctx->drm.GetConnectorForDisplay(display);
499 if (!connector) {
500 ALOGE("Failed to get connector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400501 return -ENODEV;
502 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500503
Sean Paule42febf2015-05-07 11:35:29 -0700504 int ret = connector->UpdateModes();
Sean Paul6a55e9f2015-04-30 15:31:06 -0400505 if (ret) {
506 ALOGE("Failed to update display modes %d", ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400507 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400508 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500509
Sean Paul6a55e9f2015-04-30 15:31:06 -0400510 for (DrmConnector::ModeIter iter = connector->begin_modes();
511 iter != connector->end_modes(); ++iter) {
512 size_t idx = hd->config_ids.size();
513 if (idx == *num_configs)
514 break;
515 hd->config_ids.push_back(iter->id());
516 configs[idx] = iter->id();
517 }
518 *num_configs = hd->config_ids.size();
519 return *num_configs == 0 ? -1 : 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500520}
521
Sean Paulef8f1f92015-04-29 16:05:23 -0400522static int hwc_get_display_attributes(struct hwc_composer_device_1 *dev,
523 int display, uint32_t config,
524 const uint32_t *attributes,
525 int32_t *values) {
526 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400527 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400528 if (!c) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400529 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400530 return -ENODEV;
531 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400532 DrmMode mode;
533 for (DrmConnector::ModeIter iter = c->begin_modes(); iter != c->end_modes();
534 ++iter) {
535 if (iter->id() == config) {
536 mode = *iter;
537 break;
538 }
539 }
540 if (mode.id() == 0) {
541 ALOGE("Failed to find active mode for display %d", display);
542 return -ENOENT;
Sean Paulef8f1f92015-04-29 16:05:23 -0400543 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500544
Sean Paul6a55e9f2015-04-30 15:31:06 -0400545 uint32_t mm_width = c->mm_width();
546 uint32_t mm_height = c->mm_height();
Sean Paulef8f1f92015-04-29 16:05:23 -0400547 for (int i = 0; attributes[i] != HWC_DISPLAY_NO_ATTRIBUTE; ++i) {
548 switch (attributes[i]) {
549 case HWC_DISPLAY_VSYNC_PERIOD:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400550 values[i] = 1000 * 1000 * 1000 / mode.v_refresh();
Sean Paulef8f1f92015-04-29 16:05:23 -0400551 break;
552 case HWC_DISPLAY_WIDTH:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400553 values[i] = mode.h_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400554 break;
555 case HWC_DISPLAY_HEIGHT:
Sean Paul6a55e9f2015-04-30 15:31:06 -0400556 values[i] = mode.v_display();
Sean Paulef8f1f92015-04-29 16:05:23 -0400557 break;
558 case HWC_DISPLAY_DPI_X:
559 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400560 values[i] = mm_width ? (mode.h_display() * UM_PER_INCH) / mm_width : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400561 break;
562 case HWC_DISPLAY_DPI_Y:
563 /* Dots per 1000 inches */
Sean Paul6a55e9f2015-04-30 15:31:06 -0400564 values[i] =
565 mm_height ? (mode.v_display() * UM_PER_INCH) / mm_height : 0;
Sean Paulef8f1f92015-04-29 16:05:23 -0400566 break;
567 }
568 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400569 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500570}
571
Sean Paulef8f1f92015-04-29 16:05:23 -0400572static int hwc_get_active_config(struct hwc_composer_device_1 *dev,
573 int display) {
574 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paul6a55e9f2015-04-30 15:31:06 -0400575 DrmConnector *c = ctx->drm.GetConnectorForDisplay(display);
576 if (!c) {
577 ALOGE("Failed to get DrmConnector for display %d", display);
Sean Paulef8f1f92015-04-29 16:05:23 -0400578 return -ENODEV;
579 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500580
Sean Paul6a55e9f2015-04-30 15:31:06 -0400581 DrmMode mode = c->active_mode();
Sean Paule42febf2015-05-07 11:35:29 -0700582 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400583 for (size_t i = 0; i < hd->config_ids.size(); ++i) {
584 if (hd->config_ids[i] == mode.id())
585 return i;
Sean Paulef8f1f92015-04-29 16:05:23 -0400586 }
Sean Paul6a55e9f2015-04-30 15:31:06 -0400587 return -1;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500588}
589
Sean Paulef8f1f92015-04-29 16:05:23 -0400590static int hwc_set_active_config(struct hwc_composer_device_1 *dev, int display,
591 int index) {
592 struct hwc_context_t *ctx = (struct hwc_context_t *)&dev->common;
Sean Paule42febf2015-05-07 11:35:29 -0700593 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paul6a55e9f2015-04-30 15:31:06 -0400594 if (index >= (int)hd->config_ids.size()) {
595 ALOGE("Invalid config index %d passed in", index);
596 return -EINVAL;
Sean Paulef8f1f92015-04-29 16:05:23 -0400597 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500598
Zach Reizner45624d32015-06-10 16:03:01 -0700599 int ret = ctx->drm.SetDisplayActiveMode(display, hd->config_ids[index]);
Sean Paul6a55e9f2015-04-30 15:31:06 -0400600 if (ret) {
601 ALOGE("Failed to set config for display %d", display);
602 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400603 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500604
Sean Paul6a55e9f2015-04-30 15:31:06 -0400605 return ret;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500606}
607
Sean Paulef8f1f92015-04-29 16:05:23 -0400608static int hwc_device_close(struct hw_device_t *dev) {
609 struct hwc_context_t *ctx = (struct hwc_context_t *)dev;
Sean Paulef8f1f92015-04-29 16:05:23 -0400610 delete ctx;
Sean Paulef8f1f92015-04-29 16:05:23 -0400611 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500612}
613
Sean Paul24a26e32015-02-04 10:34:47 -0800614/*
615 * TODO: This function sets the active config to the first one in the list. This
616 * should be fixed such that it selects the preferred mode for the display, or
617 * some other, saner, method of choosing the config.
618 */
Sean Paule42febf2015-05-07 11:35:29 -0700619static int hwc_set_initial_config(hwc_drm_display_t *hd) {
Sean Paulef8f1f92015-04-29 16:05:23 -0400620 uint32_t config;
621 size_t num_configs = 1;
622 int ret = hwc_get_display_configs(&hd->ctx->device, hd->display, &config,
623 &num_configs);
624 if (ret || !num_configs)
625 return 0;
Sean Paul24a26e32015-02-04 10:34:47 -0800626
Sean Paulef8f1f92015-04-29 16:05:23 -0400627 ret = hwc_set_active_config(&hd->ctx->device, hd->display, 0);
628 if (ret) {
629 ALOGE("Failed to set active config d=%d ret=%d", hd->display, ret);
630 return ret;
631 }
Sean Paul24a26e32015-02-04 10:34:47 -0800632
Sean Paulef8f1f92015-04-29 16:05:23 -0400633 return ret;
Sean Paul24a26e32015-02-04 10:34:47 -0800634}
635
Sean Paul6a55e9f2015-04-30 15:31:06 -0400636static int hwc_initialize_display(struct hwc_context_t *ctx, int display) {
Sean Paule42febf2015-05-07 11:35:29 -0700637 hwc_drm_display_t *hd = &ctx->displays[display];
Sean Paulef8f1f92015-04-29 16:05:23 -0400638 hd->ctx = ctx;
639 hd->display = display;
Zach Reizner45624d32015-06-10 16:03:01 -0700640 hd->fb_idx = 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500641
Sean Paulb386f1b2015-05-13 06:33:23 -0700642 int ret = hwc_set_initial_config(hd);
Sean Paulef8f1f92015-04-29 16:05:23 -0400643 if (ret) {
644 ALOGE("Failed to set initial config for d=%d ret=%d", display, ret);
Sean Paulef8f1f92015-04-29 16:05:23 -0400645 return ret;
646 }
Sean Paul24a26e32015-02-04 10:34:47 -0800647
Sean Paul4057be32015-05-13 06:23:09 -0700648 ret = hd->vsync_worker.Init(&ctx->drm, display);
649 if (ret) {
650 ALOGE("Failed to create event worker for display %d %d\n", display, ret);
651 return ret;
652 }
653
Sean Paulef8f1f92015-04-29 16:05:23 -0400654 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500655}
656
Sean Paulef8f1f92015-04-29 16:05:23 -0400657static int hwc_enumerate_displays(struct hwc_context_t *ctx) {
Sean Paul6a55e9f2015-04-30 15:31:06 -0400658 int ret;
659 for (DrmResources::ConnectorIter c = ctx->drm.begin_connectors();
660 c != ctx->drm.end_connectors(); ++c) {
661 ret = hwc_initialize_display(ctx, (*c)->display());
662 if (ret) {
663 ALOGE("Failed to initialize display %d", (*c)->display());
664 return ret;
Sean Paulef8f1f92015-04-29 16:05:23 -0400665 }
666 }
Sean Paulef8f1f92015-04-29 16:05:23 -0400667
668 return 0;
Sean Paule0c4c3d2015-01-20 16:56:04 -0500669}
670
Sean Paulef8f1f92015-04-29 16:05:23 -0400671static int hwc_device_open(const struct hw_module_t *module, const char *name,
672 struct hw_device_t **dev) {
673 if (strcmp(name, HWC_HARDWARE_COMPOSER)) {
674 ALOGE("Invalid module name- %s", name);
675 return -EINVAL;
676 }
677
678 struct hwc_context_t *ctx = new hwc_context_t();
679 if (!ctx) {
680 ALOGE("Failed to allocate hwc context");
681 return -ENOMEM;
682 }
683
Sean Paul6a55e9f2015-04-30 15:31:06 -0400684 int ret = ctx->drm.Init();
685 if (ret) {
686 ALOGE("Can't initialize Drm object %d", ret);
687 delete ctx;
688 return ret;
689 }
690
Zach Reizner45624d32015-06-10 16:03:01 -0700691 ret = ctx->pre_compositor.Init();
692 if (ret) {
693 ALOGE("Can't initialize OpenGL Compositor object %d", ret);
694 delete ctx;
695 return ret;
696 }
697
Sean Paulda6270d2015-06-01 14:11:52 -0400698 ctx->importer = Importer::CreateInstance(&ctx->drm);
699 if (!ctx->importer) {
700 ALOGE("Failed to create importer instance");
Sean Paulef8f1f92015-04-29 16:05:23 -0400701 delete ctx;
702 return ret;
703 }
704
Sean Paulef8f1f92015-04-29 16:05:23 -0400705 ret = hwc_enumerate_displays(ctx);
706 if (ret) {
707 ALOGE("Failed to enumerate displays: %s", strerror(ret));
Sean Paul6a55e9f2015-04-30 15:31:06 -0400708 delete ctx;
709 return ret;
710 }
711
Sean Paulef8f1f92015-04-29 16:05:23 -0400712 ctx->device.common.tag = HARDWARE_DEVICE_TAG;
713 ctx->device.common.version = HWC_DEVICE_API_VERSION_1_4;
714 ctx->device.common.module = const_cast<hw_module_t *>(module);
715 ctx->device.common.close = hwc_device_close;
716
717 ctx->device.prepare = hwc_prepare;
718 ctx->device.set = hwc_set;
719 ctx->device.eventControl = hwc_event_control;
720 ctx->device.setPowerMode = hwc_set_power_mode;
721 ctx->device.query = hwc_query;
722 ctx->device.registerProcs = hwc_register_procs;
723 ctx->device.getDisplayConfigs = hwc_get_display_configs;
724 ctx->device.getDisplayAttributes = hwc_get_display_attributes;
725 ctx->device.getActiveConfig = hwc_get_active_config;
726 ctx->device.setActiveConfig = hwc_set_active_config;
727 ctx->device.setCursorPositionAsync = NULL; /* TODO: Add cursor */
728
729 *dev = &ctx->device.common;
730
731 return 0;
732}
Sean Paul6a55e9f2015-04-30 15:31:06 -0400733}
Sean Paulef8f1f92015-04-29 16:05:23 -0400734
Sean Paul6a55e9f2015-04-30 15:31:06 -0400735static struct hw_module_methods_t hwc_module_methods = {
736 open : android::hwc_device_open
737};
Sean Paule0c4c3d2015-01-20 16:56:04 -0500738
739hwc_module_t HAL_MODULE_INFO_SYM = {
Sean Paulef8f1f92015-04-29 16:05:23 -0400740 common : {
741 tag : HARDWARE_MODULE_TAG,
742 version_major : 1,
743 version_minor : 0,
744 id : HWC_HARDWARE_MODULE_ID,
745 name : "DRM hwcomposer module",
746 author : "The Android Open Source Project",
747 methods : &hwc_module_methods,
748 dso : NULL,
749 reserved : {0},
750 }
Sean Paule0c4c3d2015-01-20 16:56:04 -0500751};