blob: c8fab3c5df9ea97431f7ce8d0d7577f267bf1d54 [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _DRM_H_
8#define _DRM_H_
9#ifdef __linux__
10#include <linux/types.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070011#include <asm/ioctl.h>
12typedef unsigned int drm_handle_t;
13#else
Christopher Ferrisb8a95e22019-10-02 18:29:20 -070014#include <stdint.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070015#include <sys/ioccom.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070016#include <sys/types.h>
17typedef int8_t __s8;
18typedef uint8_t __u8;
19typedef int16_t __s16;
Ben Cheng655a7c02013-10-16 16:09:24 -070020typedef uint16_t __u16;
21typedef int32_t __s32;
22typedef uint32_t __u32;
23typedef int64_t __s64;
Ben Cheng655a7c02013-10-16 16:09:24 -070024typedef uint64_t __u64;
Christopher Ferris106b3a82016-08-24 12:15:38 -070025typedef size_t __kernel_size_t;
Ben Cheng655a7c02013-10-16 16:09:24 -070026typedef unsigned long drm_handle_t;
27#endif
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080029extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070030#endif
31#define DRM_NAME "drm"
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define DRM_MIN_ORDER 5
33#define DRM_MAX_ORDER 22
34#define DRM_RAM_PERCENT 10
35#define _DRM_LOCK_HELD 0x80000000U
Ben Cheng655a7c02013-10-16 16:09:24 -070036#define _DRM_LOCK_CONT 0x40000000U
37#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
38#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
Tao Baod7db5942015-01-28 10:07:51 -080039#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD | _DRM_LOCK_CONT))
Ben Cheng655a7c02013-10-16 16:09:24 -070040typedef unsigned int drm_context_t;
41typedef unsigned int drm_drawable_t;
42typedef unsigned int drm_magic_t;
43struct drm_clip_rect {
Tao Baod7db5942015-01-28 10:07:51 -080044 unsigned short x1;
45 unsigned short y1;
46 unsigned short x2;
47 unsigned short y2;
Ben Cheng655a7c02013-10-16 16:09:24 -070048};
49struct drm_drawable_info {
Tao Baod7db5942015-01-28 10:07:51 -080050 unsigned int num_rects;
51 struct drm_clip_rect * rects;
Ben Cheng655a7c02013-10-16 16:09:24 -070052};
53struct drm_tex_region {
Tao Baod7db5942015-01-28 10:07:51 -080054 unsigned char next;
55 unsigned char prev;
Tao Baod7db5942015-01-28 10:07:51 -080056 unsigned char in_use;
57 unsigned char padding;
58 unsigned int age;
Ben Cheng655a7c02013-10-16 16:09:24 -070059};
Ben Cheng655a7c02013-10-16 16:09:24 -070060struct drm_hw_lock {
Tao Baod7db5942015-01-28 10:07:51 -080061 __volatile__ unsigned int lock;
62 char padding[60];
Ben Cheng655a7c02013-10-16 16:09:24 -070063};
Ben Cheng655a7c02013-10-16 16:09:24 -070064struct drm_version {
Tao Baod7db5942015-01-28 10:07:51 -080065 int version_major;
66 int version_minor;
67 int version_patchlevel;
Christopher Ferris106b3a82016-08-24 12:15:38 -070068 __kernel_size_t name_len;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070069 char * name;
Christopher Ferris106b3a82016-08-24 12:15:38 -070070 __kernel_size_t date_len;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070071 char * date;
Christopher Ferris106b3a82016-08-24 12:15:38 -070072 __kernel_size_t desc_len;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070073 char * desc;
Ben Cheng655a7c02013-10-16 16:09:24 -070074};
75struct drm_unique {
Christopher Ferris106b3a82016-08-24 12:15:38 -070076 __kernel_size_t unique_len;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070077 char * unique;
Ben Cheng655a7c02013-10-16 16:09:24 -070078};
79struct drm_list {
Tao Baod7db5942015-01-28 10:07:51 -080080 int count;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -070081 struct drm_version * version;
Ben Cheng655a7c02013-10-16 16:09:24 -070082};
83struct drm_block {
Tao Baod7db5942015-01-28 10:07:51 -080084 int unused;
Ben Cheng655a7c02013-10-16 16:09:24 -070085};
86struct drm_control {
Tao Baod7db5942015-01-28 10:07:51 -080087 enum {
Tao Baod7db5942015-01-28 10:07:51 -080088 DRM_ADD_COMMAND,
89 DRM_RM_COMMAND,
90 DRM_INST_HANDLER,
91 DRM_UNINST_HANDLER
Tao Baod7db5942015-01-28 10:07:51 -080092 } func;
93 int irq;
Ben Cheng655a7c02013-10-16 16:09:24 -070094};
95enum drm_map_type {
Tao Baod7db5942015-01-28 10:07:51 -080096 _DRM_FRAME_BUFFER = 0,
97 _DRM_REGISTERS = 1,
98 _DRM_SHM = 2,
99 _DRM_AGP = 3,
Tao Baod7db5942015-01-28 10:07:51 -0800100 _DRM_SCATTER_GATHER = 4,
Christopher Ferris106b3a82016-08-24 12:15:38 -0700101 _DRM_CONSISTENT = 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700102};
Ben Cheng655a7c02013-10-16 16:09:24 -0700103enum drm_map_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800104 _DRM_RESTRICTED = 0x01,
105 _DRM_READ_ONLY = 0x02,
106 _DRM_LOCKED = 0x04,
107 _DRM_KERNEL = 0x08,
Tao Baod7db5942015-01-28 10:07:51 -0800108 _DRM_WRITE_COMBINING = 0x10,
109 _DRM_CONTAINS_LOCK = 0x20,
110 _DRM_REMOVABLE = 0x40,
111 _DRM_DRIVER = 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700112};
113struct drm_ctx_priv_map {
Tao Baod7db5942015-01-28 10:07:51 -0800114 unsigned int ctx_id;
115 void * handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700116};
117struct drm_map {
Tao Baod7db5942015-01-28 10:07:51 -0800118 unsigned long offset;
119 unsigned long size;
Tao Baod7db5942015-01-28 10:07:51 -0800120 enum drm_map_type type;
121 enum drm_map_flags flags;
122 void * handle;
123 int mtrr;
Ben Cheng655a7c02013-10-16 16:09:24 -0700124};
125struct drm_client {
Tao Baod7db5942015-01-28 10:07:51 -0800126 int idx;
127 int auth;
Tao Baod7db5942015-01-28 10:07:51 -0800128 unsigned long pid;
129 unsigned long uid;
130 unsigned long magic;
131 unsigned long iocs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700132};
133enum drm_stat_type {
Tao Baod7db5942015-01-28 10:07:51 -0800134 _DRM_STAT_LOCK,
135 _DRM_STAT_OPENS,
Tao Baod7db5942015-01-28 10:07:51 -0800136 _DRM_STAT_CLOSES,
137 _DRM_STAT_IOCTLS,
138 _DRM_STAT_LOCKS,
139 _DRM_STAT_UNLOCKS,
Tao Baod7db5942015-01-28 10:07:51 -0800140 _DRM_STAT_VALUE,
141 _DRM_STAT_BYTE,
142 _DRM_STAT_COUNT,
143 _DRM_STAT_IRQ,
Tao Baod7db5942015-01-28 10:07:51 -0800144 _DRM_STAT_PRIMARY,
145 _DRM_STAT_SECONDARY,
146 _DRM_STAT_DMA,
147 _DRM_STAT_SPECIAL,
Tao Baod7db5942015-01-28 10:07:51 -0800148 _DRM_STAT_MISSED
Ben Cheng655a7c02013-10-16 16:09:24 -0700149};
150struct drm_stats {
Tao Baod7db5942015-01-28 10:07:51 -0800151 unsigned long count;
Tao Baod7db5942015-01-28 10:07:51 -0800152 struct {
153 unsigned long value;
154 enum drm_stat_type type;
155 } data[15];
Ben Cheng655a7c02013-10-16 16:09:24 -0700156};
157enum drm_lock_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800158 _DRM_LOCK_READY = 0x01,
159 _DRM_LOCK_QUIESCENT = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800160 _DRM_LOCK_FLUSH = 0x04,
161 _DRM_LOCK_FLUSH_ALL = 0x08,
162 _DRM_HALT_ALL_QUEUES = 0x10,
163 _DRM_HALT_CUR_QUEUES = 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700164};
165struct drm_lock {
Tao Baod7db5942015-01-28 10:07:51 -0800166 int context;
167 enum drm_lock_flags flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700168};
169enum drm_dma_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800170 _DRM_DMA_BLOCK = 0x01,
171 _DRM_DMA_WHILE_LOCKED = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800172 _DRM_DMA_PRIORITY = 0x04,
173 _DRM_DMA_WAIT = 0x10,
174 _DRM_DMA_SMALLER_OK = 0x20,
175 _DRM_DMA_LARGER_OK = 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700176};
177struct drm_buf_desc {
Tao Baod7db5942015-01-28 10:07:51 -0800178 int count;
179 int size;
Tao Baod7db5942015-01-28 10:07:51 -0800180 int low_mark;
181 int high_mark;
182 enum {
183 _DRM_PAGE_ALIGN = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800184 _DRM_AGP_BUFFER = 0x02,
185 _DRM_SG_BUFFER = 0x04,
186 _DRM_FB_BUFFER = 0x08,
187 _DRM_PCI_BUFFER_RO = 0x10
Tao Baod7db5942015-01-28 10:07:51 -0800188 } flags;
189 unsigned long agp_start;
Ben Cheng655a7c02013-10-16 16:09:24 -0700190};
Ben Cheng655a7c02013-10-16 16:09:24 -0700191struct drm_buf_info {
Tao Baod7db5942015-01-28 10:07:51 -0800192 int count;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700193 struct drm_buf_desc * list;
Ben Cheng655a7c02013-10-16 16:09:24 -0700194};
Ben Cheng655a7c02013-10-16 16:09:24 -0700195struct drm_buf_free {
Tao Baod7db5942015-01-28 10:07:51 -0800196 int count;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700197 int * list;
Ben Cheng655a7c02013-10-16 16:09:24 -0700198};
Ben Cheng655a7c02013-10-16 16:09:24 -0700199struct drm_buf_pub {
Tao Baod7db5942015-01-28 10:07:51 -0800200 int idx;
201 int total;
202 int used;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700203 void * address;
Ben Cheng655a7c02013-10-16 16:09:24 -0700204};
205struct drm_buf_map {
Tao Baod7db5942015-01-28 10:07:51 -0800206 int count;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700207#ifdef __cplusplus
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700208 void * virt;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700209#else
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700210 void * __linux_virtual;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700211#endif
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700212 struct drm_buf_pub * list;
Ben Cheng655a7c02013-10-16 16:09:24 -0700213};
214struct drm_dma {
Tao Baod7db5942015-01-28 10:07:51 -0800215 int context;
Tao Baod7db5942015-01-28 10:07:51 -0800216 int send_count;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700217 int * send_indices;
218 int * send_sizes;
Tao Baod7db5942015-01-28 10:07:51 -0800219 enum drm_dma_flags flags;
Tao Baod7db5942015-01-28 10:07:51 -0800220 int request_count;
221 int request_size;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700222 int * request_indices;
223 int * request_sizes;
Tao Baod7db5942015-01-28 10:07:51 -0800224 int granted_count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700225};
226enum drm_ctx_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800227 _DRM_CONTEXT_PRESERVED = 0x01,
Tao Baod7db5942015-01-28 10:07:51 -0800228 _DRM_CONTEXT_2DONLY = 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700229};
230struct drm_ctx {
Tao Baod7db5942015-01-28 10:07:51 -0800231 drm_context_t handle;
Tao Baod7db5942015-01-28 10:07:51 -0800232 enum drm_ctx_flags flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700233};
234struct drm_ctx_res {
Tao Baod7db5942015-01-28 10:07:51 -0800235 int count;
Elliott Hughes0f0c18f2023-03-29 15:53:31 -0700236 struct drm_ctx * contexts;
Ben Cheng655a7c02013-10-16 16:09:24 -0700237};
238struct drm_draw {
Tao Baod7db5942015-01-28 10:07:51 -0800239 drm_drawable_t handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700240};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700241typedef enum {
242 DRM_DRAWABLE_CLIPRECTS
243} drm_drawable_info_type_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700244struct drm_update_draw {
Tao Baod7db5942015-01-28 10:07:51 -0800245 drm_drawable_t handle;
246 unsigned int type;
247 unsigned int num;
Tao Baod7db5942015-01-28 10:07:51 -0800248 unsigned long long data;
Ben Cheng655a7c02013-10-16 16:09:24 -0700249};
250struct drm_auth {
Tao Baod7db5942015-01-28 10:07:51 -0800251 drm_magic_t magic;
Ben Cheng655a7c02013-10-16 16:09:24 -0700252};
253struct drm_irq_busid {
Tao Baod7db5942015-01-28 10:07:51 -0800254 int irq;
255 int busnum;
Tao Baod7db5942015-01-28 10:07:51 -0800256 int devnum;
257 int funcnum;
Ben Cheng655a7c02013-10-16 16:09:24 -0700258};
Ben Cheng655a7c02013-10-16 16:09:24 -0700259enum drm_vblank_seq_type {
Tao Baod7db5942015-01-28 10:07:51 -0800260 _DRM_VBLANK_ABSOLUTE = 0x0,
261 _DRM_VBLANK_RELATIVE = 0x1,
262 _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
263 _DRM_VBLANK_EVENT = 0x4000000,
Tao Baod7db5942015-01-28 10:07:51 -0800264 _DRM_VBLANK_FLIP = 0x8000000,
265 _DRM_VBLANK_NEXTONMISS = 0x10000000,
266 _DRM_VBLANK_SECONDARY = 0x20000000,
267 _DRM_VBLANK_SIGNAL = 0x40000000
Ben Cheng655a7c02013-10-16 16:09:24 -0700268};
269#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
270#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
Tao Baod7db5942015-01-28 10:07:51 -0800271#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
Ben Cheng655a7c02013-10-16 16:09:24 -0700272struct drm_wait_vblank_request {
Tao Baod7db5942015-01-28 10:07:51 -0800273 enum drm_vblank_seq_type type;
274 unsigned int sequence;
275 unsigned long signal;
Ben Cheng655a7c02013-10-16 16:09:24 -0700276};
277struct drm_wait_vblank_reply {
Tao Baod7db5942015-01-28 10:07:51 -0800278 enum drm_vblank_seq_type type;
279 unsigned int sequence;
Tao Baod7db5942015-01-28 10:07:51 -0800280 long tval_sec;
281 long tval_usec;
Ben Cheng655a7c02013-10-16 16:09:24 -0700282};
Ben Cheng655a7c02013-10-16 16:09:24 -0700283union drm_wait_vblank {
Tao Baod7db5942015-01-28 10:07:51 -0800284 struct drm_wait_vblank_request request;
285 struct drm_wait_vblank_reply reply;
Ben Cheng655a7c02013-10-16 16:09:24 -0700286};
Ben Cheng655a7c02013-10-16 16:09:24 -0700287#define _DRM_PRE_MODESET 1
288#define _DRM_POST_MODESET 2
289struct drm_modeset_ctl {
Tao Baod7db5942015-01-28 10:07:51 -0800290 __u32 crtc;
291 __u32 cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700292};
293struct drm_agp_mode {
Tao Baod7db5942015-01-28 10:07:51 -0800294 unsigned long mode;
Ben Cheng655a7c02013-10-16 16:09:24 -0700295};
296struct drm_agp_buffer {
Tao Baod7db5942015-01-28 10:07:51 -0800297 unsigned long size;
298 unsigned long handle;
299 unsigned long type;
Tao Baod7db5942015-01-28 10:07:51 -0800300 unsigned long physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700301};
302struct drm_agp_binding {
Tao Baod7db5942015-01-28 10:07:51 -0800303 unsigned long handle;
Tao Baod7db5942015-01-28 10:07:51 -0800304 unsigned long offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700305};
306struct drm_agp_info {
Tao Baod7db5942015-01-28 10:07:51 -0800307 int agp_version_major;
Tao Baod7db5942015-01-28 10:07:51 -0800308 int agp_version_minor;
309 unsigned long mode;
310 unsigned long aperture_base;
311 unsigned long aperture_size;
Tao Baod7db5942015-01-28 10:07:51 -0800312 unsigned long memory_allowed;
313 unsigned long memory_used;
314 unsigned short id_vendor;
315 unsigned short id_device;
Ben Cheng655a7c02013-10-16 16:09:24 -0700316};
317struct drm_scatter_gather {
Tao Baod7db5942015-01-28 10:07:51 -0800318 unsigned long size;
319 unsigned long handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700320};
321struct drm_set_version {
Tao Baod7db5942015-01-28 10:07:51 -0800322 int drm_di_major;
323 int drm_di_minor;
Tao Baod7db5942015-01-28 10:07:51 -0800324 int drm_dd_major;
325 int drm_dd_minor;
Ben Cheng655a7c02013-10-16 16:09:24 -0700326};
Ben Cheng655a7c02013-10-16 16:09:24 -0700327struct drm_gem_close {
Tao Baod7db5942015-01-28 10:07:51 -0800328 __u32 handle;
329 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700330};
Ben Cheng655a7c02013-10-16 16:09:24 -0700331struct drm_gem_flink {
Tao Baod7db5942015-01-28 10:07:51 -0800332 __u32 handle;
333 __u32 name;
Ben Cheng655a7c02013-10-16 16:09:24 -0700334};
Ben Cheng655a7c02013-10-16 16:09:24 -0700335struct drm_gem_open {
Tao Baod7db5942015-01-28 10:07:51 -0800336 __u32 name;
337 __u32 handle;
338 __u64 size;
Ben Cheng655a7c02013-10-16 16:09:24 -0700339};
Christopher Ferris38062f92014-07-09 15:33:25 -0700340#define DRM_CAP_DUMB_BUFFER 0x1
341#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
342#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
343#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
Christopher Ferris38062f92014-07-09 15:33:25 -0700344#define DRM_CAP_PRIME 0x5
345#define DRM_PRIME_CAP_IMPORT 0x1
346#define DRM_PRIME_CAP_EXPORT 0x2
347#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
Christopher Ferris38062f92014-07-09 15:33:25 -0700348#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
349#define DRM_CAP_CURSOR_WIDTH 0x8
350#define DRM_CAP_CURSOR_HEIGHT 0x9
Christopher Ferris05d08e92016-02-04 13:16:38 -0800351#define DRM_CAP_ADDFB2_MODIFIERS 0x10
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800352#define DRM_CAP_PAGE_FLIP_TARGET 0x11
Christopher Ferris525ce912017-07-26 13:12:53 -0700353#define DRM_CAP_CRTC_IN_VBLANK_EVENT 0x12
Christopher Ferris1308ad32017-11-14 17:32:13 -0800354#define DRM_CAP_SYNCOBJ 0x13
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700355#define DRM_CAP_SYNCOBJ_TIMELINE 0x14
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700356#define DRM_CAP_ATOMIC_ASYNC_PAGE_FLIP 0x15
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800357struct drm_get_cap {
Tao Baod7db5942015-01-28 10:07:51 -0800358 __u64 capability;
359 __u64 value;
Ben Cheng655a7c02013-10-16 16:09:24 -0700360};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800361#define DRM_CLIENT_CAP_STEREO_3D 1
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700362#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800363#define DRM_CLIENT_CAP_ATOMIC 3
Christopher Ferris9ce28842018-10-25 12:11:39 -0700364#define DRM_CLIENT_CAP_ASPECT_RATIO 4
365#define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700366#define DRM_CLIENT_CAP_CURSOR_PLANE_HOTSPOT 6
Christopher Ferris38062f92014-07-09 15:33:25 -0700367struct drm_set_client_cap {
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800368 __u64 capability;
Tao Baod7db5942015-01-28 10:07:51 -0800369 __u64 value;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700370};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700371#define DRM_RDWR O_RDWR
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800372#define DRM_CLOEXEC O_CLOEXEC
Ben Cheng655a7c02013-10-16 16:09:24 -0700373struct drm_prime_handle {
Tao Baod7db5942015-01-28 10:07:51 -0800374 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800375 __u32 flags;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800376 __s32 fd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700377};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800378struct drm_syncobj_create {
379 __u32 handle;
380#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
381 __u32 flags;
382};
383struct drm_syncobj_destroy {
384 __u32 handle;
385 __u32 pad;
386};
387#define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
388#define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
389struct drm_syncobj_handle {
390 __u32 handle;
391 __u32 flags;
392 __s32 fd;
393 __u32 pad;
394};
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700395struct drm_syncobj_transfer {
396 __u32 src_handle;
397 __u32 dst_handle;
398 __u64 src_point;
399 __u64 dst_point;
400 __u32 flags;
401 __u32 pad;
402};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800403#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
404#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700405#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2)
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700406#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_DEADLINE (1 << 3)
Christopher Ferris1308ad32017-11-14 17:32:13 -0800407struct drm_syncobj_wait {
408 __u64 handles;
409 __s64 timeout_nsec;
410 __u32 count_handles;
411 __u32 flags;
412 __u32 first_signaled;
413 __u32 pad;
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700414 __u64 deadline_nsec;
Christopher Ferris1308ad32017-11-14 17:32:13 -0800415};
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700416struct drm_syncobj_timeline_wait {
417 __u64 handles;
418 __u64 points;
419 __s64 timeout_nsec;
420 __u32 count_handles;
421 __u32 flags;
422 __u32 first_signaled;
423 __u32 pad;
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700424 __u64 deadline_nsec;
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700425};
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700426struct drm_syncobj_eventfd {
427 __u32 handle;
428 __u32 flags;
429 __u64 point;
430 __s32 fd;
431 __u32 pad;
432};
Christopher Ferris1308ad32017-11-14 17:32:13 -0800433struct drm_syncobj_array {
434 __u64 handles;
435 __u32 count_handles;
436 __u32 pad;
437};
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800438#define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0)
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700439struct drm_syncobj_timeline_array {
440 __u64 handles;
441 __u64 points;
442 __u32 count_handles;
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800443 __u32 flags;
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700444};
Christopher Ferris934ec942018-01-31 15:29:16 -0800445struct drm_crtc_get_sequence {
446 __u32 crtc_id;
447 __u32 active;
448 __u64 sequence;
449 __s64 sequence_ns;
450};
451#define DRM_CRTC_SEQUENCE_RELATIVE 0x00000001
452#define DRM_CRTC_SEQUENCE_NEXT_ON_MISS 0x00000002
453struct drm_crtc_queue_sequence {
454 __u32 crtc_id;
455 __u32 flags;
456 __u64 sequence;
457 __u64 user_data;
458};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700459#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800460}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700461#endif
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800462#include "drm_mode.h"
Christopher Ferris106b3a82016-08-24 12:15:38 -0700463#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800464extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700465#endif
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700466#define DRM_IOCTL_BASE 'd'
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800467#define DRM_IO(nr) _IO(DRM_IOCTL_BASE, nr)
Tao Baod7db5942015-01-28 10:07:51 -0800468#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE, nr, type)
469#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE, nr, type)
Tao Baod7db5942015-01-28 10:07:51 -0800470#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE, nr, type)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800471#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
Ben Cheng655a7c02013-10-16 16:09:24 -0700472#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
Tao Baod7db5942015-01-28 10:07:51 -0800473#define DRM_IOCTL_GET_MAGIC DRM_IOR(0x02, struct drm_auth)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700474#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800475#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
Ben Cheng655a7c02013-10-16 16:09:24 -0700476#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
Tao Baod7db5942015-01-28 10:07:51 -0800477#define DRM_IOCTL_GET_STATS DRM_IOR(0x06, struct drm_stats)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700478#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800479#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
Tao Baod7db5942015-01-28 10:07:51 -0800480#define DRM_IOCTL_GEM_CLOSE DRM_IOW(0x09, struct drm_gem_close)
Ben Cheng655a7c02013-10-16 16:09:24 -0700481#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700482#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800483#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
Tao Baod7db5942015-01-28 10:07:51 -0800484#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW(0x0d, struct drm_set_client_cap)
485#define DRM_IOCTL_SET_UNIQUE DRM_IOW(0x10, struct drm_unique)
Tao Baod7db5942015-01-28 10:07:51 -0800486#define DRM_IOCTL_AUTH_MAGIC DRM_IOW(0x11, struct drm_auth)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800487#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
Ben Cheng655a7c02013-10-16 16:09:24 -0700488#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
Tao Baod7db5942015-01-28 10:07:51 -0800489#define DRM_IOCTL_CONTROL DRM_IOW(0x14, struct drm_control)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700490#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800491#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
Tao Baod7db5942015-01-28 10:07:51 -0800492#define DRM_IOCTL_MARK_BUFS DRM_IOW(0x17, struct drm_buf_desc)
Ben Cheng655a7c02013-10-16 16:09:24 -0700493#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700494#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800495#define DRM_IOCTL_FREE_BUFS DRM_IOW(0x1a, struct drm_buf_free)
Tao Baod7db5942015-01-28 10:07:51 -0800496#define DRM_IOCTL_RM_MAP DRM_IOW(0x1b, struct drm_map)
497#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW(0x1c, struct drm_ctx_priv_map)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700498#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800499#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
Ben Cheng655a7c02013-10-16 16:09:24 -0700500#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
501#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700502#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800503#define DRM_IOCTL_MOD_CTX DRM_IOW(0x22, struct drm_ctx)
Ben Cheng655a7c02013-10-16 16:09:24 -0700504#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
Tao Baod7db5942015-01-28 10:07:51 -0800505#define DRM_IOCTL_SWITCH_CTX DRM_IOW(0x24, struct drm_ctx)
Tao Baod7db5942015-01-28 10:07:51 -0800506#define DRM_IOCTL_NEW_CTX DRM_IOW(0x25, struct drm_ctx)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800507#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
Ben Cheng655a7c02013-10-16 16:09:24 -0700508#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
509#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700510#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800511#define DRM_IOCTL_LOCK DRM_IOW(0x2a, struct drm_lock)
Tao Baod7db5942015-01-28 10:07:51 -0800512#define DRM_IOCTL_UNLOCK DRM_IOW(0x2b, struct drm_lock)
513#define DRM_IOCTL_FINISH DRM_IOW(0x2c, struct drm_lock)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700514#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800515#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
Tao Baod7db5942015-01-28 10:07:51 -0800516#define DRM_IOCTL_AGP_ACQUIRE DRM_IO(0x30)
517#define DRM_IOCTL_AGP_RELEASE DRM_IO(0x31)
Tao Baod7db5942015-01-28 10:07:51 -0800518#define DRM_IOCTL_AGP_ENABLE DRM_IOW(0x32, struct drm_agp_mode)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800519#define DRM_IOCTL_AGP_INFO DRM_IOR(0x33, struct drm_agp_info)
Ben Cheng655a7c02013-10-16 16:09:24 -0700520#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
Tao Baod7db5942015-01-28 10:07:51 -0800521#define DRM_IOCTL_AGP_FREE DRM_IOW(0x35, struct drm_agp_buffer)
Tao Baod7db5942015-01-28 10:07:51 -0800522#define DRM_IOCTL_AGP_BIND DRM_IOW(0x36, struct drm_agp_binding)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800523#define DRM_IOCTL_AGP_UNBIND DRM_IOW(0x37, struct drm_agp_binding)
Ben Cheng655a7c02013-10-16 16:09:24 -0700524#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
Tao Baod7db5942015-01-28 10:07:51 -0800525#define DRM_IOCTL_SG_FREE DRM_IOW(0x39, struct drm_scatter_gather)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700526#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
Christopher Ferris934ec942018-01-31 15:29:16 -0800527#define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
528#define DRM_IOCTL_CRTC_QUEUE_SEQUENCE DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800529#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
Ben Cheng655a7c02013-10-16 16:09:24 -0700530#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
531#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700532#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800533#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
Ben Cheng655a7c02013-10-16 16:09:24 -0700534#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
535#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700536#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800537#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
Ben Cheng655a7c02013-10-16 16:09:24 -0700538#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd)
539#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700540#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800541#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
Ben Cheng655a7c02013-10-16 16:09:24 -0700542#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
543#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700544#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800545#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
Ben Cheng655a7c02013-10-16 16:09:24 -0700546#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
547#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700548#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800549#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
Ben Cheng655a7c02013-10-16 16:09:24 -0700550#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
551#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700552#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800553#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
Ben Cheng655a7c02013-10-16 16:09:24 -0700554#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
555#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700556#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800557#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800558#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
559#define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob)
560#define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
Christopher Ferris1308ad32017-11-14 17:32:13 -0800561#define DRM_IOCTL_SYNCOBJ_CREATE DRM_IOWR(0xBF, struct drm_syncobj_create)
562#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct drm_syncobj_destroy)
563#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct drm_syncobj_handle)
564#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct drm_syncobj_handle)
565#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
566#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct drm_syncobj_array)
567#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
Christopher Ferris934ec942018-01-31 15:29:16 -0800568#define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
569#define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
570#define DRM_IOCTL_MODE_GET_LEASE DRM_IOWR(0xC8, struct drm_mode_get_lease)
571#define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -0700572#define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
573#define DRM_IOCTL_SYNCOBJ_QUERY DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
574#define DRM_IOCTL_SYNCOBJ_TRANSFER DRM_IOWR(0xCC, struct drm_syncobj_transfer)
575#define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
Christopher Ferrisaf09c702020-06-01 20:29:29 -0700576#define DRM_IOCTL_MODE_GETFB2 DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
Christopher Ferris67d1e5e2023-10-31 13:36:37 -0700577#define DRM_IOCTL_SYNCOBJ_EVENTFD DRM_IOWR(0xCF, struct drm_syncobj_eventfd)
Christopher Ferrisb830ddf2024-03-28 11:48:08 -0700578#define DRM_IOCTL_MODE_CLOSEFB DRM_IOWR(0xD0, struct drm_mode_closefb)
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800579#define DRM_COMMAND_BASE 0x40
Christopher Ferris05d08e92016-02-04 13:16:38 -0800580#define DRM_COMMAND_END 0xA0
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700581struct drm_event {
Tao Baod7db5942015-01-28 10:07:51 -0800582 __u32 type;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800583 __u32 length;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800584};
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700585#define DRM_EVENT_VBLANK 0x01
Christopher Ferris38062f92014-07-09 15:33:25 -0700586#define DRM_EVENT_FLIP_COMPLETE 0x02
Christopher Ferris934ec942018-01-31 15:29:16 -0800587#define DRM_EVENT_CRTC_SEQUENCE 0x03
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800588struct drm_event_vblank {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800589 struct drm_event base;
Tao Baod7db5942015-01-28 10:07:51 -0800590 __u64 user_data;
591 __u32 tv_sec;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800592 __u32 tv_usec;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800593 __u32 sequence;
Christopher Ferris525ce912017-07-26 13:12:53 -0700594 __u32 crtc_id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700595};
Christopher Ferris934ec942018-01-31 15:29:16 -0800596struct drm_event_crtc_sequence {
597 struct drm_event base;
598 __u64 user_data;
599 __s64 time_ns;
600 __u64 sequence;
601};
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800602typedef struct drm_clip_rect drm_clip_rect_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800603typedef struct drm_drawable_info drm_drawable_info_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700604typedef struct drm_tex_region drm_tex_region_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700605typedef struct drm_hw_lock drm_hw_lock_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800606typedef struct drm_version drm_version_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800607typedef struct drm_unique drm_unique_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700608typedef struct drm_list drm_list_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700609typedef struct drm_block drm_block_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800610typedef struct drm_control drm_control_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800611typedef enum drm_map_type drm_map_type_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700612typedef enum drm_map_flags drm_map_flags_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700613typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800614typedef struct drm_map drm_map_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800615typedef struct drm_client drm_client_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700616typedef enum drm_stat_type drm_stat_type_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700617typedef struct drm_stats drm_stats_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800618typedef enum drm_lock_flags drm_lock_flags_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800619typedef struct drm_lock drm_lock_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700620typedef enum drm_dma_flags drm_dma_flags_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700621typedef struct drm_buf_desc drm_buf_desc_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800622typedef struct drm_buf_info drm_buf_info_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800623typedef struct drm_buf_free drm_buf_free_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700624typedef struct drm_buf_pub drm_buf_pub_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700625typedef struct drm_buf_map drm_buf_map_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800626typedef struct drm_dma drm_dma_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800627typedef union drm_wait_vblank drm_wait_vblank_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700628typedef struct drm_agp_mode drm_agp_mode_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700629typedef enum drm_ctx_flags drm_ctx_flags_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800630typedef struct drm_ctx drm_ctx_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800631typedef struct drm_ctx_res drm_ctx_res_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700632typedef struct drm_draw drm_draw_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700633typedef struct drm_update_draw drm_update_draw_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800634typedef struct drm_auth drm_auth_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800635typedef struct drm_irq_busid drm_irq_busid_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700636typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700637typedef struct drm_agp_buffer drm_agp_buffer_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800638typedef struct drm_agp_binding drm_agp_binding_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800639typedef struct drm_agp_info drm_agp_info_t;
Christopher Ferrisba8d4f42014-09-03 19:56:49 -0700640typedef struct drm_scatter_gather drm_scatter_gather_t;
Christopher Ferris38062f92014-07-09 15:33:25 -0700641typedef struct drm_set_version drm_set_version_t;
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800642#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800643}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700644#endif
645#endif