blob: e33387d30973fb4c431625e1dda044541db572ab [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _I810_DRM_H_
20#define _I810_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#ifndef _I810_DEFINES_
Christopher Ferris05d08e92016-02-04 13:16:38 -080026#define _I810_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define I810_DMA_BUF_ORDER 12
Tao Baod7db5942015-01-28 10:07:51 -080028#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
Ben Cheng655a7c02013-10-16 16:09:24 -070029#define I810_DMA_BUF_NR 256
Christopher Ferris05d08e92016-02-04 13:16:38 -080030#define I810_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define I810_NR_TEX_REGIONS 64
32#define I810_LOG_MIN_TEX_REGION_SIZE 16
33#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -080034#define I810_UPLOAD_TEX0IMAGE 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define I810_UPLOAD_TEX1IMAGE 0x2
36#define I810_UPLOAD_CTX 0x4
37#define I810_UPLOAD_BUFFERS 0x8
Christopher Ferris05d08e92016-02-04 13:16:38 -080038#define I810_UPLOAD_TEX0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define I810_UPLOAD_TEX1 0x20
40#define I810_UPLOAD_CLIPRECTS 0x40
41#define I810_DESTREG_DI0 0
Christopher Ferris05d08e92016-02-04 13:16:38 -080042#define I810_DESTREG_DI1 1
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define I810_DESTREG_DV0 2
44#define I810_DESTREG_DV1 3
45#define I810_DESTREG_DR0 4
Christopher Ferris05d08e92016-02-04 13:16:38 -080046#define I810_DESTREG_DR1 5
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define I810_DESTREG_DR2 6
48#define I810_DESTREG_DR3 7
49#define I810_DESTREG_DR4 8
Christopher Ferris05d08e92016-02-04 13:16:38 -080050#define I810_DEST_SETUP_SIZE 10
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define I810_CTXREG_CF0 0
52#define I810_CTXREG_CF1 1
53#define I810_CTXREG_ST0 2
Christopher Ferris05d08e92016-02-04 13:16:38 -080054#define I810_CTXREG_ST1 3
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define I810_CTXREG_VF 4
56#define I810_CTXREG_MT 5
57#define I810_CTXREG_MC0 6
Christopher Ferris05d08e92016-02-04 13:16:38 -080058#define I810_CTXREG_MC1 7
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define I810_CTXREG_MC2 8
60#define I810_CTXREG_MA0 9
61#define I810_CTXREG_MA1 10
Christopher Ferris05d08e92016-02-04 13:16:38 -080062#define I810_CTXREG_MA2 11
Ben Cheng655a7c02013-10-16 16:09:24 -070063#define I810_CTXREG_SDM 12
64#define I810_CTXREG_FOG 13
65#define I810_CTXREG_B1 14
Christopher Ferris05d08e92016-02-04 13:16:38 -080066#define I810_CTXREG_B2 15
Ben Cheng655a7c02013-10-16 16:09:24 -070067#define I810_CTXREG_LCS 16
68#define I810_CTXREG_PV 17
69#define I810_CTXREG_ZA 18
Christopher Ferris05d08e92016-02-04 13:16:38 -080070#define I810_CTXREG_AA 19
Ben Cheng655a7c02013-10-16 16:09:24 -070071#define I810_CTX_SETUP_SIZE 20
72#define I810_TEXREG_MI0 0
73#define I810_TEXREG_MI1 1
Christopher Ferris05d08e92016-02-04 13:16:38 -080074#define I810_TEXREG_MI2 2
Ben Cheng655a7c02013-10-16 16:09:24 -070075#define I810_TEXREG_MI3 3
76#define I810_TEXREG_MF 4
77#define I810_TEXREG_MLC 5
Christopher Ferris05d08e92016-02-04 13:16:38 -080078#define I810_TEXREG_MLL 6
Ben Cheng655a7c02013-10-16 16:09:24 -070079#define I810_TEXREG_MCS 7
80#define I810_TEX_SETUP_SIZE 8
81#define I810_FRONT 0x1
Christopher Ferris05d08e92016-02-04 13:16:38 -080082#define I810_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -070083#define I810_DEPTH 0x4
84typedef enum _drm_i810_init_func {
Tao Baod7db5942015-01-28 10:07:51 -080085 I810_INIT_DMA = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 I810_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -080087 I810_INIT_DMA_1_4 = 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -070088} drm_i810_init_func_t;
89typedef struct _drm_i810_init {
Christopher Ferris05d08e92016-02-04 13:16:38 -080090 drm_i810_init_func_t func;
Tao Baod7db5942015-01-28 10:07:51 -080091 unsigned int mmio_offset;
92 unsigned int buffers_offset;
93 int sarea_priv_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080094 unsigned int ring_start;
Tao Baod7db5942015-01-28 10:07:51 -080095 unsigned int ring_end;
96 unsigned int ring_size;
97 unsigned int front_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080098 unsigned int back_offset;
Tao Baod7db5942015-01-28 10:07:51 -080099 unsigned int depth_offset;
100 unsigned int overlay_offset;
101 unsigned int overlay_physical;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800103 unsigned int h;
104 unsigned int pitch;
105 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106} drm_i810_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700107typedef struct _drm_i810_pre12_init {
Tao Baod7db5942015-01-28 10:07:51 -0800108 drm_i810_init_func_t func;
109 unsigned int mmio_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 unsigned int buffers_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800111 int sarea_priv_offset;
112 unsigned int ring_start;
113 unsigned int ring_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114 unsigned int ring_size;
Tao Baod7db5942015-01-28 10:07:51 -0800115 unsigned int front_offset;
116 unsigned int back_offset;
117 unsigned int depth_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800119 unsigned int h;
120 unsigned int pitch;
121 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122} drm_i810_pre12_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700123typedef struct _drm_i810_tex_region {
Tao Baod7db5942015-01-28 10:07:51 -0800124 unsigned char next, prev;
125 unsigned char in_use;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700127} drm_i810_tex_region_t;
128typedef struct _drm_i810_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800129 unsigned int ContextState[I810_CTX_SETUP_SIZE];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130 unsigned int BufferState[I810_DEST_SETUP_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800131 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
132 unsigned int dirty;
133 unsigned int nbox;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
Tao Baod7db5942015-01-28 10:07:51 -0800135 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
136 int texAge;
137 int last_enqueue;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800138 int last_dispatch;
Tao Baod7db5942015-01-28 10:07:51 -0800139 int last_quiescent;
140 int ctxOwner;
141 int vertex_prim;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142 int pf_enabled;
Tao Baod7db5942015-01-28 10:07:51 -0800143 int pf_active;
144 int pf_current_page;
Ben Cheng655a7c02013-10-16 16:09:24 -0700145} drm_i810_sarea_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800146#define DRM_I810_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700147#define DRM_I810_VERTEX 0x01
148#define DRM_I810_CLEAR 0x02
149#define DRM_I810_FLUSH 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800150#define DRM_I810_GETAGE 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700151#define DRM_I810_GETBUF 0x05
152#define DRM_I810_SWAP 0x06
153#define DRM_I810_COPY 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154#define DRM_I810_DOCOPY 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700155#define DRM_I810_OV0INFO 0x09
156#define DRM_I810_FSTATUS 0x0a
157#define DRM_I810_OV0FLIP 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800158#define DRM_I810_MC 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700159#define DRM_I810_RSTATUS 0x0d
160#define DRM_I810_FLIP 0x0e
Tao Baod7db5942015-01-28 10:07:51 -0800161#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800162#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
Tao Baod7db5942015-01-28 10:07:51 -0800163#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
164#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
165#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800166#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
Tao Baod7db5942015-01-28 10:07:51 -0800167#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
168#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
169#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800170#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
Tao Baod7db5942015-01-28 10:07:51 -0800171#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
172#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
173#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800174#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
Tao Baod7db5942015-01-28 10:07:51 -0800175#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700176typedef struct _drm_i810_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800177 int clear_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800178 int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800179 int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700180} drm_i810_clear_t;
181typedef struct _drm_i810_vertex {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800182 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800183 int used;
184 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700185} drm_i810_vertex_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800186typedef struct _drm_i810_copy_t {
Tao Baod7db5942015-01-28 10:07:51 -0800187 int idx;
188 int used;
189 void * address;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800190} drm_i810_copy_t;
Tao Baod7db5942015-01-28 10:07:51 -0800191#define PR_TRIANGLES (0x0 << 18)
192#define PR_TRISTRIP_0 (0x1 << 18)
193#define PR_TRISTRIP_1 (0x2 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800194#define PR_TRIFAN (0x3 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800195#define PR_POLYGON (0x4 << 18)
196#define PR_LINES (0x5 << 18)
197#define PR_LINESTRIP (0x6 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800198#define PR_RECTS (0x7 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800199#define PR_MASK (0x7 << 18)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700200typedef struct drm_i810_dma {
201 void * __linux_virtual;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800202 int request_idx;
Tao Baod7db5942015-01-28 10:07:51 -0800203 int request_size;
204 int granted;
Ben Cheng655a7c02013-10-16 16:09:24 -0700205} drm_i810_dma_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800206typedef struct _drm_i810_overlay_t {
Tao Baod7db5942015-01-28 10:07:51 -0800207 unsigned int offset;
208 unsigned int physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700209} drm_i810_overlay_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800210typedef struct _drm_i810_mc {
Tao Baod7db5942015-01-28 10:07:51 -0800211 int idx;
212 int used;
213 int num_blocks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800214 int * length;
Tao Baod7db5942015-01-28 10:07:51 -0800215 unsigned int last_render;
Ben Cheng655a7c02013-10-16 16:09:24 -0700216} drm_i810_mc_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700217#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800218}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700219#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#endif