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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / drm / i810_drm.h
blob: 9292a802bd2e4eb268d911135cd8a4b83048ae58 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _I810_DRM_H_
20#define _I810_DRM_H_
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]21#include <drm/drm.h>
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]22#ifndef _I810_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]24#define _I810_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#define I810_DMA_BUF_ORDER 12
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]26#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define I810_DMA_BUF_NR 256
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]29#define I810_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30#define I810_NR_TEX_REGIONS 64
31#define I810_LOG_MIN_TEX_REGION_SIZE 16
32#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]34#define I810_UPLOAD_TEX0IMAGE 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]35#define I810_UPLOAD_TEX1IMAGE 0x2
36#define I810_UPLOAD_CTX 0x4
37#define I810_UPLOAD_BUFFERS 0x8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]39#define I810_UPLOAD_TEX0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40#define I810_UPLOAD_TEX1 0x20
41#define I810_UPLOAD_CLIPRECTS 0x40
42#define I810_DESTREG_DI0 0
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]44#define I810_DESTREG_DI1 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]45#define I810_DESTREG_DV0 2
46#define I810_DESTREG_DV1 3
47#define I810_DESTREG_DR0 4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]49#define I810_DESTREG_DR1 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50#define I810_DESTREG_DR2 6
51#define I810_DESTREG_DR3 7
52#define I810_DESTREG_DR4 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]54#define I810_DEST_SETUP_SIZE 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]55#define I810_CTXREG_CF0 0
56#define I810_CTXREG_CF1 1
57#define I810_CTXREG_ST0 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]59#define I810_CTXREG_ST1 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]60#define I810_CTXREG_VF 4
61#define I810_CTXREG_MT 5
62#define I810_CTXREG_MC0 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]64#define I810_CTXREG_MC1 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65#define I810_CTXREG_MC2 8
66#define I810_CTXREG_MA0 9
67#define I810_CTXREG_MA1 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]69#define I810_CTXREG_MA2 11
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]70#define I810_CTXREG_SDM 12
71#define I810_CTXREG_FOG 13
72#define I810_CTXREG_B1 14
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]74#define I810_CTXREG_B2 15
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]75#define I810_CTXREG_LCS 16
76#define I810_CTXREG_PV 17
77#define I810_CTXREG_ZA 18
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]79#define I810_CTXREG_AA 19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80#define I810_CTX_SETUP_SIZE 20
81#define I810_TEXREG_MI0 0
82#define I810_TEXREG_MI1 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]84#define I810_TEXREG_MI2 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85#define I810_TEXREG_MI3 3
86#define I810_TEXREG_MF 4
87#define I810_TEXREG_MLC 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]89#define I810_TEXREG_MLL 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]90#define I810_TEXREG_MCS 7
91#define I810_TEX_SETUP_SIZE 8
92#define I810_FRONT 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]94#define I810_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95#define I810_DEPTH 0x4
96typedef enum _drm_i810_init_func {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 I810_INIT_DMA = 0x01,
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]99 I810_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]100 I810_INIT_DMA_1_4 = 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]101} drm_i810_init_func_t;
102typedef struct _drm_i810_init {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]104 drm_i810_init_func_t func;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]105 unsigned int mmio_offset;
106 unsigned int buffers_offset;
107 int sarea_priv_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]109 unsigned int ring_start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 unsigned int ring_end;
111 unsigned int ring_size;
112 unsigned int front_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]114 unsigned int back_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]115 unsigned int depth_offset;
116 unsigned int overlay_offset;
117 unsigned int overlay_physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]119 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]120 unsigned int h;
121 unsigned int pitch;
122 unsigned int pitch_bits;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]124} drm_i810_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]125typedef struct _drm_i810_pre12_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]126 drm_i810_init_func_t func;
127 unsigned int mmio_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]129 unsigned int buffers_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]130 int sarea_priv_offset;
131 unsigned int ring_start;
132 unsigned int ring_end;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]134 unsigned int ring_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]135 unsigned int front_offset;
136 unsigned int back_offset;
137 unsigned int depth_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]139 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140 unsigned int h;
141 unsigned int pitch;
142 unsigned int pitch_bits;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]144} drm_i810_pre12_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]145typedef struct _drm_i810_tex_region {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]146 unsigned char next, prev;
147 unsigned char in_use;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]149 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]150} drm_i810_tex_region_t;
151typedef struct _drm_i810_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]152 unsigned int ContextState[I810_CTX_SETUP_SIZE];
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]154 unsigned int BufferState[I810_DEST_SETUP_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
156 unsigned int dirty;
157 unsigned int nbox;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]159 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]160 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
161 int texAge;
162 int last_enqueue;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]164 int last_dispatch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 int last_quiescent;
166 int ctxOwner;
167 int vertex_prim;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]169 int pf_enabled;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]170 int pf_active;
171 int pf_current_page;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]172} drm_i810_sarea_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]174#define DRM_I810_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]175#define DRM_I810_VERTEX 0x01
176#define DRM_I810_CLEAR 0x02
177#define DRM_I810_FLUSH 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]179#define DRM_I810_GETAGE 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]180#define DRM_I810_GETBUF 0x05
181#define DRM_I810_SWAP 0x06
182#define DRM_I810_COPY 0x07
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]184#define DRM_I810_DOCOPY 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]185#define DRM_I810_OV0INFO 0x09
186#define DRM_I810_FSTATUS 0x0a
187#define DRM_I810_OV0FLIP 0x0b
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]189#define DRM_I810_MC 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]190#define DRM_I810_RSTATUS 0x0d
191#define DRM_I810_FLIP 0x0e
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]192#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]194#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]195#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
196#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
197#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]199#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]200#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
201#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
202#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]204#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]205#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
206#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
207#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]209#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]210#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]211typedef struct _drm_i810_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]212 int clear_color;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]214 int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]215 int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]216} drm_i810_clear_t;
217typedef struct _drm_i810_vertex {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]219 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]220 int used;
221 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]222} drm_i810_vertex_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]224typedef struct _drm_i810_copy_t {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]225 int idx;
226 int used;
227 void * address;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]229} drm_i810_copy_t;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]230#define PR_TRIANGLES (0x0 << 18)
231#define PR_TRISTRIP_0 (0x1 << 18)
232#define PR_TRISTRIP_1 (0x2 << 18)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]234#define PR_TRIFAN (0x3 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]235#define PR_POLYGON (0x4 << 18)
236#define PR_LINES (0x5 << 18)
237#define PR_LINESTRIP (0x6 << 18)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]239#define PR_RECTS (0x7 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]240#define PR_MASK (0x7 << 18)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]241typedef struct drm_i810_dma {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]242 void * virtual;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]244 int request_idx;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]245 int request_size;
246 int granted;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]247} drm_i810_dma_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]249typedef struct _drm_i810_overlay_t {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]250 unsigned int offset;
251 unsigned int physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]252} drm_i810_overlay_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]254typedef struct _drm_i810_mc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]255 int idx;
256 int used;
257 int num_blocks;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]259 int * length;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]260 unsigned int last_render;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]261} drm_i810_mc_t;
262#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */