Gitiles
Code Review Sign In
gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / i810_drm.h
blob: ad2fdcf2324ef9b40dfc06c258cb32f59f98fed5 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _I810_DRM_H_
20#define _I810_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
25#ifndef _I810_DEFINES_
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]26#define _I810_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27#define I810_DMA_BUF_ORDER 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]29#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30#define I810_DMA_BUF_NR 256
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]31#define I810_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32#define I810_NR_TEX_REGIONS 64
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34#define I810_LOG_MIN_TEX_REGION_SIZE 16
35#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]36#define I810_UPLOAD_TEX0IMAGE 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]37#define I810_UPLOAD_TEX1IMAGE 0x2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39#define I810_UPLOAD_CTX 0x4
40#define I810_UPLOAD_BUFFERS 0x8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]41#define I810_UPLOAD_TEX0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]42#define I810_UPLOAD_TEX1 0x20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44#define I810_UPLOAD_CLIPRECTS 0x40
45#define I810_DESTREG_DI0 0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]46#define I810_DESTREG_DI1 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]47#define I810_DESTREG_DV0 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49#define I810_DESTREG_DV1 3
50#define I810_DESTREG_DR0 4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]51#define I810_DESTREG_DR1 5
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]52#define I810_DESTREG_DR2 6
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]54#define I810_DESTREG_DR3 7
55#define I810_DESTREG_DR4 8
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]56#define I810_DEST_SETUP_SIZE 10
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]57#define I810_CTXREG_CF0 0
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59#define I810_CTXREG_CF1 1
60#define I810_CTXREG_ST0 2
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]61#define I810_CTXREG_ST1 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]62#define I810_CTXREG_VF 4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64#define I810_CTXREG_MT 5
65#define I810_CTXREG_MC0 6
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]66#define I810_CTXREG_MC1 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]67#define I810_CTXREG_MC2 8
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69#define I810_CTXREG_MA0 9
70#define I810_CTXREG_MA1 10
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]71#define I810_CTXREG_MA2 11
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]72#define I810_CTXREG_SDM 12
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]74#define I810_CTXREG_FOG 13
75#define I810_CTXREG_B1 14
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]76#define I810_CTXREG_B2 15
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]77#define I810_CTXREG_LCS 16
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]79#define I810_CTXREG_PV 17
80#define I810_CTXREG_ZA 18
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]81#define I810_CTXREG_AA 19
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]82#define I810_CTX_SETUP_SIZE 20
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]84#define I810_TEXREG_MI0 0
85#define I810_TEXREG_MI1 1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]86#define I810_TEXREG_MI2 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]87#define I810_TEXREG_MI3 3
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]89#define I810_TEXREG_MF 4
90#define I810_TEXREG_MLC 5
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]91#define I810_TEXREG_MLL 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92#define I810_TEXREG_MCS 7
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94#define I810_TEX_SETUP_SIZE 8
95#define I810_FRONT 0x1
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]96#define I810_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]97#define I810_DEPTH 0x4
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]99typedef enum _drm_i810_init_func {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]100 I810_INIT_DMA = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]101 I810_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102 I810_INIT_DMA_1_4 = 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]104} drm_i810_init_func_t;
105typedef struct _drm_i810_init {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]106 drm_i810_init_func_t func;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]107 unsigned int mmio_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]109 unsigned int buffers_offset;
110 int sarea_priv_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]111 unsigned int ring_start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]112 unsigned int ring_end;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 unsigned int ring_size;
115 unsigned int front_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]116 unsigned int back_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 unsigned int depth_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 unsigned int overlay_offset;
120 unsigned int overlay_physical;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]121 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]122 unsigned int h;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]124 unsigned int pitch;
125 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]126} drm_i810_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]127typedef struct _drm_i810_pre12_init {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]129 drm_i810_init_func_t func;
130 unsigned int mmio_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]131 unsigned int buffers_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]132 int sarea_priv_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]134 unsigned int ring_start;
135 unsigned int ring_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]136 unsigned int ring_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]137 unsigned int front_offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]139 unsigned int back_offset;
140 unsigned int depth_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]141 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]142 unsigned int h;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 unsigned int pitch;
145 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]146} drm_i810_pre12_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]147typedef struct _drm_i810_tex_region {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149 unsigned char next, prev;
150 unsigned char in_use;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]151 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]152} drm_i810_tex_region_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]154typedef struct _drm_i810_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 unsigned int ContextState[I810_CTX_SETUP_SIZE];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]156 unsigned int BufferState[I810_DEST_SETUP_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]157 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]159 unsigned int dirty;
160 unsigned int nbox;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]161 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]162 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]164 int texAge;
165 int last_enqueue;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]166 int last_dispatch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]167 int last_quiescent;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]169 int ctxOwner;
170 int vertex_prim;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]171 int pf_enabled;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]172 int pf_active;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]174 int pf_current_page;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]175} drm_i810_sarea_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]176#define DRM_I810_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]177#define DRM_I810_VERTEX 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]179#define DRM_I810_CLEAR 0x02
180#define DRM_I810_FLUSH 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]181#define DRM_I810_GETAGE 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182#define DRM_I810_GETBUF 0x05
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_I810_SWAP 0x06
185#define DRM_I810_COPY 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]186#define DRM_I810_DOCOPY 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]187#define DRM_I810_OV0INFO 0x09
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define DRM_I810_FSTATUS 0x0a
190#define DRM_I810_OV0FLIP 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]191#define DRM_I810_MC 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]192#define DRM_I810_RSTATUS 0x0d
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define DRM_I810_FLIP 0x0e
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]195#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]196#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]197#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]199#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
200#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]201#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]202#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]204#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
205#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]206#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]207#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]208/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]209#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
210#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]211#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]212#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]213/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]214typedef struct _drm_i810_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]215 int clear_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]216 int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]217 int flags;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]218/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]219} drm_i810_clear_t;
220typedef struct _drm_i810_vertex {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]221 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]222 int used;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]223/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]224 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]225} drm_i810_vertex_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]226typedef struct _drm_i810_copy_t {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]227 int idx;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]228/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]229 int used;
230 void * address;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]231} drm_i810_copy_t;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]232#define PR_TRIANGLES (0x0 << 18)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]233/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]234#define PR_TRISTRIP_0 (0x1 << 18)
235#define PR_TRISTRIP_1 (0x2 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]236#define PR_TRIFAN (0x3 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]237#define PR_POLYGON (0x4 << 18)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]238/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]239#define PR_LINES (0x5 << 18)
240#define PR_LINESTRIP (0x6 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]241#define PR_RECTS (0x7 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]242#define PR_MASK (0x7 << 18)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]243/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]244typedef struct drm_i810_dma {
245 void * __linux_virtual;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]246 int request_idx;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]247 int request_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]248/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]249 int granted;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]250} drm_i810_dma_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]251typedef struct _drm_i810_overlay_t {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]252 unsigned int offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]253/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]254 unsigned int physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]255} drm_i810_overlay_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]256typedef struct _drm_i810_mc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]257 int idx;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]258/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]259 int used;
260 int num_blocks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]261 int * length;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]262 unsigned int last_render;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]263/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]264} drm_i810_mc_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]265#ifdef __cplusplus
266#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]267#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]268/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */