blob: ae87d21b44a9d07e0f62bbe2d09001d4c7d9302f [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __SAVAGE_DRM_H__
20#define __SAVAGE_DRM_H__
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#ifndef __SAVAGE_SAREA_DEFINES__
Christopher Ferris05d08e92016-02-04 13:16:38 -080026#define __SAVAGE_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define SAVAGE_CARD_HEAP 0
28#define SAVAGE_AGP_HEAP 1
29#define SAVAGE_NR_TEX_HEAPS 2
Christopher Ferris05d08e92016-02-04 13:16:38 -080030#define SAVAGE_NR_TEX_REGIONS 16
Ben Cheng655a7c02013-10-16 16:09:24 -070031#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
32#endif
33typedef struct _drm_savage_sarea {
Christopher Ferris05d08e92016-02-04 13:16:38 -080034 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -080035 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
36 int ctxOwner;
37} drm_savage_sarea_t, * drm_savage_sarea_ptr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080038#define DRM_SAVAGE_BCI_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define DRM_SAVAGE_BCI_CMDBUF 0x01
40#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
41#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -080042#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
Tao Baod7db5942015-01-28 10:07:51 -080043#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
Ben Cheng655a7c02013-10-16 16:09:24 -070044#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
Tao Baod7db5942015-01-28 10:07:51 -080045#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -080046#define SAVAGE_DMA_PCI 1
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define SAVAGE_DMA_AGP 3
48typedef struct drm_savage_init {
Tao Baod7db5942015-01-28 10:07:51 -080049 enum {
Christopher Ferris05d08e92016-02-04 13:16:38 -080050 SAVAGE_INIT_BCI = 1,
Tao Baod7db5942015-01-28 10:07:51 -080051 SAVAGE_CLEANUP_BCI = 2
52 } func;
53 unsigned int sarea_priv_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080054 unsigned int cob_size;
Tao Baod7db5942015-01-28 10:07:51 -080055 unsigned int bci_threshold_lo, bci_threshold_hi;
56 unsigned int dma_type;
57 unsigned int fb_bpp;
Christopher Ferris05d08e92016-02-04 13:16:38 -080058 unsigned int front_offset, front_pitch;
Tao Baod7db5942015-01-28 10:07:51 -080059 unsigned int back_offset, back_pitch;
60 unsigned int depth_bpp;
61 unsigned int depth_offset, depth_pitch;
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 unsigned int texture_offset;
Tao Baod7db5942015-01-28 10:07:51 -080063 unsigned int texture_size;
64 unsigned long status_offset;
65 unsigned long buffers_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 unsigned long agp_textures_offset;
Tao Baod7db5942015-01-28 10:07:51 -080067 unsigned long cmd_dma_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070068} drm_savage_init_t;
69typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -080070typedef struct drm_savage_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -080071 drm_savage_cmd_header_t __user * cmd_addr;
72 unsigned int size;
73 unsigned int dma_idx;
Christopher Ferris05d08e92016-02-04 13:16:38 -080074 int discard;
Tao Baod7db5942015-01-28 10:07:51 -080075 unsigned int __user * vb_addr;
76 unsigned int vb_size;
77 unsigned int vb_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 struct drm_clip_rect __user * box_addr;
Tao Baod7db5942015-01-28 10:07:51 -080079 unsigned int nbox;
Ben Cheng655a7c02013-10-16 16:09:24 -070080} drm_savage_cmdbuf_t;
81#define SAVAGE_WAIT_2D 0x1
Christopher Ferris05d08e92016-02-04 13:16:38 -080082#define SAVAGE_WAIT_3D 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -070083#define SAVAGE_WAIT_IRQ 0x4
84typedef struct drm_savage_event {
Tao Baod7db5942015-01-28 10:07:51 -080085 unsigned int count;
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 unsigned int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -070087} drm_savage_event_emit_t, drm_savage_event_wait_t;
88#define SAVAGE_CMD_STATE 0
89#define SAVAGE_CMD_DMA_PRIM 1
Christopher Ferris05d08e92016-02-04 13:16:38 -080090#define SAVAGE_CMD_VB_PRIM 2
Ben Cheng655a7c02013-10-16 16:09:24 -070091#define SAVAGE_CMD_DMA_IDX 3
92#define SAVAGE_CMD_VB_IDX 4
93#define SAVAGE_CMD_CLEAR 5
Christopher Ferris05d08e92016-02-04 13:16:38 -080094#define SAVAGE_CMD_SWAP 6
Ben Cheng655a7c02013-10-16 16:09:24 -070095#define SAVAGE_PRIM_TRILIST 0
96#define SAVAGE_PRIM_TRISTRIP 1
97#define SAVAGE_PRIM_TRIFAN 2
Christopher Ferris05d08e92016-02-04 13:16:38 -080098#define SAVAGE_PRIM_TRILIST_201 3
Ben Cheng655a7c02013-10-16 16:09:24 -070099#define SAVAGE_SKIP_Z 0x01
100#define SAVAGE_SKIP_W 0x02
101#define SAVAGE_SKIP_C0 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102#define SAVAGE_SKIP_C1 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700103#define SAVAGE_SKIP_S0 0x10
104#define SAVAGE_SKIP_T0 0x20
105#define SAVAGE_SKIP_ST0 0x30
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106#define SAVAGE_SKIP_S1 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700107#define SAVAGE_SKIP_T1 0x80
108#define SAVAGE_SKIP_ST1 0xc0
109#define SAVAGE_SKIP_ALL_S3D 0x3f
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110#define SAVAGE_SKIP_ALL_S4 0xff
Ben Cheng655a7c02013-10-16 16:09:24 -0700111#define SAVAGE_FRONT 0x1
112#define SAVAGE_BACK 0x2
113#define SAVAGE_DEPTH 0x4
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114union drm_savage_cmd_header {
Tao Baod7db5942015-01-28 10:07:51 -0800115 struct {
116 unsigned char cmd;
117 unsigned char pad0;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118 unsigned short pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800119 unsigned short pad2;
120 unsigned short pad3;
121 } cmd;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800123 unsigned char cmd;
124 unsigned char global;
125 unsigned short count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126 unsigned short start;
Tao Baod7db5942015-01-28 10:07:51 -0800127 unsigned short pad3;
128 } state;
129 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800130 unsigned char cmd;
Tao Baod7db5942015-01-28 10:07:51 -0800131 unsigned char prim;
132 unsigned short skip;
133 unsigned short count;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800134 unsigned short start;
Tao Baod7db5942015-01-28 10:07:51 -0800135 } prim;
136 struct {
137 unsigned char cmd;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800138 unsigned char prim;
Tao Baod7db5942015-01-28 10:07:51 -0800139 unsigned short skip;
140 unsigned short count;
141 unsigned short pad3;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142 } idx;
Tao Baod7db5942015-01-28 10:07:51 -0800143 struct {
144 unsigned char cmd;
145 unsigned char pad0;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800146 unsigned short pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800147 unsigned int flags;
148 } clear0;
149 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800150 unsigned int mask;
Tao Baod7db5942015-01-28 10:07:51 -0800151 unsigned int value;
152 } clear1;
Ben Cheng655a7c02013-10-16 16:09:24 -0700153};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700154#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800155}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700156#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800157#endif