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gerrit.omnirom.org / android_bionic / 05d08e9716b5974d6ed08973f44930804890b902 / . / libc / kernel / uapi / drm / savage_drm.h
blob: eba99a3bcb34b985a79093888fced8900bcffd6c [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef __SAVAGE_DRM_H__
20#define __SAVAGE_DRM_H__
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]21#include <drm/drm.h>
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]22#ifndef __SAVAGE_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]24#define __SAVAGE_SAREA_DEFINES__
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]25#define SAVAGE_CARD_HEAP 0
26#define SAVAGE_AGP_HEAP 1
27#define SAVAGE_NR_TEX_HEAPS 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]29#define SAVAGE_NR_TEX_REGIONS 16
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]30#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
31#endif
32typedef struct _drm_savage_sarea {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]34 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS + 1];
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]35 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
36 int ctxOwner;
37} drm_savage_sarea_t, * drm_savage_sarea_ptr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]39#define DRM_SAVAGE_BCI_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40#define DRM_SAVAGE_BCI_CMDBUF 0x01
41#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
42#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]44#define DRM_IOCTL_SAVAGE_BCI_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]45#define DRM_IOCTL_SAVAGE_BCI_CMDBUF DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]46#define DRM_IOCTL_SAVAGE_BCI_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]47#define DRM_IOCTL_SAVAGE_BCI_EVENT_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]49#define SAVAGE_DMA_PCI 1
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50#define SAVAGE_DMA_AGP 3
51typedef struct drm_savage_init {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52 enum {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]54 SAVAGE_INIT_BCI = 1,
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]55 SAVAGE_CLEANUP_BCI = 2
56 } func;
57 unsigned int sarea_priv_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]59 unsigned int cob_size;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]60 unsigned int bci_threshold_lo, bci_threshold_hi;
61 unsigned int dma_type;
62 unsigned int fb_bpp;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]64 unsigned int front_offset, front_pitch;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]65 unsigned int back_offset, back_pitch;
66 unsigned int depth_bpp;
67 unsigned int depth_offset, depth_pitch;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]69 unsigned int texture_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]70 unsigned int texture_size;
71 unsigned long status_offset;
72 unsigned long buffers_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]74 unsigned long agp_textures_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]75 unsigned long cmd_dma_offset;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]76} drm_savage_init_t;
77typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]79typedef struct drm_savage_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]80 drm_savage_cmd_header_t __user * cmd_addr;
81 unsigned int size;
82 unsigned int dma_idx;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]84 int discard;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]85 unsigned int __user * vb_addr;
86 unsigned int vb_size;
87 unsigned int vb_stride;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]89 struct drm_clip_rect __user * box_addr;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]90 unsigned int nbox;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]91} drm_savage_cmdbuf_t;
92#define SAVAGE_WAIT_2D 0x1
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]94#define SAVAGE_WAIT_3D 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]95#define SAVAGE_WAIT_IRQ 0x4
96typedef struct drm_savage_event {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 unsigned int count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]99 unsigned int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]100} drm_savage_event_emit_t, drm_savage_event_wait_t;
101#define SAVAGE_CMD_STATE 0
102#define SAVAGE_CMD_DMA_PRIM 1
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]104#define SAVAGE_CMD_VB_PRIM 2
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]105#define SAVAGE_CMD_DMA_IDX 3
106#define SAVAGE_CMD_VB_IDX 4
107#define SAVAGE_CMD_CLEAR 5
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]109#define SAVAGE_CMD_SWAP 6
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]110#define SAVAGE_PRIM_TRILIST 0
111#define SAVAGE_PRIM_TRISTRIP 1
112#define SAVAGE_PRIM_TRIFAN 2
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]114#define SAVAGE_PRIM_TRILIST_201 3
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115#define SAVAGE_SKIP_Z 0x01
116#define SAVAGE_SKIP_W 0x02
117#define SAVAGE_SKIP_C0 0x04
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]119#define SAVAGE_SKIP_C1 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]120#define SAVAGE_SKIP_S0 0x10
121#define SAVAGE_SKIP_T0 0x20
122#define SAVAGE_SKIP_ST0 0x30
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]124#define SAVAGE_SKIP_S1 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]125#define SAVAGE_SKIP_T1 0x80
126#define SAVAGE_SKIP_ST1 0xc0
127#define SAVAGE_SKIP_ALL_S3D 0x3f
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]129#define SAVAGE_SKIP_ALL_S4 0xff
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]130#define SAVAGE_FRONT 0x1
131#define SAVAGE_BACK 0x2
132#define SAVAGE_DEPTH 0x4
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]134union drm_savage_cmd_header {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]135 struct {
136 unsigned char cmd;
137 unsigned char pad0;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]139 unsigned short pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140 unsigned short pad2;
141 unsigned short pad3;
142 } cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]144 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]145 unsigned char cmd;
146 unsigned char global;
147 unsigned short count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]149 unsigned short start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]150 unsigned short pad3;
151 } state;
152 struct {
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]154 unsigned char cmd;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]155 unsigned char prim;
156 unsigned short skip;
157 unsigned short count;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]159 unsigned short start;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]160 } prim;
161 struct {
162 unsigned char cmd;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]164 unsigned char prim;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]165 unsigned short skip;
166 unsigned short count;
167 unsigned short pad3;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]169 } idx;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]170 struct {
171 unsigned char cmd;
172 unsigned char pad0;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]174 unsigned short pad1;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]175 unsigned int flags;
176 } clear0;
177 struct {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]179 unsigned int mask;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]180 unsigned int value;
181 } clear1;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]182};
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame^]184#endif