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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _I810_DRM_H_
20#define _I810_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris106b3a82016-08-24 12:15:38 -070023#endif
24#ifndef _I810_DEFINES_
Christopher Ferris05d08e92016-02-04 13:16:38 -080025#define _I810_DEFINES_
Ben Cheng655a7c02013-10-16 16:09:24 -070026#define I810_DMA_BUF_ORDER 12
Tao Baod7db5942015-01-28 10:07:51 -080027#define I810_DMA_BUF_SZ (1 << I810_DMA_BUF_ORDER)
Ben Cheng655a7c02013-10-16 16:09:24 -070028#define I810_DMA_BUF_NR 256
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define I810_NR_SAREA_CLIPRECTS 8
Ben Cheng655a7c02013-10-16 16:09:24 -070030#define I810_NR_TEX_REGIONS 64
31#define I810_LOG_MIN_TEX_REGION_SIZE 16
32#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -080033#define I810_UPLOAD_TEX0IMAGE 0x1
Ben Cheng655a7c02013-10-16 16:09:24 -070034#define I810_UPLOAD_TEX1IMAGE 0x2
35#define I810_UPLOAD_CTX 0x4
36#define I810_UPLOAD_BUFFERS 0x8
Christopher Ferris05d08e92016-02-04 13:16:38 -080037#define I810_UPLOAD_TEX0 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070038#define I810_UPLOAD_TEX1 0x20
39#define I810_UPLOAD_CLIPRECTS 0x40
40#define I810_DESTREG_DI0 0
Christopher Ferris05d08e92016-02-04 13:16:38 -080041#define I810_DESTREG_DI1 1
Ben Cheng655a7c02013-10-16 16:09:24 -070042#define I810_DESTREG_DV0 2
43#define I810_DESTREG_DV1 3
44#define I810_DESTREG_DR0 4
Christopher Ferris05d08e92016-02-04 13:16:38 -080045#define I810_DESTREG_DR1 5
Ben Cheng655a7c02013-10-16 16:09:24 -070046#define I810_DESTREG_DR2 6
47#define I810_DESTREG_DR3 7
48#define I810_DESTREG_DR4 8
Christopher Ferris05d08e92016-02-04 13:16:38 -080049#define I810_DEST_SETUP_SIZE 10
Ben Cheng655a7c02013-10-16 16:09:24 -070050#define I810_CTXREG_CF0 0
51#define I810_CTXREG_CF1 1
52#define I810_CTXREG_ST0 2
Christopher Ferris05d08e92016-02-04 13:16:38 -080053#define I810_CTXREG_ST1 3
Ben Cheng655a7c02013-10-16 16:09:24 -070054#define I810_CTXREG_VF 4
55#define I810_CTXREG_MT 5
56#define I810_CTXREG_MC0 6
Christopher Ferris05d08e92016-02-04 13:16:38 -080057#define I810_CTXREG_MC1 7
Ben Cheng655a7c02013-10-16 16:09:24 -070058#define I810_CTXREG_MC2 8
59#define I810_CTXREG_MA0 9
60#define I810_CTXREG_MA1 10
Christopher Ferris05d08e92016-02-04 13:16:38 -080061#define I810_CTXREG_MA2 11
Ben Cheng655a7c02013-10-16 16:09:24 -070062#define I810_CTXREG_SDM 12
63#define I810_CTXREG_FOG 13
64#define I810_CTXREG_B1 14
Christopher Ferris05d08e92016-02-04 13:16:38 -080065#define I810_CTXREG_B2 15
Ben Cheng655a7c02013-10-16 16:09:24 -070066#define I810_CTXREG_LCS 16
67#define I810_CTXREG_PV 17
68#define I810_CTXREG_ZA 18
Christopher Ferris05d08e92016-02-04 13:16:38 -080069#define I810_CTXREG_AA 19
Ben Cheng655a7c02013-10-16 16:09:24 -070070#define I810_CTX_SETUP_SIZE 20
71#define I810_TEXREG_MI0 0
72#define I810_TEXREG_MI1 1
Christopher Ferris05d08e92016-02-04 13:16:38 -080073#define I810_TEXREG_MI2 2
Ben Cheng655a7c02013-10-16 16:09:24 -070074#define I810_TEXREG_MI3 3
75#define I810_TEXREG_MF 4
76#define I810_TEXREG_MLC 5
Christopher Ferris05d08e92016-02-04 13:16:38 -080077#define I810_TEXREG_MLL 6
Ben Cheng655a7c02013-10-16 16:09:24 -070078#define I810_TEXREG_MCS 7
79#define I810_TEX_SETUP_SIZE 8
80#define I810_FRONT 0x1
Christopher Ferris05d08e92016-02-04 13:16:38 -080081#define I810_BACK 0x2
Ben Cheng655a7c02013-10-16 16:09:24 -070082#define I810_DEPTH 0x4
83typedef enum _drm_i810_init_func {
Tao Baod7db5942015-01-28 10:07:51 -080084 I810_INIT_DMA = 0x01,
Christopher Ferris05d08e92016-02-04 13:16:38 -080085 I810_CLEANUP_DMA = 0x02,
Tao Baod7db5942015-01-28 10:07:51 -080086 I810_INIT_DMA_1_4 = 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -070087} drm_i810_init_func_t;
88typedef struct _drm_i810_init {
Christopher Ferris05d08e92016-02-04 13:16:38 -080089 drm_i810_init_func_t func;
Tao Baod7db5942015-01-28 10:07:51 -080090 unsigned int mmio_offset;
91 unsigned int buffers_offset;
92 int sarea_priv_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080093 unsigned int ring_start;
Tao Baod7db5942015-01-28 10:07:51 -080094 unsigned int ring_end;
95 unsigned int ring_size;
96 unsigned int front_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -080097 unsigned int back_offset;
Tao Baod7db5942015-01-28 10:07:51 -080098 unsigned int depth_offset;
99 unsigned int overlay_offset;
100 unsigned int overlay_physical;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800101 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800102 unsigned int h;
103 unsigned int pitch;
104 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800105} drm_i810_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700106typedef struct _drm_i810_pre12_init {
Tao Baod7db5942015-01-28 10:07:51 -0800107 drm_i810_init_func_t func;
108 unsigned int mmio_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800109 unsigned int buffers_offset;
Tao Baod7db5942015-01-28 10:07:51 -0800110 int sarea_priv_offset;
111 unsigned int ring_start;
112 unsigned int ring_end;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800113 unsigned int ring_size;
Tao Baod7db5942015-01-28 10:07:51 -0800114 unsigned int front_offset;
115 unsigned int back_offset;
116 unsigned int depth_offset;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800117 unsigned int w;
Tao Baod7db5942015-01-28 10:07:51 -0800118 unsigned int h;
119 unsigned int pitch;
120 unsigned int pitch_bits;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800121} drm_i810_pre12_init_t;
Ben Cheng655a7c02013-10-16 16:09:24 -0700122typedef struct _drm_i810_tex_region {
Tao Baod7db5942015-01-28 10:07:51 -0800123 unsigned char next, prev;
124 unsigned char in_use;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800125 int age;
Ben Cheng655a7c02013-10-16 16:09:24 -0700126} drm_i810_tex_region_t;
127typedef struct _drm_i810_sarea {
Tao Baod7db5942015-01-28 10:07:51 -0800128 unsigned int ContextState[I810_CTX_SETUP_SIZE];
Christopher Ferris05d08e92016-02-04 13:16:38 -0800129 unsigned int BufferState[I810_DEST_SETUP_SIZE];
Tao Baod7db5942015-01-28 10:07:51 -0800130 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
131 unsigned int dirty;
132 unsigned int nbox;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800133 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
Tao Baod7db5942015-01-28 10:07:51 -0800134 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
135 int texAge;
136 int last_enqueue;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800137 int last_dispatch;
Tao Baod7db5942015-01-28 10:07:51 -0800138 int last_quiescent;
139 int ctxOwner;
140 int vertex_prim;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800141 int pf_enabled;
Tao Baod7db5942015-01-28 10:07:51 -0800142 int pf_active;
143 int pf_current_page;
Ben Cheng655a7c02013-10-16 16:09:24 -0700144} drm_i810_sarea_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800145#define DRM_I810_INIT 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700146#define DRM_I810_VERTEX 0x01
147#define DRM_I810_CLEAR 0x02
148#define DRM_I810_FLUSH 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800149#define DRM_I810_GETAGE 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700150#define DRM_I810_GETBUF 0x05
151#define DRM_I810_SWAP 0x06
152#define DRM_I810_COPY 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800153#define DRM_I810_DOCOPY 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -0700154#define DRM_I810_OV0INFO 0x09
155#define DRM_I810_FSTATUS 0x0a
156#define DRM_I810_OV0FLIP 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800157#define DRM_I810_MC 0x0c
Ben Cheng655a7c02013-10-16 16:09:24 -0700158#define DRM_I810_RSTATUS 0x0d
159#define DRM_I810_FLIP 0x0e
Tao Baod7db5942015-01-28 10:07:51 -0800160#define DRM_IOCTL_I810_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800161#define DRM_IOCTL_I810_VERTEX DRM_IOW(DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
Tao Baod7db5942015-01-28 10:07:51 -0800162#define DRM_IOCTL_I810_CLEAR DRM_IOW(DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
163#define DRM_IOCTL_I810_FLUSH DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLUSH)
164#define DRM_IOCTL_I810_GETAGE DRM_IO(DRM_COMMAND_BASE + DRM_I810_GETAGE)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800165#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
Tao Baod7db5942015-01-28 10:07:51 -0800166#define DRM_IOCTL_I810_SWAP DRM_IO(DRM_COMMAND_BASE + DRM_I810_SWAP)
167#define DRM_IOCTL_I810_COPY DRM_IOW(DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
168#define DRM_IOCTL_I810_DOCOPY DRM_IO(DRM_COMMAND_BASE + DRM_I810_DOCOPY)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800169#define DRM_IOCTL_I810_OV0INFO DRM_IOR(DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
Tao Baod7db5942015-01-28 10:07:51 -0800170#define DRM_IOCTL_I810_FSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_FSTATUS)
171#define DRM_IOCTL_I810_OV0FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
172#define DRM_IOCTL_I810_MC DRM_IOW(DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800173#define DRM_IOCTL_I810_RSTATUS DRM_IO(DRM_COMMAND_BASE + DRM_I810_RSTATUS)
Tao Baod7db5942015-01-28 10:07:51 -0800174#define DRM_IOCTL_I810_FLIP DRM_IO(DRM_COMMAND_BASE + DRM_I810_FLIP)
Ben Cheng655a7c02013-10-16 16:09:24 -0700175typedef struct _drm_i810_clear {
Tao Baod7db5942015-01-28 10:07:51 -0800176 int clear_color;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800177 int clear_depth;
Tao Baod7db5942015-01-28 10:07:51 -0800178 int flags;
Ben Cheng655a7c02013-10-16 16:09:24 -0700179} drm_i810_clear_t;
180typedef struct _drm_i810_vertex {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800181 int idx;
Tao Baod7db5942015-01-28 10:07:51 -0800182 int used;
183 int discard;
Ben Cheng655a7c02013-10-16 16:09:24 -0700184} drm_i810_vertex_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800185typedef struct _drm_i810_copy_t {
Tao Baod7db5942015-01-28 10:07:51 -0800186 int idx;
187 int used;
188 void * address;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800189} drm_i810_copy_t;
Tao Baod7db5942015-01-28 10:07:51 -0800190#define PR_TRIANGLES (0x0 << 18)
191#define PR_TRISTRIP_0 (0x1 << 18)
192#define PR_TRISTRIP_1 (0x2 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800193#define PR_TRIFAN (0x3 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800194#define PR_POLYGON (0x4 << 18)
195#define PR_LINES (0x5 << 18)
196#define PR_LINESTRIP (0x6 << 18)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800197#define PR_RECTS (0x7 << 18)
Tao Baod7db5942015-01-28 10:07:51 -0800198#define PR_MASK (0x7 << 18)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700199typedef struct drm_i810_dma {
200 void * __linux_virtual;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800201 int request_idx;
Tao Baod7db5942015-01-28 10:07:51 -0800202 int request_size;
203 int granted;
Ben Cheng655a7c02013-10-16 16:09:24 -0700204} drm_i810_dma_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800205typedef struct _drm_i810_overlay_t {
Tao Baod7db5942015-01-28 10:07:51 -0800206 unsigned int offset;
207 unsigned int physical;
Ben Cheng655a7c02013-10-16 16:09:24 -0700208} drm_i810_overlay_t;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800209typedef struct _drm_i810_mc {
Tao Baod7db5942015-01-28 10:07:51 -0800210 int idx;
211 int used;
212 int num_blocks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800213 int * length;
Tao Baod7db5942015-01-28 10:07:51 -0800214 unsigned int last_render;
Ben Cheng655a7c02013-10-16 16:09:24 -0700215} drm_i810_mc_t;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700216#ifdef __cplusplus
217#endif
Ben Cheng655a7c02013-10-16 16:09:24 -0700218#endif