blob: 5887678ff4f5121774bb176fc8805807583fd547 [file] [log] [blame]
Christopher Ferris9ce28842018-10-25 12:11:39 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _V3D_DRM_H_
20#define _V3D_DRM_H_
21#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris9ce28842018-10-25 12:11:39 -070024#endif
25#define DRM_V3D_SUBMIT_CL 0x00
26#define DRM_V3D_WAIT_BO 0x01
27#define DRM_V3D_CREATE_BO 0x02
28#define DRM_V3D_MMAP_BO 0x03
29#define DRM_V3D_GET_PARAM 0x04
30#define DRM_V3D_GET_BO_OFFSET 0x05
Christopher Ferrisd842e432019-03-07 10:21:59 -080031#define DRM_V3D_SUBMIT_TFU 0x06
Christopher Ferrisb8a95e22019-10-02 18:29:20 -070032#define DRM_V3D_SUBMIT_CSD 0x07
Christopher Ferris2abfa9e2021-11-01 16:26:06 -070033#define DRM_V3D_PERFMON_CREATE 0x08
34#define DRM_V3D_PERFMON_DESTROY 0x09
35#define DRM_V3D_PERFMON_GET_VALUES 0x0a
Christopher Ferris9ce28842018-10-25 12:11:39 -070036#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
37#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
38#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
39#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
40#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
41#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
Christopher Ferrisd842e432019-03-07 10:21:59 -080042#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
Christopher Ferrisb8a95e22019-10-02 18:29:20 -070043#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
Christopher Ferris2abfa9e2021-11-01 16:26:06 -070044#define DRM_IOCTL_V3D_PERFMON_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, struct drm_v3d_perfmon_create)
45#define DRM_IOCTL_V3D_PERFMON_DESTROY DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, struct drm_v3d_perfmon_destroy)
46#define DRM_IOCTL_V3D_PERFMON_GET_VALUES DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, struct drm_v3d_perfmon_get_values)
Christopher Ferrisd32ca142020-02-04 16:16:51 -080047#define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
Christopher Ferrisa4792612022-01-10 13:51:15 -080048#define DRM_V3D_SUBMIT_EXTENSION 0x02
49struct drm_v3d_extension {
50 __u64 next;
51 __u32 id;
52#define DRM_V3D_EXT_ID_MULTI_SYNC 0x01
53 __u32 flags;
54};
55struct drm_v3d_sem {
56 __u32 handle;
57 __u32 flags;
58 __u64 point;
59 __u64 mbz[2];
60};
61enum v3d_queue {
62 V3D_BIN,
63 V3D_RENDER,
64 V3D_TFU,
65 V3D_CSD,
66 V3D_CACHE_CLEAN,
67};
68struct drm_v3d_multi_sync {
69 struct drm_v3d_extension base;
70 __u64 in_syncs;
71 __u64 out_syncs;
72 __u32 in_sync_count;
73 __u32 out_sync_count;
74 __u32 wait_stage;
75 __u32 pad;
76};
Christopher Ferris9ce28842018-10-25 12:11:39 -070077struct drm_v3d_submit_cl {
78 __u32 bcl_start;
79 __u32 bcl_end;
80 __u32 rcl_start;
81 __u32 rcl_end;
82 __u32 in_sync_bcl;
83 __u32 in_sync_rcl;
84 __u32 out_sync;
85 __u32 qma;
86 __u32 qms;
87 __u32 qts;
88 __u64 bo_handles;
89 __u32 bo_handle_count;
Christopher Ferrisd32ca142020-02-04 16:16:51 -080090 __u32 flags;
Christopher Ferris2abfa9e2021-11-01 16:26:06 -070091 __u32 perfmon_id;
92 __u32 pad;
Christopher Ferrisa4792612022-01-10 13:51:15 -080093 __u64 extensions;
Christopher Ferris9ce28842018-10-25 12:11:39 -070094};
95struct drm_v3d_wait_bo {
96 __u32 handle;
97 __u32 pad;
98 __u64 timeout_ns;
99};
100struct drm_v3d_create_bo {
101 __u32 size;
102 __u32 flags;
103 __u32 handle;
104 __u32 offset;
105};
106struct drm_v3d_mmap_bo {
107 __u32 handle;
108 __u32 flags;
109 __u64 offset;
110};
111enum drm_v3d_param {
112 DRM_V3D_PARAM_V3D_UIFCFG,
113 DRM_V3D_PARAM_V3D_HUB_IDENT1,
114 DRM_V3D_PARAM_V3D_HUB_IDENT2,
115 DRM_V3D_PARAM_V3D_HUB_IDENT3,
116 DRM_V3D_PARAM_V3D_CORE0_IDENT0,
117 DRM_V3D_PARAM_V3D_CORE0_IDENT1,
118 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
Christopher Ferrisd842e432019-03-07 10:21:59 -0800119 DRM_V3D_PARAM_SUPPORTS_TFU,
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700120 DRM_V3D_PARAM_SUPPORTS_CSD,
Christopher Ferrisd32ca142020-02-04 16:16:51 -0800121 DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
Christopher Ferris2abfa9e2021-11-01 16:26:06 -0700122 DRM_V3D_PARAM_SUPPORTS_PERFMON,
Christopher Ferrisa4792612022-01-10 13:51:15 -0800123 DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700124};
125struct drm_v3d_get_param {
126 __u32 param;
127 __u32 pad;
128 __u64 value;
129};
130struct drm_v3d_get_bo_offset {
131 __u32 handle;
132 __u32 offset;
133};
Christopher Ferrisd842e432019-03-07 10:21:59 -0800134struct drm_v3d_submit_tfu {
135 __u32 icfg;
136 __u32 iia;
137 __u32 iis;
138 __u32 ica;
139 __u32 iua;
140 __u32 ioa;
141 __u32 ios;
142 __u32 coef[4];
143 __u32 bo_handles[4];
144 __u32 in_sync;
145 __u32 out_sync;
Christopher Ferrisa4792612022-01-10 13:51:15 -0800146 __u32 flags;
147 __u64 extensions;
Christopher Ferrisd842e432019-03-07 10:21:59 -0800148};
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700149struct drm_v3d_submit_csd {
150 __u32 cfg[7];
151 __u32 coef[4];
152 __u64 bo_handles;
153 __u32 bo_handle_count;
154 __u32 in_sync;
155 __u32 out_sync;
Christopher Ferris2abfa9e2021-11-01 16:26:06 -0700156 __u32 perfmon_id;
Christopher Ferrisa4792612022-01-10 13:51:15 -0800157 __u64 extensions;
158 __u32 flags;
159 __u32 pad;
Christopher Ferris2abfa9e2021-11-01 16:26:06 -0700160};
161enum {
162 V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
163 V3D_PERFCNT_FEP_VALID_PRIMS,
164 V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
165 V3D_PERFCNT_FEP_VALID_QUADS,
166 V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
167 V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
168 V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
169 V3D_PERFCNT_TLB_QUADS_ZERO_COV,
170 V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
171 V3D_PERFCNT_TLB_QUADS_WRITTEN,
172 V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
173 V3D_PERFCNT_PTB_PRIM_CLIP,
174 V3D_PERFCNT_PTB_PRIM_REV,
175 V3D_PERFCNT_QPU_IDLE_CYCLES,
176 V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
177 V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
178 V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
179 V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
180 V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
181 V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
182 V3D_PERFCNT_QPU_IC_HIT,
183 V3D_PERFCNT_QPU_IC_MISS,
184 V3D_PERFCNT_QPU_UC_HIT,
185 V3D_PERFCNT_QPU_UC_MISS,
186 V3D_PERFCNT_TMU_TCACHE_ACCESS,
187 V3D_PERFCNT_TMU_TCACHE_MISS,
188 V3D_PERFCNT_VPM_VDW_STALL,
189 V3D_PERFCNT_VPM_VCD_STALL,
190 V3D_PERFCNT_BIN_ACTIVE,
191 V3D_PERFCNT_RDR_ACTIVE,
192 V3D_PERFCNT_L2T_HITS,
193 V3D_PERFCNT_L2T_MISSES,
194 V3D_PERFCNT_CYCLE_COUNT,
195 V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
196 V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
197 V3D_PERFCNT_PTB_PRIMS_BINNED,
198 V3D_PERFCNT_AXI_WRITES_WATCH_0,
199 V3D_PERFCNT_AXI_READS_WATCH_0,
200 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
201 V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
202 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
203 V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
204 V3D_PERFCNT_AXI_WRITES_WATCH_1,
205 V3D_PERFCNT_AXI_READS_WATCH_1,
206 V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
207 V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
208 V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
209 V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
210 V3D_PERFCNT_TLB_PARTIAL_QUADS,
211 V3D_PERFCNT_TMU_CONFIG_ACCESSES,
212 V3D_PERFCNT_L2T_NO_ID_STALL,
213 V3D_PERFCNT_L2T_COM_QUE_STALL,
214 V3D_PERFCNT_L2T_TMU_WRITES,
215 V3D_PERFCNT_TMU_ACTIVE_CYCLES,
216 V3D_PERFCNT_TMU_STALLED_CYCLES,
217 V3D_PERFCNT_CLE_ACTIVE,
218 V3D_PERFCNT_L2T_TMU_READS,
219 V3D_PERFCNT_L2T_CLE_READS,
220 V3D_PERFCNT_L2T_VCD_READS,
221 V3D_PERFCNT_L2T_TMUCFG_READS,
222 V3D_PERFCNT_L2T_SLC0_READS,
223 V3D_PERFCNT_L2T_SLC1_READS,
224 V3D_PERFCNT_L2T_SLC2_READS,
225 V3D_PERFCNT_L2T_TMU_W_MISSES,
226 V3D_PERFCNT_L2T_TMU_R_MISSES,
227 V3D_PERFCNT_L2T_CLE_MISSES,
228 V3D_PERFCNT_L2T_VCD_MISSES,
229 V3D_PERFCNT_L2T_TMUCFG_MISSES,
230 V3D_PERFCNT_L2T_SLC0_MISSES,
231 V3D_PERFCNT_L2T_SLC1_MISSES,
232 V3D_PERFCNT_L2T_SLC2_MISSES,
233 V3D_PERFCNT_CORE_MEM_WRITES,
234 V3D_PERFCNT_L2T_MEM_WRITES,
235 V3D_PERFCNT_PTB_MEM_WRITES,
236 V3D_PERFCNT_TLB_MEM_WRITES,
237 V3D_PERFCNT_CORE_MEM_READS,
238 V3D_PERFCNT_L2T_MEM_READS,
239 V3D_PERFCNT_PTB_MEM_READS,
240 V3D_PERFCNT_PSE_MEM_READS,
241 V3D_PERFCNT_TLB_MEM_READS,
242 V3D_PERFCNT_GMP_MEM_READS,
243 V3D_PERFCNT_PTB_W_MEM_WORDS,
244 V3D_PERFCNT_TLB_W_MEM_WORDS,
245 V3D_PERFCNT_PSE_R_MEM_WORDS,
246 V3D_PERFCNT_TLB_R_MEM_WORDS,
247 V3D_PERFCNT_TMU_MRU_HITS,
248 V3D_PERFCNT_COMPUTE_ACTIVE,
249 V3D_PERFCNT_NUM,
250};
251#define DRM_V3D_MAX_PERF_COUNTERS 32
252struct drm_v3d_perfmon_create {
253 __u32 id;
254 __u32 ncounters;
255 __u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
256};
257struct drm_v3d_perfmon_destroy {
258 __u32 id;
259};
260struct drm_v3d_perfmon_get_values {
261 __u32 id;
262 __u32 pad;
263 __u64 values_ptr;
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700264};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700265#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800266}
Christopher Ferris9ce28842018-10-25 12:11:39 -0700267#endif
268#endif