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gerrit.omnirom.org / android_bionic / b8a95e21865efd16bf821333d34e005b8f0a8d3a / . / libc / kernel / uapi / drm / v3d_drm.h
blob: 0b6b94f2054a054dbfdb6ea1b8c8e1c0078a20e3 [file] [log] [blame]
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _V3D_DRM_H_
20#define _V3D_DRM_H_
21#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800[diff] [blame]23extern "C" {
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]24#endif
25#define DRM_V3D_SUBMIT_CL 0x00
26#define DRM_V3D_WAIT_BO 0x01
27#define DRM_V3D_CREATE_BO 0x02
28#define DRM_V3D_MMAP_BO 0x03
29#define DRM_V3D_GET_PARAM 0x04
30#define DRM_V3D_GET_BO_OFFSET 0x05
Christopher Ferrisd842e432019-03-07 10:21:59 -0800[diff] [blame]31#define DRM_V3D_SUBMIT_TFU 0x06
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame^]32#define DRM_V3D_SUBMIT_CSD 0x07
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]33#define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
34#define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
35#define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
36#define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
37#define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
38#define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
Christopher Ferrisd842e432019-03-07 10:21:59 -0800[diff] [blame]39#define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame^]40#define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]41struct drm_v3d_submit_cl {
42 __u32 bcl_start;
43 __u32 bcl_end;
44 __u32 rcl_start;
45 __u32 rcl_end;
46 __u32 in_sync_bcl;
47 __u32 in_sync_rcl;
48 __u32 out_sync;
49 __u32 qma;
50 __u32 qms;
51 __u32 qts;
52 __u64 bo_handles;
53 __u32 bo_handle_count;
54 __u32 pad;
55};
56struct drm_v3d_wait_bo {
57 __u32 handle;
58 __u32 pad;
59 __u64 timeout_ns;
60};
61struct drm_v3d_create_bo {
62 __u32 size;
63 __u32 flags;
64 __u32 handle;
65 __u32 offset;
66};
67struct drm_v3d_mmap_bo {
68 __u32 handle;
69 __u32 flags;
70 __u64 offset;
71};
72enum drm_v3d_param {
73 DRM_V3D_PARAM_V3D_UIFCFG,
74 DRM_V3D_PARAM_V3D_HUB_IDENT1,
75 DRM_V3D_PARAM_V3D_HUB_IDENT2,
76 DRM_V3D_PARAM_V3D_HUB_IDENT3,
77 DRM_V3D_PARAM_V3D_CORE0_IDENT0,
78 DRM_V3D_PARAM_V3D_CORE0_IDENT1,
79 DRM_V3D_PARAM_V3D_CORE0_IDENT2,
Christopher Ferrisd842e432019-03-07 10:21:59 -0800[diff] [blame]80 DRM_V3D_PARAM_SUPPORTS_TFU,
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame^]81 DRM_V3D_PARAM_SUPPORTS_CSD,
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]82};
83struct drm_v3d_get_param {
84 __u32 param;
85 __u32 pad;
86 __u64 value;
87};
88struct drm_v3d_get_bo_offset {
89 __u32 handle;
90 __u32 offset;
91};
Christopher Ferrisd842e432019-03-07 10:21:59 -0800[diff] [blame]92struct drm_v3d_submit_tfu {
93 __u32 icfg;
94 __u32 iia;
95 __u32 iis;
96 __u32 ica;
97 __u32 iua;
98 __u32 ioa;
99 __u32 ios;
100 __u32 coef[4];
101 __u32 bo_handles[4];
102 __u32 in_sync;
103 __u32 out_sync;
104};
Christopher Ferrisb8a95e22019-10-02 18:29:20 -0700[diff] [blame^]105struct drm_v3d_submit_csd {
106 __u32 cfg[7];
107 __u32 coef[4];
108 __u64 bo_handles;
109 __u32 bo_handle_count;
110 __u32 in_sync;
111 __u32 out_sync;
112};
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]113#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800[diff] [blame]114}
Christopher Ferris9ce28842018-10-25 12:11:39 -0700[diff] [blame]115#endif
116#endif