blob: 7f532771b620d4b4aa40c13c8c4b37d2e3b46cbb [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _LINUX_SERIAL_REG_H
8#define _LINUX_SERIAL_REG_H
9#define UART_RX 0
10#define UART_TX 0
Ben Cheng655a7c02013-10-16 16:09:24 -070011#define UART_IER 1
12#define UART_IER_MSI 0x08
13#define UART_IER_RLSI 0x04
14#define UART_IER_THRI 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -070015#define UART_IER_RDI 0x01
16#define UART_IERX_SLEEP 0x10
17#define UART_IIR 2
18#define UART_IIR_NO_INT 0x01
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070019#define UART_IIR_ID 0x0e
Ben Cheng655a7c02013-10-16 16:09:24 -070020#define UART_IIR_MSI 0x00
21#define UART_IIR_THRI 0x02
22#define UART_IIR_RDI 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -070023#define UART_IIR_RLSI 0x06
24#define UART_IIR_BUSY 0x07
25#define UART_IIR_RX_TIMEOUT 0x0c
26#define UART_IIR_XOFF 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define UART_IIR_CTS_RTS_DSR 0x20
Christopher Ferrisb7cef6d2023-05-09 19:04:15 +000028#define UART_IIR_64BYTE_FIFO 0x20
29#define UART_IIR_FIFO_ENABLED 0xc0
30#define UART_IIR_FIFO_ENABLED_8250 0x00
31#define UART_IIR_FIFO_ENABLED_16550 0x80
32#define UART_IIR_FIFO_ENABLED_16550A 0xc0
Christopher Ferris0f795212024-01-17 14:17:28 -080033#define UART_IIR_FIFO_ENABLED_16750 0xe0
Ben Cheng655a7c02013-10-16 16:09:24 -070034#define UART_FCR 2
35#define UART_FCR_ENABLE_FIFO 0x01
36#define UART_FCR_CLEAR_RCVR 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -070037#define UART_FCR_CLEAR_XMIT 0x04
38#define UART_FCR_DMA_SELECT 0x08
39#define UART_FCR_R_TRIG_00 0x00
40#define UART_FCR_R_TRIG_01 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -070041#define UART_FCR_R_TRIG_10 0x80
42#define UART_FCR_R_TRIG_11 0xc0
43#define UART_FCR_T_TRIG_00 0x00
44#define UART_FCR_T_TRIG_01 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070045#define UART_FCR_T_TRIG_10 0x20
46#define UART_FCR_T_TRIG_11 0x30
47#define UART_FCR_TRIGGER_MASK 0xC0
48#define UART_FCR_TRIGGER_1 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070049#define UART_FCR_TRIGGER_4 0x40
50#define UART_FCR_TRIGGER_8 0x80
51#define UART_FCR_TRIGGER_14 0xC0
52#define UART_FCR6_R_TRIGGER_8 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070053#define UART_FCR6_R_TRIGGER_16 0x40
54#define UART_FCR6_R_TRIGGER_24 0x80
55#define UART_FCR6_R_TRIGGER_28 0xC0
56#define UART_FCR6_T_TRIGGER_16 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070057#define UART_FCR6_T_TRIGGER_8 0x10
58#define UART_FCR6_T_TRIGGER_24 0x20
59#define UART_FCR6_T_TRIGGER_30 0x30
60#define UART_FCR7_64BYTE 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -080061#define UART_FCR_R_TRIG_SHIFT 6
Tao Baod7db5942015-01-28 10:07:51 -080062#define UART_FCR_R_TRIG_BITS(x) (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
Christopher Ferris82d75042015-01-26 10:57:07 -080063#define UART_FCR_R_TRIG_MAX_STATE 4
Ben Cheng655a7c02013-10-16 16:09:24 -070064#define UART_LCR 3
65#define UART_LCR_DLAB 0x80
66#define UART_LCR_SBC 0x40
67#define UART_LCR_SPAR 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -070068#define UART_LCR_EPAR 0x10
69#define UART_LCR_PARITY 0x08
70#define UART_LCR_STOP 0x04
71#define UART_LCR_WLEN5 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070072#define UART_LCR_WLEN6 0x01
73#define UART_LCR_WLEN7 0x02
74#define UART_LCR_WLEN8 0x03
75#define UART_LCR_CONF_MODE_A UART_LCR_DLAB
Ben Cheng655a7c02013-10-16 16:09:24 -070076#define UART_LCR_CONF_MODE_B 0xBF
77#define UART_MCR 4
78#define UART_MCR_CLKSEL 0x80
79#define UART_MCR_TCRTLR 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -070080#define UART_MCR_XONANY 0x20
81#define UART_MCR_AFE 0x20
82#define UART_MCR_LOOP 0x10
83#define UART_MCR_OUT2 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -070084#define UART_MCR_OUT1 0x04
85#define UART_MCR_RTS 0x02
86#define UART_MCR_DTR 0x01
87#define UART_LSR 5
Ben Cheng655a7c02013-10-16 16:09:24 -070088#define UART_LSR_FIFOE 0x80
89#define UART_LSR_TEMT 0x40
90#define UART_LSR_THRE 0x20
91#define UART_LSR_BI 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070092#define UART_LSR_FE 0x08
93#define UART_LSR_PE 0x04
94#define UART_LSR_OE 0x02
95#define UART_LSR_DR 0x01
Christopher Ferris7447a1c2022-10-04 18:24:44 -070096#define UART_LSR_BRK_ERROR_BITS (UART_LSR_BI | UART_LSR_FE | UART_LSR_PE | UART_LSR_OE)
Ben Cheng655a7c02013-10-16 16:09:24 -070097#define UART_MSR 6
98#define UART_MSR_DCD 0x80
99#define UART_MSR_RI 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700100#define UART_MSR_DSR 0x20
101#define UART_MSR_CTS 0x10
102#define UART_MSR_DDCD 0x08
103#define UART_MSR_TERI 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700104#define UART_MSR_DDSR 0x02
105#define UART_MSR_DCTS 0x01
Christopher Ferris7447a1c2022-10-04 18:24:44 -0700106#define UART_MSR_ANY_DELTA (UART_MSR_DDCD | UART_MSR_TERI | UART_MSR_DDSR | UART_MSR_DCTS)
Ben Cheng655a7c02013-10-16 16:09:24 -0700107#define UART_SCR 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700108#define UART_DLL 0
109#define UART_DLM 1
Christopher Ferris934ec942018-01-31 15:29:16 -0800110#define UART_DIV_MAX 0xFFFF
Ben Cheng655a7c02013-10-16 16:09:24 -0700111#define UART_EFR 2
112#define UART_XR_EFR 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700113#define UART_EFR_CTS 0x80
114#define UART_EFR_RTS 0x40
115#define UART_EFR_SCD 0x20
116#define UART_EFR_ECB 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700117#define UART_XON1 4
118#define UART_XON2 5
119#define UART_XOFF1 6
120#define UART_XOFF2 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700121#define UART_TI752_TCR 6
122#define UART_TI752_TLR 7
123#define UART_TRG 0
124#define UART_TRG_1 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700125#define UART_TRG_4 0x04
126#define UART_TRG_8 0x08
127#define UART_TRG_16 0x10
128#define UART_TRG_32 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700129#define UART_TRG_64 0x40
130#define UART_TRG_96 0x60
131#define UART_TRG_120 0x78
132#define UART_TRG_128 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700133#define UART_FCTR 1
134#define UART_FCTR_RTS_NODELAY 0x00
135#define UART_FCTR_RTS_4DELAY 0x01
136#define UART_FCTR_RTS_6DELAY 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700137#define UART_FCTR_RTS_8DELAY 0x03
138#define UART_FCTR_IRDA 0x04
139#define UART_FCTR_TX_INT 0x08
140#define UART_FCTR_TRGA 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700141#define UART_FCTR_TRGB 0x10
142#define UART_FCTR_TRGC 0x20
143#define UART_FCTR_TRGD 0x30
144#define UART_FCTR_SCR_SWAP 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700145#define UART_FCTR_RX 0x00
146#define UART_FCTR_TX 0x80
147#define UART_EMSR 7
148#define UART_EMSR_FIFO_COUNT 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700149#define UART_EMSR_ALT_COUNT 0x02
150#define UART_IER_DMAE 0x80
151#define UART_IER_UUE 0x40
152#define UART_IER_NRZE 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700153#define UART_IER_RTOIE 0x10
154#define UART_IIR_TOD 0x08
155#define UART_FCR_PXAR1 0x00
156#define UART_FCR_PXAR8 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700157#define UART_FCR_PXAR16 0x80
158#define UART_FCR_PXAR32 0xc0
Ben Cheng655a7c02013-10-16 16:09:24 -0700159#define UART_ASR 0x01
160#define UART_RFL 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700161#define UART_TFL 0x04
162#define UART_ICR 0x05
163#define UART_ACR 0x00
164#define UART_CPR 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700165#define UART_TCR 0x02
166#define UART_CKS 0x03
167#define UART_TTL 0x04
168#define UART_RTL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700169#define UART_FCL 0x06
170#define UART_FCH 0x07
171#define UART_ID1 0x08
172#define UART_ID2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700173#define UART_ID3 0x0A
174#define UART_REV 0x0B
175#define UART_CSR 0x0C
176#define UART_NMR 0x0D
Ben Cheng655a7c02013-10-16 16:09:24 -0700177#define UART_CTR 0xFF
178#define UART_ACR_RXDIS 0x01
179#define UART_ACR_TXDIS 0x02
180#define UART_ACR_DSRFC 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700181#define UART_ACR_TLENB 0x20
182#define UART_ACR_ICRRD 0x40
183#define UART_ACR_ASREN 0x80
Tao Baod7db5942015-01-28 10:07:51 -0800184#define UART_RSA_BASE (- 8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700185#define UART_RSA_MSR ((UART_RSA_BASE) + 0)
186#define UART_RSA_MSR_SWAP (1 << 0)
187#define UART_RSA_MSR_FIFO (1 << 2)
188#define UART_RSA_MSR_FLOW (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700189#define UART_RSA_MSR_ITYP (1 << 4)
190#define UART_RSA_IER ((UART_RSA_BASE) + 1)
191#define UART_RSA_IER_Rx_FIFO_H (1 << 0)
192#define UART_RSA_IER_Tx_FIFO_H (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700193#define UART_RSA_IER_Tx_FIFO_E (1 << 2)
194#define UART_RSA_IER_Rx_TOUT (1 << 3)
195#define UART_RSA_IER_TIMER (1 << 4)
196#define UART_RSA_SRR ((UART_RSA_BASE) + 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700197#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0)
198#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1)
199#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2)
200#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700201#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4)
202#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5)
203#define UART_RSA_SRR_Rx_TOUT (1 << 6)
204#define UART_RSA_SRR_TIMER (1 << 7)
Ben Cheng655a7c02013-10-16 16:09:24 -0700205#define UART_RSA_FRR ((UART_RSA_BASE) + 2)
206#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3)
207#define UART_RSA_TCR ((UART_RSA_BASE) + 4)
208#define UART_RSA_TCR_SWITCH (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700209#define SERIAL_RSA_BAUD_BASE (921600)
210#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
Christopher Ferris525ce912017-07-26 13:12:53 -0700211#define UART_DA830_PWREMU_MGMT 12
212#define UART_DA830_PWREMU_MGMT_FREE (1 << 0)
213#define UART_DA830_PWREMU_MGMT_URRST (1 << 13)
214#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800215#define OMAP1_UART1_BASE 0xfffb0000
216#define OMAP1_UART2_BASE 0xfffb0800
217#define OMAP1_UART3_BASE 0xfffb9800
Ben Cheng655a7c02013-10-16 16:09:24 -0700218#define UART_OMAP_MDR1 0x08
219#define UART_OMAP_MDR2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700220#define UART_OMAP_SCR 0x10
221#define UART_OMAP_SSR 0x11
222#define UART_OMAP_EBLR 0x12
223#define UART_OMAP_OSC_12M_SEL 0x13
Ben Cheng655a7c02013-10-16 16:09:24 -0700224#define UART_OMAP_MVER 0x14
225#define UART_OMAP_SYSC 0x15
226#define UART_OMAP_SYSS 0x16
227#define UART_OMAP_WER 0x17
Christopher Ferris05d08e92016-02-04 13:16:38 -0800228#define UART_OMAP_TX_LVL 0x1a
Ben Cheng655a7c02013-10-16 16:09:24 -0700229#define UART_OMAP_MDR1_16X_MODE 0x00
230#define UART_OMAP_MDR1_SIR_MODE 0x01
231#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02
232#define UART_OMAP_MDR1_13X_MODE 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700233#define UART_OMAP_MDR1_MIR_MODE 0x04
234#define UART_OMAP_MDR1_FIR_MODE 0x05
235#define UART_OMAP_MDR1_CIR_MODE 0x06
236#define UART_OMAP_MDR1_DISABLE 0x07
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800237#define UART_ALTR_AFR 0x40
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800238#define UART_ALTR_EN_TXFIFO_LW 0x01
239#define UART_ALTR_TX_LOW 0x41
240#endif