blob: 95c99566adecbbf1073c3fb6adb1d9771ad8f46a [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _LINUX_SERIAL_REG_H
20#define _LINUX_SERIAL_REG_H
21#define UART_RX 0
22#define UART_TX 0
Ben Cheng655a7c02013-10-16 16:09:24 -070023#define UART_IER 1
24#define UART_IER_MSI 0x08
25#define UART_IER_RLSI 0x04
26#define UART_IER_THRI 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -070027#define UART_IER_RDI 0x01
28#define UART_IERX_SLEEP 0x10
29#define UART_IIR 2
30#define UART_IIR_NO_INT 0x01
Christopher Ferrisba8d4f42014-09-03 19:56:49 -070031#define UART_IIR_ID 0x0e
Ben Cheng655a7c02013-10-16 16:09:24 -070032#define UART_IIR_MSI 0x00
33#define UART_IIR_THRI 0x02
34#define UART_IIR_RDI 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -070035#define UART_IIR_RLSI 0x06
36#define UART_IIR_BUSY 0x07
37#define UART_IIR_RX_TIMEOUT 0x0c
38#define UART_IIR_XOFF 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070039#define UART_IIR_CTS_RTS_DSR 0x20
40#define UART_FCR 2
41#define UART_FCR_ENABLE_FIFO 0x01
42#define UART_FCR_CLEAR_RCVR 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -070043#define UART_FCR_CLEAR_XMIT 0x04
44#define UART_FCR_DMA_SELECT 0x08
45#define UART_FCR_R_TRIG_00 0x00
46#define UART_FCR_R_TRIG_01 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -070047#define UART_FCR_R_TRIG_10 0x80
48#define UART_FCR_R_TRIG_11 0xc0
49#define UART_FCR_T_TRIG_00 0x00
50#define UART_FCR_T_TRIG_01 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define UART_FCR_T_TRIG_10 0x20
52#define UART_FCR_T_TRIG_11 0x30
53#define UART_FCR_TRIGGER_MASK 0xC0
54#define UART_FCR_TRIGGER_1 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070055#define UART_FCR_TRIGGER_4 0x40
56#define UART_FCR_TRIGGER_8 0x80
57#define UART_FCR_TRIGGER_14 0xC0
58#define UART_FCR6_R_TRIGGER_8 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070059#define UART_FCR6_R_TRIGGER_16 0x40
60#define UART_FCR6_R_TRIGGER_24 0x80
61#define UART_FCR6_R_TRIGGER_28 0xC0
62#define UART_FCR6_T_TRIGGER_16 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070063#define UART_FCR6_T_TRIGGER_8 0x10
64#define UART_FCR6_T_TRIGGER_24 0x20
65#define UART_FCR6_T_TRIGGER_30 0x30
66#define UART_FCR7_64BYTE 0x20
Christopher Ferris82d75042015-01-26 10:57:07 -080067#define UART_FCR_R_TRIG_SHIFT 6
Tao Baod7db5942015-01-28 10:07:51 -080068#define UART_FCR_R_TRIG_BITS(x) (((x) & UART_FCR_TRIGGER_MASK) >> UART_FCR_R_TRIG_SHIFT)
Christopher Ferris82d75042015-01-26 10:57:07 -080069#define UART_FCR_R_TRIG_MAX_STATE 4
Ben Cheng655a7c02013-10-16 16:09:24 -070070#define UART_LCR 3
71#define UART_LCR_DLAB 0x80
72#define UART_LCR_SBC 0x40
73#define UART_LCR_SPAR 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -070074#define UART_LCR_EPAR 0x10
75#define UART_LCR_PARITY 0x08
76#define UART_LCR_STOP 0x04
77#define UART_LCR_WLEN5 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -070078#define UART_LCR_WLEN6 0x01
79#define UART_LCR_WLEN7 0x02
80#define UART_LCR_WLEN8 0x03
81#define UART_LCR_CONF_MODE_A UART_LCR_DLAB
Ben Cheng655a7c02013-10-16 16:09:24 -070082#define UART_LCR_CONF_MODE_B 0xBF
83#define UART_MCR 4
84#define UART_MCR_CLKSEL 0x80
85#define UART_MCR_TCRTLR 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -070086#define UART_MCR_XONANY 0x20
87#define UART_MCR_AFE 0x20
88#define UART_MCR_LOOP 0x10
89#define UART_MCR_OUT2 0x08
Ben Cheng655a7c02013-10-16 16:09:24 -070090#define UART_MCR_OUT1 0x04
91#define UART_MCR_RTS 0x02
92#define UART_MCR_DTR 0x01
93#define UART_LSR 5
Ben Cheng655a7c02013-10-16 16:09:24 -070094#define UART_LSR_FIFOE 0x80
95#define UART_LSR_TEMT 0x40
96#define UART_LSR_THRE 0x20
97#define UART_LSR_BI 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -070098#define UART_LSR_FE 0x08
99#define UART_LSR_PE 0x04
100#define UART_LSR_OE 0x02
101#define UART_LSR_DR 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700102#define UART_LSR_BRK_ERROR_BITS 0x1E
103#define UART_MSR 6
104#define UART_MSR_DCD 0x80
105#define UART_MSR_RI 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700106#define UART_MSR_DSR 0x20
107#define UART_MSR_CTS 0x10
108#define UART_MSR_DDCD 0x08
109#define UART_MSR_TERI 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700110#define UART_MSR_DDSR 0x02
111#define UART_MSR_DCTS 0x01
112#define UART_MSR_ANY_DELTA 0x0F
113#define UART_SCR 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700114#define UART_DLL 0
115#define UART_DLM 1
116#define UART_EFR 2
117#define UART_XR_EFR 9
Ben Cheng655a7c02013-10-16 16:09:24 -0700118#define UART_EFR_CTS 0x80
119#define UART_EFR_RTS 0x40
120#define UART_EFR_SCD 0x20
121#define UART_EFR_ECB 0x10
Ben Cheng655a7c02013-10-16 16:09:24 -0700122#define UART_XON1 4
123#define UART_XON2 5
124#define UART_XOFF1 6
125#define UART_XOFF2 7
Ben Cheng655a7c02013-10-16 16:09:24 -0700126#define UART_TI752_TCR 6
127#define UART_TI752_TLR 7
128#define UART_TRG 0
129#define UART_TRG_1 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700130#define UART_TRG_4 0x04
131#define UART_TRG_8 0x08
132#define UART_TRG_16 0x10
133#define UART_TRG_32 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700134#define UART_TRG_64 0x40
135#define UART_TRG_96 0x60
136#define UART_TRG_120 0x78
137#define UART_TRG_128 0x80
Ben Cheng655a7c02013-10-16 16:09:24 -0700138#define UART_FCTR 1
139#define UART_FCTR_RTS_NODELAY 0x00
140#define UART_FCTR_RTS_4DELAY 0x01
141#define UART_FCTR_RTS_6DELAY 0x02
Ben Cheng655a7c02013-10-16 16:09:24 -0700142#define UART_FCTR_RTS_8DELAY 0x03
143#define UART_FCTR_IRDA 0x04
144#define UART_FCTR_TX_INT 0x08
145#define UART_FCTR_TRGA 0x00
Ben Cheng655a7c02013-10-16 16:09:24 -0700146#define UART_FCTR_TRGB 0x10
147#define UART_FCTR_TRGC 0x20
148#define UART_FCTR_TRGD 0x30
149#define UART_FCTR_SCR_SWAP 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700150#define UART_FCTR_RX 0x00
151#define UART_FCTR_TX 0x80
152#define UART_EMSR 7
153#define UART_EMSR_FIFO_COUNT 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700154#define UART_EMSR_ALT_COUNT 0x02
155#define UART_IER_DMAE 0x80
156#define UART_IER_UUE 0x40
157#define UART_IER_NRZE 0x20
Ben Cheng655a7c02013-10-16 16:09:24 -0700158#define UART_IER_RTOIE 0x10
159#define UART_IIR_TOD 0x08
160#define UART_FCR_PXAR1 0x00
161#define UART_FCR_PXAR8 0x40
Ben Cheng655a7c02013-10-16 16:09:24 -0700162#define UART_FCR_PXAR16 0x80
163#define UART_FCR_PXAR32 0xc0
Ben Cheng655a7c02013-10-16 16:09:24 -0700164#define UART_ASR 0x01
165#define UART_RFL 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700166#define UART_TFL 0x04
167#define UART_ICR 0x05
168#define UART_ACR 0x00
169#define UART_CPR 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700170#define UART_TCR 0x02
171#define UART_CKS 0x03
172#define UART_TTL 0x04
173#define UART_RTL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700174#define UART_FCL 0x06
175#define UART_FCH 0x07
176#define UART_ID1 0x08
177#define UART_ID2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700178#define UART_ID3 0x0A
179#define UART_REV 0x0B
180#define UART_CSR 0x0C
181#define UART_NMR 0x0D
Ben Cheng655a7c02013-10-16 16:09:24 -0700182#define UART_CTR 0xFF
183#define UART_ACR_RXDIS 0x01
184#define UART_ACR_TXDIS 0x02
185#define UART_ACR_DSRFC 0x04
Ben Cheng655a7c02013-10-16 16:09:24 -0700186#define UART_ACR_TLENB 0x20
187#define UART_ACR_ICRRD 0x40
188#define UART_ACR_ASREN 0x80
Tao Baod7db5942015-01-28 10:07:51 -0800189#define UART_RSA_BASE (- 8)
Ben Cheng655a7c02013-10-16 16:09:24 -0700190#define UART_RSA_MSR ((UART_RSA_BASE) + 0)
191#define UART_RSA_MSR_SWAP (1 << 0)
192#define UART_RSA_MSR_FIFO (1 << 2)
193#define UART_RSA_MSR_FLOW (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700194#define UART_RSA_MSR_ITYP (1 << 4)
195#define UART_RSA_IER ((UART_RSA_BASE) + 1)
196#define UART_RSA_IER_Rx_FIFO_H (1 << 0)
197#define UART_RSA_IER_Tx_FIFO_H (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700198#define UART_RSA_IER_Tx_FIFO_E (1 << 2)
199#define UART_RSA_IER_Rx_TOUT (1 << 3)
200#define UART_RSA_IER_TIMER (1 << 4)
201#define UART_RSA_SRR ((UART_RSA_BASE) + 2)
Ben Cheng655a7c02013-10-16 16:09:24 -0700202#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0)
203#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1)
204#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2)
205#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3)
Ben Cheng655a7c02013-10-16 16:09:24 -0700206#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4)
207#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5)
208#define UART_RSA_SRR_Rx_TOUT (1 << 6)
209#define UART_RSA_SRR_TIMER (1 << 7)
Ben Cheng655a7c02013-10-16 16:09:24 -0700210#define UART_RSA_FRR ((UART_RSA_BASE) + 2)
211#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3)
212#define UART_RSA_TCR ((UART_RSA_BASE) + 4)
213#define UART_RSA_TCR_SWITCH (1 << 0)
Ben Cheng655a7c02013-10-16 16:09:24 -0700214#define SERIAL_RSA_BAUD_BASE (921600)
215#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
Christopher Ferris525ce912017-07-26 13:12:53 -0700216#define UART_DA830_PWREMU_MGMT 12
217#define UART_DA830_PWREMU_MGMT_FREE (1 << 0)
218#define UART_DA830_PWREMU_MGMT_URRST (1 << 13)
219#define UART_DA830_PWREMU_MGMT_UTRST (1 << 14)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800220#define OMAP1_UART1_BASE 0xfffb0000
221#define OMAP1_UART2_BASE 0xfffb0800
222#define OMAP1_UART3_BASE 0xfffb9800
Ben Cheng655a7c02013-10-16 16:09:24 -0700223#define UART_OMAP_MDR1 0x08
224#define UART_OMAP_MDR2 0x09
Ben Cheng655a7c02013-10-16 16:09:24 -0700225#define UART_OMAP_SCR 0x10
226#define UART_OMAP_SSR 0x11
227#define UART_OMAP_EBLR 0x12
228#define UART_OMAP_OSC_12M_SEL 0x13
Ben Cheng655a7c02013-10-16 16:09:24 -0700229#define UART_OMAP_MVER 0x14
230#define UART_OMAP_SYSC 0x15
231#define UART_OMAP_SYSS 0x16
232#define UART_OMAP_WER 0x17
Christopher Ferris05d08e92016-02-04 13:16:38 -0800233#define UART_OMAP_TX_LVL 0x1a
Ben Cheng655a7c02013-10-16 16:09:24 -0700234#define UART_OMAP_MDR1_16X_MODE 0x00
235#define UART_OMAP_MDR1_SIR_MODE 0x01
236#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02
237#define UART_OMAP_MDR1_13X_MODE 0x03
Ben Cheng655a7c02013-10-16 16:09:24 -0700238#define UART_OMAP_MDR1_MIR_MODE 0x04
239#define UART_OMAP_MDR1_FIR_MODE 0x05
240#define UART_OMAP_MDR1_CIR_MODE 0x06
241#define UART_OMAP_MDR1_DISABLE 0x07
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800242#define UART_ALTR_AFR 0x40
Christopher Ferris6a9755d2017-01-13 14:09:31 -0800243#define UART_ALTR_EN_TXFIFO_LW 0x01
244#define UART_ALTR_TX_LOW 0x41
245#endif