blob: 2df0768c9e2527222e26410e10cd847bb8715e89 [file] [log] [blame]
Jiyong Park196115b2023-02-25 02:01:15 +09001/*
2 * Copyright (C) 2022 Google LLC
3 */
4
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6
7#define PLACEHOLDER 0xffffffff
8#define PLACEHOLDER2 PLACEHOLDER PLACEHOLDER
9#define PLACEHOLDER4 PLACEHOLDER2 PLACEHOLDER2
10
Pierre-Clément Tosib88ad952024-05-22 11:27:45 +010011#define PLACEHOLDER_CPU_MAP_CORE(n) core##n { cpu = <PLACEHOLDER>; };
12#define PLACEHOLDER_CPU_MAP_CLUSTER \
13 PLACEHOLDER_CPU_MAP_CORE(0) \
14 PLACEHOLDER_CPU_MAP_CORE(1) \
15 PLACEHOLDER_CPU_MAP_CORE(2) \
16 PLACEHOLDER_CPU_MAP_CORE(3) \
17 PLACEHOLDER_CPU_MAP_CORE(4) \
18 PLACEHOLDER_CPU_MAP_CORE(5) \
19 PLACEHOLDER_CPU_MAP_CORE(6) \
20 PLACEHOLDER_CPU_MAP_CORE(7) \
21 PLACEHOLDER_CPU_MAP_CORE(8) \
22 PLACEHOLDER_CPU_MAP_CORE(9)
23
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +010024#define PLACEHOLDER_OPP_TABLE_ENTRY(n) opp##n { opp-hz = <PLACEHOLDER2>; };
25#define PLACEHOLDER_OPP_TABLE \
26 PLACEHOLDER_OPP_TABLE_ENTRY(1) \
27 PLACEHOLDER_OPP_TABLE_ENTRY(2) \
28 PLACEHOLDER_OPP_TABLE_ENTRY(3) \
29 PLACEHOLDER_OPP_TABLE_ENTRY(4) \
30 PLACEHOLDER_OPP_TABLE_ENTRY(5) \
31 PLACEHOLDER_OPP_TABLE_ENTRY(6) \
32 PLACEHOLDER_OPP_TABLE_ENTRY(7) \
33 PLACEHOLDER_OPP_TABLE_ENTRY(8) \
34 PLACEHOLDER_OPP_TABLE_ENTRY(9) \
35 PLACEHOLDER_OPP_TABLE_ENTRY(10) \
36 PLACEHOLDER_OPP_TABLE_ENTRY(11) \
37 PLACEHOLDER_OPP_TABLE_ENTRY(12) \
38 PLACEHOLDER_OPP_TABLE_ENTRY(13) \
39 PLACEHOLDER_OPP_TABLE_ENTRY(14) \
40 PLACEHOLDER_OPP_TABLE_ENTRY(15) \
41 PLACEHOLDER_OPP_TABLE_ENTRY(16) \
42 PLACEHOLDER_OPP_TABLE_ENTRY(17) \
43 PLACEHOLDER_OPP_TABLE_ENTRY(18) \
44 PLACEHOLDER_OPP_TABLE_ENTRY(19) \
45 PLACEHOLDER_OPP_TABLE_ENTRY(20)
46
Jiyong Parka503f422023-03-21 19:27:04 +090047#define IRQ_BASE 4
48
Jiyong Park196115b2023-02-25 02:01:15 +090049/dts-v1/;
50
51/ {
52 interrupt-parent = <&intc>;
53 compatible = "linux,dummy-virt";
54 #address-cells = <2>;
55 #size-cells = <2>;
56
57 chosen {
58 stdout-path = "/uart@3f8";
59 linux,pci-probe-only = <1>;
60 kaslr-seed = <PLACEHOLDER2>;
61 avf,strict-boot;
62 avf,new-instance;
63 };
64
65 memory {
66 device_type = "memory";
Jiyong Parkef85e832023-02-25 02:03:39 +090067 reg = <0x00 0x80000000 PLACEHOLDER2>;
Jiyong Park196115b2023-02-25 02:01:15 +090068 };
69
70 reserved-memory {
71 #address-cells = <2>;
72 #size-cells = <2>;
73 ranges;
74 swiotlb: restricted_dma_reserved {
75 compatible = "restricted-dma-pool";
Pierre-Clément Tosic27c4272023-05-19 15:46:26 +000076 reg = <PLACEHOLDER4>;
Jiyong Park196115b2023-02-25 02:01:15 +090077 size = <PLACEHOLDER2>;
78 alignment = <PLACEHOLDER2>;
79 };
80
81 dice {
82 compatible = "google,open-dice";
83 no-map;
84 reg = <PLACEHOLDER4>;
85 };
86 };
87
88 cpus {
89 #address-cells = <1>;
90 #size-cells = <0>;
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +000091
92 cpu-map {
Pierre-Clément Tosib88ad952024-05-22 11:27:45 +010093 cluster0 { PLACEHOLDER_CPU_MAP_CLUSTER };
94 cluster1 { PLACEHOLDER_CPU_MAP_CLUSTER };
95 cluster2 { PLACEHOLDER_CPU_MAP_CLUSTER };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +000096 };
97
98 cpu0: cpu@0 {
Jiyong Park196115b2023-02-25 02:01:15 +090099 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100100 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900101 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000102 reg = <0x0>;
David Dai50168a32024-02-14 17:00:48 -0800103 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800104 operating-points-v2 = <&opp_table0>;
105 opp_table0: opp-table-0 {
106 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100107 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800108 };
Jiyong Park196115b2023-02-25 02:01:15 +0900109 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000110 cpu1: cpu@1 {
Jiyong Park196115b2023-02-25 02:01:15 +0900111 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100112 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900113 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000114 reg = <0x1>;
David Dai50168a32024-02-14 17:00:48 -0800115 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800116 operating-points-v2 = <&opp_table1>;
117 opp_table1: opp-table-1 {
118 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100119 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800120 };
Jiyong Park196115b2023-02-25 02:01:15 +0900121 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000122 cpu2: cpu@2 {
Jiyong Park196115b2023-02-25 02:01:15 +0900123 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100124 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900125 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000126 reg = <0x2>;
David Dai50168a32024-02-14 17:00:48 -0800127 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800128 operating-points-v2 = <&opp_table2>;
129 opp_table2: opp-table-2 {
130 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100131 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800132 };
Jiyong Park196115b2023-02-25 02:01:15 +0900133 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000134 cpu3: cpu@3 {
Jiyong Park196115b2023-02-25 02:01:15 +0900135 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100136 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900137 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000138 reg = <0x3>;
David Dai50168a32024-02-14 17:00:48 -0800139 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800140 operating-points-v2 = <&opp_table3>;
141 opp_table3: opp-table-3 {
142 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100143 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800144 };
Jiyong Park196115b2023-02-25 02:01:15 +0900145 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000146 cpu4: cpu@4 {
Jiyong Park196115b2023-02-25 02:01:15 +0900147 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100148 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900149 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000150 reg = <0x4>;
David Dai50168a32024-02-14 17:00:48 -0800151 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800152 operating-points-v2 = <&opp_table4>;
153 opp_table4: opp-table-4 {
154 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100155 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800156 };
Jiyong Park196115b2023-02-25 02:01:15 +0900157 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000158 cpu5: cpu@5 {
Jiyong Park196115b2023-02-25 02:01:15 +0900159 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100160 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900161 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000162 reg = <0x5>;
David Dai50168a32024-02-14 17:00:48 -0800163 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800164 operating-points-v2 = <&opp_table5>;
165 opp_table5: opp-table-5 {
166 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100167 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800168 };
Jiyong Park196115b2023-02-25 02:01:15 +0900169 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000170 cpu6: cpu@6 {
Jiyong Park196115b2023-02-25 02:01:15 +0900171 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100172 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900173 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000174 reg = <0x6>;
David Dai50168a32024-02-14 17:00:48 -0800175 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800176 operating-points-v2 = <&opp_table6>;
177 opp_table6: opp-table-6 {
178 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100179 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800180 };
Jiyong Park196115b2023-02-25 02:01:15 +0900181 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000182 cpu7: cpu@7 {
Jiyong Park196115b2023-02-25 02:01:15 +0900183 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100184 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900185 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000186 reg = <0x7>;
David Dai50168a32024-02-14 17:00:48 -0800187 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800188 operating-points-v2 = <&opp_table7>;
189 opp_table7: opp-table-7 {
190 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100191 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800192 };
Jiyong Park196115b2023-02-25 02:01:15 +0900193 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000194 cpu8: cpu@8 {
Jiyong Park196115b2023-02-25 02:01:15 +0900195 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100196 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900197 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000198 reg = <0x8>;
David Dai50168a32024-02-14 17:00:48 -0800199 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800200 operating-points-v2 = <&opp_table8>;
201 opp_table8: opp-table-8 {
202 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100203 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800204 };
Jiyong Park196115b2023-02-25 02:01:15 +0900205 };
Pierre-Clément Tosia0823f12024-02-15 16:41:05 +0000206 cpu9: cpu@9 {
Jiyong Park196115b2023-02-25 02:01:15 +0900207 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100208 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900209 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000210 reg = <0x9>;
David Dai50168a32024-02-14 17:00:48 -0800211 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800212 operating-points-v2 = <&opp_table9>;
213 opp_table9: opp-table-9 {
214 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100215 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800216 };
Jiyong Park196115b2023-02-25 02:01:15 +0900217 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000218 cpu10: cpu@a {
Jiyong Park196115b2023-02-25 02:01:15 +0900219 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100220 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900221 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000222 reg = <0xa>;
David Dai50168a32024-02-14 17:00:48 -0800223 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800224 operating-points-v2 = <&opp_table10>;
225 opp_table10: opp-table-10 {
226 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100227 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800228 };
Jiyong Park196115b2023-02-25 02:01:15 +0900229 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000230 cpu11: cpu@b {
Jiyong Park196115b2023-02-25 02:01:15 +0900231 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100232 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900233 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000234 reg = <0xb>;
David Dai50168a32024-02-14 17:00:48 -0800235 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800236 operating-points-v2 = <&opp_table11>;
237 opp_table11: opp-table-11 {
238 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100239 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800240 };
Jiyong Park196115b2023-02-25 02:01:15 +0900241 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000242 cpu12: cpu@c {
Jiyong Park196115b2023-02-25 02:01:15 +0900243 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100244 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900245 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000246 reg = <0xc>;
David Dai50168a32024-02-14 17:00:48 -0800247 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800248 operating-points-v2 = <&opp_table12>;
249 opp_table12: opp-table-12 {
250 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100251 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800252 };
Jiyong Park196115b2023-02-25 02:01:15 +0900253 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000254 cpu13: cpu@d {
Jiyong Park196115b2023-02-25 02:01:15 +0900255 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100256 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900257 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000258 reg = <0xd>;
David Dai50168a32024-02-14 17:00:48 -0800259 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800260 operating-points-v2 = <&opp_table13>;
261 opp_table13: opp-table-13 {
262 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100263 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800264 };
Jiyong Park196115b2023-02-25 02:01:15 +0900265 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000266 cpu14: cpu@e {
Jiyong Park196115b2023-02-25 02:01:15 +0900267 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100268 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900269 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000270 reg = <0xe>;
David Dai50168a32024-02-14 17:00:48 -0800271 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800272 operating-points-v2 = <&opp_table14>;
273 opp_table14: opp-table-14 {
274 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100275 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800276 };
Jiyong Park196115b2023-02-25 02:01:15 +0900277 };
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000278 cpu15: cpu@f {
Jiyong Park196115b2023-02-25 02:01:15 +0900279 device_type = "cpu";
Pierre-Clément Tosi6ae8fe22024-04-17 20:02:23 +0100280 compatible = "arm,armv8";
Jiyong Park196115b2023-02-25 02:01:15 +0900281 enable-method = "psci";
Pierre-Clément Tosi27a2b032024-03-26 16:36:11 +0000282 reg = <0xf>;
David Dai50168a32024-02-14 17:00:48 -0800283 capacity-dmips-mhz = <PLACEHOLDER>;
David Dai9bdb10c2024-02-01 22:42:54 -0800284 operating-points-v2 = <&opp_table15>;
285 opp_table15: opp-table-15 {
286 compatible = "operating-points-v2";
Pierre-Clément Tosie73fdcf2024-04-16 15:21:40 +0100287 PLACEHOLDER_OPP_TABLE
David Dai9bdb10c2024-02-01 22:42:54 -0800288 };
Jiyong Park196115b2023-02-25 02:01:15 +0900289 };
290 };
291
292 intc: intc {
293 compatible = "arm,gic-v3";
294 #address-cells = <2>;
295 #size-cells = <2>;
296 #interrupt-cells = <3>;
297 interrupt-controller;
298 reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
299 };
300
301 timer {
302 compatible = "arm,armv8-timer";
303 always-on;
304 /* The IRQ type needs to be OR-ed with the CPU mask */
305 interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
306 GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
307 GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
308 GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
309 };
310
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900311 uart@3f8 {
Jiyong Park196115b2023-02-25 02:01:15 +0900312 compatible = "ns16550a";
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900313 reg = <0x00 0x3f8 0x00 0x8>;
Jiyong Park196115b2023-02-25 02:01:15 +0900314 clock-frequency = <0x1c2000>;
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900315 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
Jiyong Park196115b2023-02-25 02:01:15 +0900316 };
317
318 uart@2f8 {
319 compatible = "ns16550a";
320 reg = <0x00 0x2f8 0x00 0x8>;
321 clock-frequency = <0x1c2000>;
322 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
323 };
324
325 uart@3e8 {
326 compatible = "ns16550a";
327 reg = <0x00 0x3e8 0x00 0x8>;
328 clock-frequency = <0x1c2000>;
329 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
330 };
331
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900332 uart@2e8 {
Jiyong Park196115b2023-02-25 02:01:15 +0900333 compatible = "ns16550a";
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900334 reg = <0x00 0x2e8 0x00 0x8>;
Jiyong Park196115b2023-02-25 02:01:15 +0900335 clock-frequency = <0x1c2000>;
Jiyong Park1ba9b4a2024-05-28 22:21:57 +0900336 interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
Jiyong Park196115b2023-02-25 02:01:15 +0900337 };
338
339 psci {
340 compatible = "arm,psci-1.0";
341 method = "hvc";
342 };
343
344 pci {
345 compatible = "pci-host-cam-generic";
346 device_type = "pci";
347 #address-cells = <3>;
348 #size-cells = <2>;
349 #interrupt-cells = <1>;
350 dma-coherent;
351 memory-region = <&swiotlb>;
352 ranges = <
353 0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
354 0x3000000 PLACEHOLDER2 PLACEHOLDER2 PLACEHOLDER2
355 >;
356 bus-range = <0x00 0x00>;
357 reg = <0x00 0x10000 0x00 0x1000000>;
358 interrupt-map = <
Jiyong Parka503f422023-03-21 19:27:04 +0900359 0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH
360 0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH
361 0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH
362 0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH
363 0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH
364 0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH
365 0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH
366 0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH
Nikita Ioffe85d80262023-07-12 17:34:07 +0100367 0x4800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 8) IRQ_TYPE_LEVEL_HIGH
368 0x5000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 9) IRQ_TYPE_LEVEL_HIGH
Nikita Ioffe2d0969c2024-06-06 12:59:12 +0000369 0x5800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 10) IRQ_TYPE_LEVEL_HIGH
370 0x6000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 11) IRQ_TYPE_LEVEL_HIGH
371 0x6800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 12) IRQ_TYPE_LEVEL_HIGH
372 0x7000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 13) IRQ_TYPE_LEVEL_HIGH
373 0x7800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 14) IRQ_TYPE_LEVEL_HIGH
374 0x8000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 15) IRQ_TYPE_LEVEL_HIGH
Jiyong Park196115b2023-02-25 02:01:15 +0900375 >;
376 interrupt-map-mask = <0xf800 0x0 0x0 0x7
377 0xf800 0x0 0x0 0x7
378 0xf800 0x0 0x0 0x7
379 0xf800 0x0 0x0 0x7
380 0xf800 0x0 0x0 0x7
381 0xf800 0x0 0x0 0x7
Jiyong Parka503f422023-03-21 19:27:04 +0900382 0xf800 0x0 0x0 0x7
Nikita Ioffe85d80262023-07-12 17:34:07 +0100383 0xf800 0x0 0x0 0x7
384 0xf800 0x0 0x0 0x7
Nikita Ioffe2d0969c2024-06-06 12:59:12 +0000385 0xf800 0x0 0x0 0x7
386 0xf800 0x0 0x0 0x7
387 0xf800 0x0 0x0 0x7
388 0xf800 0x0 0x0 0x7
389 0xf800 0x0 0x0 0x7
390 0xf800 0x0 0x0 0x7
Jiyong Park196115b2023-02-25 02:01:15 +0900391 0xf800 0x0 0x0 0x7>;
392 };
393
394 clk: pclk@3M {
395 compatible = "fixed-clock";
396 clock-frequency = <0x2fefd8>;
397 #clock-cells = <0>;
398 };
399
400 rtc@2000 {
401 compatible = "arm,primecell";
402 arm,primecell-periphid = <0x41030>;
403 reg = <0x00 0x2000 0x00 0x1000>;
404 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
405 clock-names = "apb_pclk";
406 clocks = <&clk>;
407 };
Sebastian Ene21d12bf2023-03-14 11:04:58 +0000408
409 vmwdt@3000 {
410 compatible = "qemu,vcpu-stall-detector";
411 reg = <0x00 0x3000 0x00 0x1000>;
412 clock-frequency = <10>;
413 timeout-sec = <8>;
414 };
Jaewan Kim96411e92023-11-13 15:54:02 +0900415
Jaewan Kim8f6f4662023-12-12 17:38:47 +0900416 cpufreq {
417 compatible = "virtual,android-v-only-cpufreq";
418 reg = <0x0 0x1040000 PLACEHOLDER2>;
419 };
420
421 // Keep pvIOMMUs at the last for making test happy.
422 // Otherwise, phandle of other nodes are changed when unused pvIOMMU nodes
423 // are removed, so hardcoded phandles in test data would mismatch.
Jaewan Kim96411e92023-11-13 15:54:02 +0900424 pviommu_0: pviommu0 {
425 compatible = "pkvm,pviommu";
426 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900427 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900428 };
429
430 pviommu_1: pviommu1 {
431 compatible = "pkvm,pviommu";
432 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900433 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900434 };
435
436 pviommu_2: pviommu2 {
437 compatible = "pkvm,pviommu";
438 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900439 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900440 };
441
442 pviommu_3: pviommu3 {
443 compatible = "pkvm,pviommu";
444 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900445 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900446 };
447
448 pviommu_4: pviommu4 {
449 compatible = "pkvm,pviommu";
450 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900451 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900452 };
453
454 pviommu_5: pviommu5 {
455 compatible = "pkvm,pviommu";
456 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900457 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900458 };
459
460 pviommu_6: pviommu6 {
461 compatible = "pkvm,pviommu";
462 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900463 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900464 };
465
466 pviommu_7: pviommu7 {
467 compatible = "pkvm,pviommu";
468 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900469 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900470 };
471
472 pviommu_8: pviommu8 {
473 compatible = "pkvm,pviommu";
474 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900475 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900476 };
477
478 pviommu_9: pviommu9 {
479 compatible = "pkvm,pviommu";
480 id = <PLACEHOLDER>;
Jaewan Kimf2542452023-12-01 15:03:51 +0900481 #iommu-cells = <1>;
Jaewan Kim96411e92023-11-13 15:54:02 +0900482 };
David Dai9bdb10c2024-02-01 22:42:54 -0800483
Jaewan Kim8f6f4662023-12-12 17:38:47 +0900484 // Do not add new node below
Jiyong Park196115b2023-02-25 02:01:15 +0900485};