pvmfw/platform.dts

/*
 * Copyright (C) 2022 Google LLC
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

#define PLACEHOLDER	0xffffffff
#define PLACEHOLDER2	PLACEHOLDER PLACEHOLDER
#define PLACEHOLDER4	PLACEHOLDER2 PLACEHOLDER2

#define PLACEHOLDER_CPU_MAP_CORE(n) core##n { cpu = <PLACEHOLDER>; };
#define PLACEHOLDER_CPU_MAP_CLUSTER \
	PLACEHOLDER_CPU_MAP_CORE(0) \
	PLACEHOLDER_CPU_MAP_CORE(1) \
	PLACEHOLDER_CPU_MAP_CORE(2) \
	PLACEHOLDER_CPU_MAP_CORE(3) \
	PLACEHOLDER_CPU_MAP_CORE(4) \
	PLACEHOLDER_CPU_MAP_CORE(5) \
	PLACEHOLDER_CPU_MAP_CORE(6) \
	PLACEHOLDER_CPU_MAP_CORE(7) \
	PLACEHOLDER_CPU_MAP_CORE(8) \
	PLACEHOLDER_CPU_MAP_CORE(9)

#define PLACEHOLDER_OPP_TABLE_ENTRY(n) opp##n { opp-hz = <PLACEHOLDER2>; };
#define PLACEHOLDER_OPP_TABLE \
	PLACEHOLDER_OPP_TABLE_ENTRY(1) \
	PLACEHOLDER_OPP_TABLE_ENTRY(2) \
	PLACEHOLDER_OPP_TABLE_ENTRY(3) \
	PLACEHOLDER_OPP_TABLE_ENTRY(4) \
	PLACEHOLDER_OPP_TABLE_ENTRY(5) \
	PLACEHOLDER_OPP_TABLE_ENTRY(6) \
	PLACEHOLDER_OPP_TABLE_ENTRY(7) \
	PLACEHOLDER_OPP_TABLE_ENTRY(8) \
	PLACEHOLDER_OPP_TABLE_ENTRY(9) \
	PLACEHOLDER_OPP_TABLE_ENTRY(10) \
	PLACEHOLDER_OPP_TABLE_ENTRY(11) \
	PLACEHOLDER_OPP_TABLE_ENTRY(12) \
	PLACEHOLDER_OPP_TABLE_ENTRY(13) \
	PLACEHOLDER_OPP_TABLE_ENTRY(14) \
	PLACEHOLDER_OPP_TABLE_ENTRY(15) \
	PLACEHOLDER_OPP_TABLE_ENTRY(16) \
	PLACEHOLDER_OPP_TABLE_ENTRY(17) \
	PLACEHOLDER_OPP_TABLE_ENTRY(18) \
	PLACEHOLDER_OPP_TABLE_ENTRY(19) \
	PLACEHOLDER_OPP_TABLE_ENTRY(20)

#define IRQ_BASE 4

/dts-v1/;

/ {
	interrupt-parent = <&intc>;
	compatible = "linux,dummy-virt";
	#address-cells = <2>;
	#size-cells = <2>;

	chosen {
		stdout-path = "/uart@3f8";
		linux,pci-probe-only = <1>;
		kaslr-seed = <PLACEHOLDER2>;
		avf,strict-boot;
		avf,new-instance;
	};

	memory {
		device_type = "memory";
		reg = <0x00 0x80000000 PLACEHOLDER2>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		swiotlb: restricted_dma_reserved {
			compatible = "restricted-dma-pool";
			reg = <PLACEHOLDER4>;
			size = <PLACEHOLDER2>;
			alignment = <PLACEHOLDER2>;
		};

		dice {
			compatible = "google,open-dice";
			no-map;
			reg = <PLACEHOLDER4>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 { PLACEHOLDER_CPU_MAP_CLUSTER };
			cluster1 { PLACEHOLDER_CPU_MAP_CLUSTER };
			cluster2 { PLACEHOLDER_CPU_MAP_CLUSTER };
		};

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x0>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table0>;
			opp_table0: opp-table-0 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x1>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table1>;
			opp_table1: opp-table-1 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x2>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table2>;
			opp_table2: opp-table-2 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x3>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table3>;
			opp_table3: opp-table-3 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x4>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table4>;
			opp_table4: opp-table-4 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x5>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table5>;
			opp_table5: opp-table-5 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x6>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table6>;
			opp_table6: opp-table-6 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x7>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table7>;
			opp_table7: opp-table-7 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu8: cpu@8 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x8>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table8>;
			opp_table8: opp-table-8 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu9: cpu@9 {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0x9>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table9>;
			opp_table9: opp-table-9 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu10: cpu@a {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xa>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table10>;
			opp_table10: opp-table-10 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu11: cpu@b {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xb>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table11>;
			opp_table11: opp-table-11 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu12: cpu@c {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xc>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table12>;
			opp_table12: opp-table-12 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu13: cpu@d {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xd>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table13>;
			opp_table13: opp-table-13 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu14: cpu@e {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xe>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table14>;
			opp_table14: opp-table-14 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
		cpu15: cpu@f {
			device_type = "cpu";
			compatible = "arm,armv8";
			enable-method = "psci";
			reg = <0xf>;
			capacity-dmips-mhz = <PLACEHOLDER>;
			operating-points-v2 = <&opp_table15>;
			opp_table15: opp-table-15 {
				compatible = "operating-points-v2";
				PLACEHOLDER_OPP_TABLE
			};
		};
	};

	intc: intc {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x3fff0000 0x00 0x10000>, <PLACEHOLDER4>;
	};

	timer {
		compatible = "arm,armv8-timer";
		always-on;
		/* The IRQ type needs to be OR-ed with the CPU mask */
		interrupts = <GIC_PPI 0xd IRQ_TYPE_LEVEL_LOW
		              GIC_PPI 0xe IRQ_TYPE_LEVEL_LOW
			      GIC_PPI 0xb IRQ_TYPE_LEVEL_LOW
			      GIC_PPI 0xa IRQ_TYPE_LEVEL_LOW>;
	};

	uart@3f8 {
		compatible = "ns16550a";
		reg = <0x00 0x3f8 0x00 0x8>;
		clock-frequency = <0x1c2000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
	};

	uart@2f8 {
		compatible = "ns16550a";
		reg = <0x00 0x2f8 0x00 0x8>;
		clock-frequency = <0x1c2000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
	};

	uart@3e8 {
		compatible = "ns16550a";
		reg = <0x00 0x3e8 0x00 0x8>;
		clock-frequency = <0x1c2000>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
	};

	uart@2e8 {
		compatible = "ns16550a";
		reg = <0x00 0x2e8 0x00 0x8>;
		clock-frequency = <0x1c2000>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "hvc";
	};

	pci {
		compatible = "pci-host-cam-generic";
		device_type = "pci";
		#address-cells = <3>;
		#size-cells = <2>;
		#interrupt-cells = <1>;
		dma-coherent;
		memory-region = <&swiotlb>;
		ranges = <
			0x3000000 0x0 0x02000000 0x0 0x02000000 0x00 0x02000000
			0x3000000 PLACEHOLDER2   PLACEHOLDER2   PLACEHOLDER2
		>;
		bus-range = <0x00 0x00>;
		reg = <0x00 0x10000 0x00 0x1000000>;
		interrupt-map = <
			0x0800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 0) IRQ_TYPE_LEVEL_HIGH
			0x1000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 1) IRQ_TYPE_LEVEL_HIGH
			0x1800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 2) IRQ_TYPE_LEVEL_HIGH
			0x2000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 3) IRQ_TYPE_LEVEL_HIGH
			0x2800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 4) IRQ_TYPE_LEVEL_HIGH
			0x3000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 5) IRQ_TYPE_LEVEL_HIGH
			0x3800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 6) IRQ_TYPE_LEVEL_HIGH
			0x4000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 7) IRQ_TYPE_LEVEL_HIGH
			0x4800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 8) IRQ_TYPE_LEVEL_HIGH
			0x5000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 9) IRQ_TYPE_LEVEL_HIGH
			0x5800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 10) IRQ_TYPE_LEVEL_HIGH
			0x6000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 11) IRQ_TYPE_LEVEL_HIGH
			0x6800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 12) IRQ_TYPE_LEVEL_HIGH
			0x7000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 13) IRQ_TYPE_LEVEL_HIGH
			0x7800 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 14) IRQ_TYPE_LEVEL_HIGH
			0x8000 0x0 0x0 1 &intc 0 0 GIC_SPI (IRQ_BASE + 15) IRQ_TYPE_LEVEL_HIGH
		>;
		interrupt-map-mask = <0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7
				      0xf800 0x0 0x0 0x7>;
	};

	clk: pclk@3M {
		compatible = "fixed-clock";
		clock-frequency = <0x2fefd8>;
		#clock-cells = <0>;
	};

	rtc@2000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x41030>;
		reg = <0x00 0x2000 0x00 0x1000>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "apb_pclk";
		clocks = <&clk>;
	};

	vmwdt@3000 {
		compatible = "qemu,vcpu-stall-detector";
		reg = <0x00 0x3000 0x00 0x1000>;
		clock-frequency = <10>;
		timeout-sec = <8>;
	};

	cpufreq {
		compatible = "virtual,android-v-only-cpufreq";
		reg = <0x0 0x1040000 PLACEHOLDER2>;
	};

	// Keep pvIOMMUs at the last for making test happy.
	// Otherwise, phandle of other nodes are changed when unused pvIOMMU nodes
	// are removed, so hardcoded phandles in test data would mismatch.
	pviommu_0: pviommu0 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_1: pviommu1 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_2: pviommu2 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_3: pviommu3 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_4: pviommu4 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_5: pviommu5 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_6: pviommu6 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_7: pviommu7 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_8: pviommu8 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	pviommu_9: pviommu9 {
		compatible = "pkvm,pviommu";
		id = <PLACEHOLDER>;
		#iommu-cells = <1>;
	};

	// Do not add new node below
};