Pierre-Clément Tosi | a0934c1 | 2022-11-25 20:54:11 +0000 | [diff] [blame] | 1 | // Copyright 2022, The Android Open Source Project |
| 2 | // |
| 3 | // Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | // you may not use this file except in compliance with the License. |
| 5 | // You may obtain a copy of the License at |
| 6 | // |
| 7 | // http://www.apache.org/licenses/LICENSE-2.0 |
| 8 | // |
| 9 | // Unless required by applicable law or agreed to in writing, software |
| 10 | // distributed under the License is distributed on an "AS IS" BASIS, |
| 11 | // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 12 | // See the License for the specific language governing permissions and |
| 13 | // limitations under the License. |
| 14 | |
| 15 | //! Low-level allocation and tracking of main memory. |
| 16 | |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 17 | use crate::entry::RebootReason; |
| 18 | use crate::fdt; |
Pierre-Clément Tosi | ad1fc75 | 2023-05-31 16:56:56 +0000 | [diff] [blame] | 19 | use aarch64_paging::MapError; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 20 | use core::num::NonZeroUsize; |
Pierre-Clément Tosi | a0934c1 | 2022-11-25 20:54:11 +0000 | [diff] [blame] | 21 | use core::result; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 22 | use core::slice; |
| 23 | use log::debug; |
Alice Wang | 93ee98a | 2023-06-08 08:20:39 +0000 | [diff] [blame] | 24 | use log::error; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 25 | use log::info; |
| 26 | use log::warn; |
Pierre-Clément Tosi | 3d4c5c3 | 2023-05-31 16:57:06 +0000 | [diff] [blame] | 27 | use vmbase::{ |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 28 | layout::{self, crosvm}, |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 29 | memory::{init_shared_pool, map_data, map_rodata, resize_available_memory, PageTable}, |
Pierre-Clément Tosi | 3d4c5c3 | 2023-05-31 16:57:06 +0000 | [diff] [blame] | 30 | }; |
Pierre-Clément Tosi | a0934c1 | 2022-11-25 20:54:11 +0000 | [diff] [blame] | 31 | |
Pierre-Clément Tosi | ad1fc75 | 2023-05-31 16:56:56 +0000 | [diff] [blame] | 32 | pub fn init_page_table() -> result::Result<PageTable, MapError> { |
Alice Wang | ee5b180 | 2023-06-07 07:41:54 +0000 | [diff] [blame] | 33 | let mut page_table = PageTable::default(); |
Pierre-Clément Tosi | ad1fc75 | 2023-05-31 16:56:56 +0000 | [diff] [blame] | 34 | |
| 35 | // Stack and scratch ranges are explicitly zeroed and flushed before jumping to payload, |
| 36 | // so dirty state management can be omitted. |
Pierre-Clément Tosi | 0b02a2b | 2024-11-28 22:48:27 +0000 | [diff] [blame] | 37 | page_table.map_data(&layout::data_bss_range().into())?; |
| 38 | page_table.map_data(&layout::eh_stack_range().into())?; |
Pierre-Clément Tosi | eba8316 | 2024-11-02 12:11:48 +0000 | [diff] [blame^] | 39 | page_table.map_data(&layout::stack_range().into())?; |
Alice Wang | a3931aa | 2023-07-05 12:52:09 +0000 | [diff] [blame] | 40 | page_table.map_code(&layout::text_range().into())?; |
| 41 | page_table.map_rodata(&layout::rodata_range().into())?; |
Pierre-Clément Tosi | 38a3621 | 2024-06-06 11:30:39 +0100 | [diff] [blame] | 42 | if let Err(e) = page_table.map_device(&layout::console_uart_page().into()) { |
Alice Wang | 807fa59 | 2023-06-02 09:54:43 +0000 | [diff] [blame] | 43 | error!("Failed to remap the UART as a dynamic page table entry: {e}"); |
| 44 | return Err(e); |
| 45 | } |
Pierre-Clément Tosi | ad1fc75 | 2023-05-31 16:56:56 +0000 | [diff] [blame] | 46 | Ok(page_table) |
| 47 | } |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 48 | |
| 49 | pub(crate) struct MemorySlices<'a> { |
| 50 | pub fdt: &'a mut libfdt::Fdt, |
| 51 | pub kernel: &'a [u8], |
| 52 | pub ramdisk: Option<&'a [u8]>, |
| 53 | } |
| 54 | |
| 55 | impl<'a> MemorySlices<'a> { |
| 56 | pub fn new( |
| 57 | fdt: usize, |
| 58 | kernel: usize, |
| 59 | kernel_size: usize, |
| 60 | vm_dtbo: Option<&mut [u8]>, |
| 61 | vm_ref_dt: Option<&[u8]>, |
| 62 | ) -> Result<Self, RebootReason> { |
| 63 | let fdt_size = NonZeroUsize::new(crosvm::FDT_MAX_SIZE).unwrap(); |
| 64 | // TODO - Only map the FDT as read-only, until we modify it right before jump_to_payload() |
| 65 | // e.g. by generating a DTBO for a template DT in main() and, on return, re-map DT as RW, |
| 66 | // overwrite with the template DT and apply the DTBO. |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 67 | map_data(fdt, fdt_size).map_err(|e| { |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 68 | error!("Failed to allocate the FDT range: {e}"); |
| 69 | RebootReason::InternalError |
| 70 | })?; |
| 71 | |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 72 | // SAFETY: map_data validated the range to be in main memory, mapped, and not overlap. |
| 73 | let fdt = unsafe { slice::from_raw_parts_mut(fdt as *mut u8, fdt_size.into()) }; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 74 | |
| 75 | let info = fdt::sanitize_device_tree(fdt, vm_dtbo, vm_ref_dt)?; |
| 76 | let fdt = libfdt::Fdt::from_mut_slice(fdt).map_err(|e| { |
| 77 | error!("Failed to load sanitized FDT: {e}"); |
| 78 | RebootReason::InvalidFdt |
| 79 | })?; |
| 80 | debug!("Fdt passed validation!"); |
| 81 | |
| 82 | let memory_range = info.memory_range; |
| 83 | debug!("Resizing MemoryTracker to range {memory_range:#x?}"); |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 84 | resize_available_memory(&memory_range).map_err(|e| { |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 85 | error!("Failed to use memory range value from DT: {memory_range:#x?}: {e}"); |
| 86 | RebootReason::InvalidFdt |
| 87 | })?; |
| 88 | |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 89 | init_shared_pool(info.swiotlb_info.fixed_range()).map_err(|e| { |
| 90 | error!("Failed to initialize shared pool: {e}"); |
| 91 | RebootReason::InternalError |
| 92 | })?; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 93 | |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 94 | let (kernel_start, kernel_size) = if let Some(r) = info.kernel_range { |
| 95 | let size = r.len().try_into().map_err(|_| { |
| 96 | error!("Invalid kernel size: {:#x}", r.len()); |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 97 | RebootReason::InternalError |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 98 | })?; |
| 99 | (r.start, size) |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 100 | } else if cfg!(feature = "legacy") { |
| 101 | warn!("Failed to find the kernel range in the DT; falling back to legacy ABI"); |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 102 | let size = NonZeroUsize::new(kernel_size).ok_or_else(|| { |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 103 | error!("Invalid kernel size: {kernel_size:#x}"); |
| 104 | RebootReason::InvalidPayload |
| 105 | })?; |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 106 | (kernel, size) |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 107 | } else { |
| 108 | error!("Failed to locate the kernel from the DT"); |
| 109 | return Err(RebootReason::InvalidPayload); |
| 110 | }; |
| 111 | |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 112 | map_rodata(kernel_start, kernel_size).map_err(|e| { |
| 113 | error!("Failed to map kernel range: {e}"); |
| 114 | RebootReason::InternalError |
| 115 | })?; |
| 116 | |
| 117 | let kernel = kernel_start as *const u8; |
| 118 | // SAFETY: map_rodata validated the range to be in main memory, mapped, and not overlap. |
| 119 | let kernel = unsafe { slice::from_raw_parts(kernel, kernel_size.into()) }; |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 120 | |
| 121 | let ramdisk = if let Some(r) = info.initrd_range { |
| 122 | debug!("Located ramdisk at {r:?}"); |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 123 | let ramdisk_size = r.len().try_into().map_err(|_| { |
| 124 | error!("Invalid ramdisk size: {:#x}", r.len()); |
| 125 | RebootReason::InvalidRamdisk |
| 126 | })?; |
| 127 | map_rodata(r.start, ramdisk_size).map_err(|e| { |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 128 | error!("Failed to obtain the initrd range: {e}"); |
| 129 | RebootReason::InvalidRamdisk |
| 130 | })?; |
| 131 | |
Pierre-Clément Tosi | c26e220 | 2024-11-01 23:12:23 +0000 | [diff] [blame] | 132 | // SAFETY: map_rodata validated the range to be in main memory, mapped, and not |
| 133 | // overlap. |
Pierre-Clément Tosi | 462bdf4 | 2024-10-30 17:46:23 +0000 | [diff] [blame] | 134 | Some(unsafe { slice::from_raw_parts(r.start as *const u8, r.len()) }) |
| 135 | } else { |
| 136 | info!("Couldn't locate the ramdisk from the device tree"); |
| 137 | None |
| 138 | }; |
| 139 | |
| 140 | Ok(Self { fdt, kernel, ramdisk }) |
| 141 | } |
| 142 | } |