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Ben Cheng655a7c02013-10-16 16:09:24 -07001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
25#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
Christopher Ferris38062f92014-07-09 15:33:25 -070026#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -070027struct drm_tegra_gem_create {
Tao Baod7db5942015-01-28 10:07:51 -080028 __u64 size;
29 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -080030 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -070031};
Ben Cheng655a7c02013-10-16 16:09:24 -070032struct drm_tegra_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -080033 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080034 __u32 pad;
35 __u64 offset;
Ben Cheng655a7c02013-10-16 16:09:24 -070036};
Ben Cheng655a7c02013-10-16 16:09:24 -070037struct drm_tegra_syncpt_read {
Christopher Ferris05d08e92016-02-04 13:16:38 -080038 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080039 __u32 value;
Ben Cheng655a7c02013-10-16 16:09:24 -070040};
Ben Cheng655a7c02013-10-16 16:09:24 -070041struct drm_tegra_syncpt_incr {
Christopher Ferris05d08e92016-02-04 13:16:38 -080042 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080043 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070044};
Ben Cheng655a7c02013-10-16 16:09:24 -070045struct drm_tegra_syncpt_wait {
Christopher Ferris05d08e92016-02-04 13:16:38 -080046 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -080047 __u32 thresh;
48 __u32 timeout;
49 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -080050};
Ben Cheng655a7c02013-10-16 16:09:24 -070051#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
52struct drm_tegra_open_channel {
Tao Baod7db5942015-01-28 10:07:51 -080053 __u32 client;
Christopher Ferris05d08e92016-02-04 13:16:38 -080054 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -080055 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -070056};
Ben Cheng655a7c02013-10-16 16:09:24 -070057struct drm_tegra_close_channel {
Christopher Ferris05d08e92016-02-04 13:16:38 -080058 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -070059};
60struct drm_tegra_get_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -080061 __u64 context;
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 __u32 index;
Tao Baod7db5942015-01-28 10:07:51 -080063 __u32 id;
Christopher Ferris38062f92014-07-09 15:33:25 -070064};
65struct drm_tegra_get_syncpt_base {
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 __u64 context;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 syncpt;
68 __u32 id;
Ben Cheng655a7c02013-10-16 16:09:24 -070069};
Christopher Ferris05d08e92016-02-04 13:16:38 -080070struct drm_tegra_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -080071 __u32 id;
72 __u32 incrs;
Ben Cheng655a7c02013-10-16 16:09:24 -070073};
Christopher Ferris05d08e92016-02-04 13:16:38 -080074struct drm_tegra_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -080075 __u32 handle;
76 __u32 offset;
77 __u32 words;
Christopher Ferris05d08e92016-02-04 13:16:38 -080078 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070079};
80struct drm_tegra_reloc {
Tao Baod7db5942015-01-28 10:07:51 -080081 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080082 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -080083 __u32 offset;
84 } cmdbuf;
85 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -080086 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -080087 __u32 offset;
88 } target;
89 __u32 shift;
Christopher Ferris05d08e92016-02-04 13:16:38 -080090 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -070091};
92struct drm_tegra_waitchk {
Tao Baod7db5942015-01-28 10:07:51 -080093 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -080094 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -080095 __u32 syncpt;
96 __u32 thresh;
Ben Cheng655a7c02013-10-16 16:09:24 -070097};
Christopher Ferris05d08e92016-02-04 13:16:38 -080098struct drm_tegra_submit {
Tao Baod7db5942015-01-28 10:07:51 -080099 __u64 context;
100 __u32 num_syncpts;
101 __u32 num_cmdbufs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800102 __u32 num_relocs;
Tao Baod7db5942015-01-28 10:07:51 -0800103 __u32 num_waitchks;
104 __u32 waitchk_mask;
105 __u32 timeout;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106 __u64 syncpts;
Tao Baod7db5942015-01-28 10:07:51 -0800107 __u64 cmdbufs;
108 __u64 relocs;
109 __u64 waitchks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800110 __u32 fence;
Tao Baod7db5942015-01-28 10:07:51 -0800111 __u32 reserved[5];
Ben Cheng655a7c02013-10-16 16:09:24 -0700112};
Christopher Ferris82d75042015-01-26 10:57:07 -0800113#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800114#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800115#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
116struct drm_tegra_gem_set_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800117 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800118 __u32 mode;
Tao Baod7db5942015-01-28 10:07:51 -0800119 __u32 value;
120 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800121};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800122struct drm_tegra_gem_get_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800123 __u32 handle;
124 __u32 mode;
125 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800126 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800127};
128#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
129#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
130struct drm_tegra_gem_set_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800131 __u32 handle;
132 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800133};
134struct drm_tegra_gem_get_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800135 __u32 handle;
136 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800137};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800138#define DRM_TEGRA_GEM_CREATE 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800139#define DRM_TEGRA_GEM_MMAP 0x01
Ben Cheng655a7c02013-10-16 16:09:24 -0700140#define DRM_TEGRA_SYNCPT_READ 0x02
141#define DRM_TEGRA_SYNCPT_INCR 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800142#define DRM_TEGRA_SYNCPT_WAIT 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800143#define DRM_TEGRA_OPEN_CHANNEL 0x05
Ben Cheng655a7c02013-10-16 16:09:24 -0700144#define DRM_TEGRA_CLOSE_CHANNEL 0x06
145#define DRM_TEGRA_GET_SYNCPT 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800146#define DRM_TEGRA_SUBMIT 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800147#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
148#define DRM_TEGRA_GEM_SET_TILING 0x0a
149#define DRM_TEGRA_GEM_GET_TILING 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800150#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
Christopher Ferris82d75042015-01-26 10:57:07 -0800151#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
Ben Cheng655a7c02013-10-16 16:09:24 -0700152#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
153#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Christopher Ferris82d75042015-01-26 10:57:07 -0800155#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Ben Cheng655a7c02013-10-16 16:09:24 -0700156#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
157#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris9ce28842018-10-25 12:11:39 -0700158#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel)
Christopher Ferris82d75042015-01-26 10:57:07 -0800159#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Ben Cheng655a7c02013-10-16 16:09:24 -0700160#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
Christopher Ferris38062f92014-07-09 15:33:25 -0700161#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800162#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
Christopher Ferris82d75042015-01-26 10:57:07 -0800163#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
164#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
165#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700166#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800167}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700168#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800169#endif