Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 1 | /**************************************************************************** |
| 2 | **************************************************************************** |
| 3 | *** |
| 4 | *** This header was automatically generated from a Linux kernel header |
| 5 | *** of the same name, to make information necessary for userspace to |
| 6 | *** call into the kernel available to libc. It contains only constants, |
| 7 | *** structures, and macros generated from the original header, and thus, |
| 8 | *** contains no copyrightable information. |
| 9 | *** |
| 10 | *** To edit the content of this header, modify the corresponding |
| 11 | *** source file (e.g. under external/kernel-headers/original/) then |
| 12 | *** run bionic/libc/kernel/tools/update_all.py |
| 13 | *** |
| 14 | *** Any manual change here will be lost the next time this script will |
| 15 | *** be run. You've been warned! |
| 16 | *** |
| 17 | **************************************************************************** |
| 18 | ****************************************************************************/ |
| 19 | #ifndef _UAPI_TEGRA_DRM_H_ |
| 20 | #define _UAPI_TEGRA_DRM_H_ |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 21 | #include "drm.h" |
| 22 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame] | 23 | extern "C" { |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 24 | #endif |
| 25 | #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 26 | #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 27 | struct drm_tegra_gem_create { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 28 | __u64 size; |
| 29 | __u32 flags; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 30 | __u32 handle; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 31 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 32 | struct drm_tegra_gem_mmap { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 33 | __u32 handle; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 34 | __u32 pad; |
| 35 | __u64 offset; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 36 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 37 | struct drm_tegra_syncpt_read { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 38 | __u32 id; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 39 | __u32 value; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 40 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 41 | struct drm_tegra_syncpt_incr { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 42 | __u32 id; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 43 | __u32 pad; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 44 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 45 | struct drm_tegra_syncpt_wait { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 46 | __u32 id; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 47 | __u32 thresh; |
| 48 | __u32 timeout; |
| 49 | __u32 value; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 50 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 51 | #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) |
| 52 | struct drm_tegra_open_channel { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 53 | __u32 client; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 54 | __u32 pad; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 55 | __u64 context; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 56 | }; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 57 | struct drm_tegra_close_channel { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 58 | __u64 context; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 59 | }; |
| 60 | struct drm_tegra_get_syncpt { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 61 | __u64 context; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 62 | __u32 index; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 63 | __u32 id; |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 64 | }; |
| 65 | struct drm_tegra_get_syncpt_base { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 66 | __u64 context; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 67 | __u32 syncpt; |
| 68 | __u32 id; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 69 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 70 | struct drm_tegra_syncpt { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 71 | __u32 id; |
| 72 | __u32 incrs; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 73 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 74 | struct drm_tegra_cmdbuf { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 75 | __u32 handle; |
| 76 | __u32 offset; |
| 77 | __u32 words; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 78 | __u32 pad; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 79 | }; |
| 80 | struct drm_tegra_reloc { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 81 | struct { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 82 | __u32 handle; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 83 | __u32 offset; |
| 84 | } cmdbuf; |
| 85 | struct { |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 86 | __u32 handle; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 87 | __u32 offset; |
| 88 | } target; |
| 89 | __u32 shift; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 90 | __u32 pad; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 91 | }; |
| 92 | struct drm_tegra_waitchk { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 93 | __u32 handle; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 94 | __u32 offset; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 95 | __u32 syncpt; |
| 96 | __u32 thresh; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 97 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 98 | struct drm_tegra_submit { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 99 | __u64 context; |
| 100 | __u32 num_syncpts; |
| 101 | __u32 num_cmdbufs; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 102 | __u32 num_relocs; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 103 | __u32 num_waitchks; |
| 104 | __u32 waitchk_mask; |
| 105 | __u32 timeout; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 106 | __u64 syncpts; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 107 | __u64 cmdbufs; |
| 108 | __u64 relocs; |
| 109 | __u64 waitchks; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 110 | __u32 fence; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 111 | __u32 reserved[5]; |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 112 | }; |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 113 | #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 114 | #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 115 | #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 |
| 116 | struct drm_tegra_gem_set_tiling { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 117 | __u32 handle; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 118 | __u32 mode; |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 119 | __u32 value; |
| 120 | __u32 pad; |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 121 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 122 | struct drm_tegra_gem_get_tiling { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 123 | __u32 handle; |
| 124 | __u32 mode; |
| 125 | __u32 value; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 126 | __u32 pad; |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 127 | }; |
| 128 | #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) |
| 129 | #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) |
| 130 | struct drm_tegra_gem_set_flags { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 131 | __u32 handle; |
| 132 | __u32 flags; |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 133 | }; |
| 134 | struct drm_tegra_gem_get_flags { |
Tao Bao | d7db594 | 2015-01-28 10:07:51 -0800 | [diff] [blame] | 135 | __u32 handle; |
| 136 | __u32 flags; |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 137 | }; |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 138 | #define DRM_TEGRA_GEM_CREATE 0x00 |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 139 | #define DRM_TEGRA_GEM_MMAP 0x01 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 140 | #define DRM_TEGRA_SYNCPT_READ 0x02 |
| 141 | #define DRM_TEGRA_SYNCPT_INCR 0x03 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 142 | #define DRM_TEGRA_SYNCPT_WAIT 0x04 |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 143 | #define DRM_TEGRA_OPEN_CHANNEL 0x05 |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 144 | #define DRM_TEGRA_CLOSE_CHANNEL 0x06 |
| 145 | #define DRM_TEGRA_GET_SYNCPT 0x07 |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 146 | #define DRM_TEGRA_SUBMIT 0x08 |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 147 | #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 |
| 148 | #define DRM_TEGRA_GEM_SET_TILING 0x0a |
| 149 | #define DRM_TEGRA_GEM_GET_TILING 0x0b |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 150 | #define DRM_TEGRA_GEM_SET_FLAGS 0x0c |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 151 | #define DRM_TEGRA_GEM_GET_FLAGS 0x0d |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 152 | #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) |
| 153 | #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 154 | #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 155 | #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 156 | #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) |
| 157 | #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) |
Christopher Ferris | 9ce2884 | 2018-10-25 12:11:39 -0700 | [diff] [blame] | 158 | #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_close_channel) |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 159 | #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) |
Ben Cheng | 655a7c0 | 2013-10-16 16:09:24 -0700 | [diff] [blame] | 160 | #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) |
Christopher Ferris | 38062f9 | 2014-07-09 15:33:25 -0700 | [diff] [blame] | 161 | #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 162 | #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) |
Christopher Ferris | 82d7504 | 2015-01-26 10:57:07 -0800 | [diff] [blame] | 163 | #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) |
| 164 | #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) |
| 165 | #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 166 | #ifdef __cplusplus |
Christopher Ferris | 48fe0ae | 2019-01-10 15:59:33 -0800 | [diff] [blame] | 167 | } |
Christopher Ferris | 106b3a8 | 2016-08-24 12:15:38 -0700 | [diff] [blame] | 168 | #endif |
Christopher Ferris | 05d08e9 | 2016-02-04 13:16:38 -0800 | [diff] [blame] | 169 | #endif |