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gerrit.omnirom.org / android_bionic / 106b3a8a7dc03c19a45e322de425ac56aafac358 / . / libc / kernel / uapi / drm / tegra_drm.h
blob: 2d85a146a1efd0ea111507eb21773cd283246491 [file] [log] [blame]
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]1/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef _UAPI_TEGRA_DRM_H_
20#define _UAPI_TEGRA_DRM_H_
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]21#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]23/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]24#endif
25#define DRM_TEGRA_GEM_CREATE_TILED (1 << 0)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]26#define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1)
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]27struct drm_tegra_gem_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]28/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]29 __u64 size;
30 __u32 flags;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]31 __u32 handle;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]32};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]33/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]34struct drm_tegra_gem_mmap {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]35 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]36 __u32 pad;
37 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]38/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]39};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]40struct drm_tegra_syncpt_read {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]41 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]42 __u32 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]43/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]44};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]45struct drm_tegra_syncpt_incr {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]46 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]47 __u32 pad;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]48/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]49};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]50struct drm_tegra_syncpt_wait {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]51 __u32 id;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]52 __u32 thresh;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]53/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]54 __u32 timeout;
55 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]56};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]57#define DRM_TEGRA_NO_TIMEOUT (0xffffffff)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]58/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]59struct drm_tegra_open_channel {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]60 __u32 client;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]61 __u32 pad;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]62 __u64 context;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]63/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]64};
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]65struct drm_tegra_close_channel {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]66 __u64 context;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]67};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]68/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]69struct drm_tegra_get_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]70 __u64 context;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]71 __u32 index;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]72 __u32 id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]73/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]74};
75struct drm_tegra_get_syncpt_base {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]76 __u64 context;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]77 __u32 syncpt;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]78/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]79 __u32 id;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]80};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]81struct drm_tegra_syncpt {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]82 __u32 id;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]83/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]84 __u32 incrs;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]85};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]86struct drm_tegra_cmdbuf {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]87 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]88/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]89 __u32 offset;
90 __u32 words;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]91 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]92};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]93/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]94struct drm_tegra_reloc {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]95 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]96 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]97 __u32 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]98/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]99 } cmdbuf;
100 struct {
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]101 __u32 handle;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]102 __u32 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]103/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]104 } target;
105 __u32 shift;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]106 __u32 pad;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]107};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]108/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]109struct drm_tegra_waitchk {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]110 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]111 __u32 offset;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]112 __u32 syncpt;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]113/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]114 __u32 thresh;
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]115};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]116struct drm_tegra_submit {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]117 __u64 context;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]118/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]119 __u32 num_syncpts;
120 __u32 num_cmdbufs;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]121 __u32 num_relocs;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]122 __u32 num_waitchks;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]123/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]124 __u32 waitchk_mask;
125 __u32 timeout;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]126 __u64 syncpts;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]127 __u64 cmdbufs;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]128/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]129 __u64 relocs;
130 __u64 waitchks;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]131 __u32 fence;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]132 __u32 reserved[5];
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]133/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]134};
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]135#define DRM_TEGRA_GEM_TILING_MODE_PITCH 0
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]136#define DRM_TEGRA_GEM_TILING_MODE_TILED 1
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]137#define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]138/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]139struct drm_tegra_gem_set_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]140 __u32 handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]141 __u32 mode;
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]142 __u32 value;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]143/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]144 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]145};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]146struct drm_tegra_gem_get_tiling {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]147 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]148/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]149 __u32 mode;
150 __u32 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]151 __u32 pad;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]152};
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]153/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]154#define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0)
155#define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP)
156struct drm_tegra_gem_set_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]157 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]158/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]159 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]160};
161struct drm_tegra_gem_get_flags {
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]162 __u32 handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]163/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Tao Baod7db5942015-01-28 10:07:51 -0800[diff] [blame]164 __u32 flags;
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]165};
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]166#define DRM_TEGRA_GEM_CREATE 0x00
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]167#define DRM_TEGRA_GEM_MMAP 0x01
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]168/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]169#define DRM_TEGRA_SYNCPT_READ 0x02
170#define DRM_TEGRA_SYNCPT_INCR 0x03
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]171#define DRM_TEGRA_SYNCPT_WAIT 0x04
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]172#define DRM_TEGRA_OPEN_CHANNEL 0x05
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]173/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]174#define DRM_TEGRA_CLOSE_CHANNEL 0x06
175#define DRM_TEGRA_GET_SYNCPT 0x07
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]176#define DRM_TEGRA_SUBMIT 0x08
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]177#define DRM_TEGRA_GET_SYNCPT_BASE 0x09
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]178/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]179#define DRM_TEGRA_GEM_SET_TILING 0x0a
180#define DRM_TEGRA_GEM_GET_TILING 0x0b
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]181#define DRM_TEGRA_GEM_SET_FLAGS 0x0c
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]182#define DRM_TEGRA_GEM_GET_FLAGS 0x0d
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]183/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]184#define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create)
185#define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]186#define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]187#define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]188/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]189#define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait)
190#define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]191#define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]192#define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]193/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Ben Cheng655a7c02013-10-16 16:09:24 -0700[diff] [blame]194#define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit)
Christopher Ferris38062f92014-07-09 15:33:25 -0700[diff] [blame]195#define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]196#define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling)
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]197#define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]198/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]199#define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags)
200#define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700[diff] [blame^]201#ifdef __cplusplus
202#endif
Christopher Ferris82d75042015-01-26 10:57:07 -0800[diff] [blame]203/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
Christopher Ferris05d08e92016-02-04 13:16:38 -0800[diff] [blame]204#endif