blob: 342282daa879a257a26916c30fedc538e10dded3 [file] [log] [blame]
Christopher Ferris05d08e92016-02-04 13:16:38 -08001/****************************************************************************
2 ****************************************************************************
3 ***
4 *** This header was automatically generated from a Linux kernel header
5 *** of the same name, to make information necessary for userspace to
6 *** call into the kernel available to libc. It contains only constants,
7 *** structures, and macros generated from the original header, and thus,
8 *** contains no copyrightable information.
9 ***
10 *** To edit the content of this header, modify the corresponding
11 *** source file (e.g. under external/kernel-headers/original/) then
12 *** run bionic/libc/kernel/tools/update_all.py
13 ***
14 *** Any manual change here will be lost the next time this script will
15 *** be run. You've been warned!
16 ***
17 ****************************************************************************
18 ****************************************************************************/
19#ifndef VIRTGPU_DRM_H
20#define VIRTGPU_DRM_H
Christopher Ferris106b3a82016-08-24 12:15:38 -070021#include "drm.h"
22#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -080023extern "C" {
Christopher Ferris106b3a82016-08-24 12:15:38 -070024#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -080025#define DRM_VIRTGPU_MAP 0x01
26#define DRM_VIRTGPU_EXECBUFFER 0x02
27#define DRM_VIRTGPU_GETPARAM 0x03
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
Christopher Ferris05d08e92016-02-04 13:16:38 -080029#define DRM_VIRTGPU_RESOURCE_INFO 0x05
30#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
31#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
Christopher Ferris106b3a82016-08-24 12:15:38 -070032#define DRM_VIRTGPU_WAIT 0x08
Christopher Ferris05d08e92016-02-04 13:16:38 -080033#define DRM_VIRTGPU_GET_CAPS 0x09
Christopher Ferris05667cd2021-02-16 16:01:34 -080034#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
Christopher Ferrisa4792612022-01-10 13:51:15 -080035#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
Christopher Ferrisd842e432019-03-07 10:21:59 -080036#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
37#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
Christopher Ferrisa4792612022-01-10 13:51:15 -080038#define VIRTGPU_EXECBUF_RING_IDX 0x04
39#define VIRTGPU_EXECBUF_FLAGS (VIRTGPU_EXECBUF_FENCE_FD_IN | VIRTGPU_EXECBUF_FENCE_FD_OUT | VIRTGPU_EXECBUF_RING_IDX | 0)
Christopher Ferris05d08e92016-02-04 13:16:38 -080040struct drm_virtgpu_map {
Christopher Ferris106b3a82016-08-24 12:15:38 -070041 __u64 offset;
Christopher Ferris106b3a82016-08-24 12:15:38 -070042 __u32 handle;
43 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -080044};
45struct drm_virtgpu_execbuffer {
Christopher Ferris106b3a82016-08-24 12:15:38 -070046 __u32 flags;
47 __u32 size;
48 __u64 command;
49 __u64 bo_handles;
Christopher Ferris106b3a82016-08-24 12:15:38 -070050 __u32 num_bo_handles;
Christopher Ferrisd842e432019-03-07 10:21:59 -080051 __s32 fence_fd;
Christopher Ferrisa4792612022-01-10 13:51:15 -080052 __u32 ring_idx;
53 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -080054};
55#define VIRTGPU_PARAM_3D_FEATURES 1
Christopher Ferris76a1d452018-06-27 14:12:29 -070056#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2
Christopher Ferris05667cd2021-02-16 16:01:34 -080057#define VIRTGPU_PARAM_RESOURCE_BLOB 3
58#define VIRTGPU_PARAM_HOST_VISIBLE 4
59#define VIRTGPU_PARAM_CROSS_DEVICE 5
Christopher Ferrisa4792612022-01-10 13:51:15 -080060#define VIRTGPU_PARAM_CONTEXT_INIT 6
61#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7
Christopher Ferris05d08e92016-02-04 13:16:38 -080062struct drm_virtgpu_getparam {
Christopher Ferris106b3a82016-08-24 12:15:38 -070063 __u64 param;
64 __u64 value;
Christopher Ferris05d08e92016-02-04 13:16:38 -080065};
66struct drm_virtgpu_resource_create {
Christopher Ferris106b3a82016-08-24 12:15:38 -070067 __u32 target;
68 __u32 format;
69 __u32 bind;
Christopher Ferris106b3a82016-08-24 12:15:38 -070070 __u32 width;
71 __u32 height;
72 __u32 depth;
73 __u32 array_size;
Christopher Ferris106b3a82016-08-24 12:15:38 -070074 __u32 last_level;
75 __u32 nr_samples;
76 __u32 flags;
77 __u32 bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070078 __u32 res_handle;
79 __u32 size;
80 __u32 stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -080081};
82struct drm_virtgpu_resource_info {
Christopher Ferris106b3a82016-08-24 12:15:38 -070083 __u32 bo_handle;
84 __u32 res_handle;
85 __u32 size;
Christopher Ferris05667cd2021-02-16 16:01:34 -080086 __u32 blob_mem;
Christopher Ferris05d08e92016-02-04 13:16:38 -080087};
88struct drm_virtgpu_3d_box {
Christopher Ferris106b3a82016-08-24 12:15:38 -070089 __u32 x;
Christopher Ferris106b3a82016-08-24 12:15:38 -070090 __u32 y;
91 __u32 z;
92 __u32 w;
93 __u32 h;
Christopher Ferris106b3a82016-08-24 12:15:38 -070094 __u32 d;
Christopher Ferris05d08e92016-02-04 13:16:38 -080095};
96struct drm_virtgpu_3d_transfer_to_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -070097 __u32 bo_handle;
Christopher Ferris106b3a82016-08-24 12:15:38 -070098 struct drm_virtgpu_3d_box box;
99 __u32 level;
100 __u32 offset;
Christopher Ferris05667cd2021-02-16 16:01:34 -0800101 __u32 stride;
102 __u32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800103};
104struct drm_virtgpu_3d_transfer_from_host {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700105 __u32 bo_handle;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800106 struct drm_virtgpu_3d_box box;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700107 __u32 level;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700108 __u32 offset;
Christopher Ferris05667cd2021-02-16 16:01:34 -0800109 __u32 stride;
110 __u32 layer_stride;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800111};
112#define VIRTGPU_WAIT_NOWAIT 1
113struct drm_virtgpu_3d_wait {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700114 __u32 handle;
115 __u32 flags;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800116};
117struct drm_virtgpu_get_caps {
Christopher Ferris106b3a82016-08-24 12:15:38 -0700118 __u32 cap_set_id;
119 __u32 cap_set_ver;
120 __u64 addr;
121 __u32 size;
Christopher Ferris106b3a82016-08-24 12:15:38 -0700122 __u32 pad;
Christopher Ferris05d08e92016-02-04 13:16:38 -0800123};
Christopher Ferris05667cd2021-02-16 16:01:34 -0800124struct drm_virtgpu_resource_create_blob {
125#define VIRTGPU_BLOB_MEM_GUEST 0x0001
126#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
127#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
128#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
129#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
130#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
131 __u32 blob_mem;
132 __u32 blob_flags;
133 __u32 bo_handle;
134 __u32 res_handle;
135 __u64 size;
136 __u32 pad;
137 __u32 cmd_size;
138 __u64 cmd;
139 __u64 blob_id;
140};
Christopher Ferrisa4792612022-01-10 13:51:15 -0800141#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
142#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
143#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
144struct drm_virtgpu_context_set_param {
145 __u64 param;
146 __u64 value;
147};
148struct drm_virtgpu_context_init {
149 __u32 num_params;
150 __u32 pad;
151 __u64 ctx_set_params;
152};
153#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
Christopher Ferris05d08e92016-02-04 13:16:38 -0800154#define DRM_IOCTL_VIRTGPU_MAP DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
Christopher Ferrisd842e432019-03-07 10:21:59 -0800155#define DRM_IOCTL_VIRTGPU_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER, struct drm_virtgpu_execbuffer)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700156#define DRM_IOCTL_VIRTGPU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM, struct drm_virtgpu_getparam)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800157#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, struct drm_virtgpu_resource_create)
158#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, struct drm_virtgpu_resource_info)
159#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, struct drm_virtgpu_3d_transfer_from_host)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700160#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, struct drm_virtgpu_3d_transfer_to_host)
Christopher Ferris05d08e92016-02-04 13:16:38 -0800161#define DRM_IOCTL_VIRTGPU_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, struct drm_virtgpu_3d_wait)
162#define DRM_IOCTL_VIRTGPU_GET_CAPS DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, struct drm_virtgpu_get_caps)
Christopher Ferris05667cd2021-02-16 16:01:34 -0800163#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, struct drm_virtgpu_resource_create_blob)
Christopher Ferrisa4792612022-01-10 13:51:15 -0800164#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, struct drm_virtgpu_context_init)
Christopher Ferris106b3a82016-08-24 12:15:38 -0700165#ifdef __cplusplus
Christopher Ferris48fe0ae2019-01-10 15:59:33 -0800166}
Christopher Ferris106b3a82016-08-24 12:15:38 -0700167#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800168#endif