blob: 4541a66f2bc1abf73c05b20e0d624af6bd71dbae [file] [log] [blame]
Elliott Hughes180edef2023-11-02 00:08:05 +00001/*
2 * This file is auto-generated. Modifications will be lost.
3 *
4 * See https://android.googlesource.com/platform/bionic/+/master/libc/kernel/
5 * for more information.
6 */
Ben Cheng655a7c02013-10-16 16:09:24 -07007#ifndef _UAPI__ASM_PTRACE_H
8#define _UAPI__ASM_PTRACE_H
9#include <linux/types.h>
10#include <asm/hwcap.h>
Christopher Ferrisd842e432019-03-07 10:21:59 -080011#include <asm/sve_context.h>
Ben Cheng655a7c02013-10-16 16:09:24 -070012#define PSR_MODE_EL0t 0x00000000
13#define PSR_MODE_EL1t 0x00000004
14#define PSR_MODE_EL1h 0x00000005
15#define PSR_MODE_EL2t 0x00000008
Ben Cheng655a7c02013-10-16 16:09:24 -070016#define PSR_MODE_EL2h 0x00000009
17#define PSR_MODE_EL3t 0x0000000c
18#define PSR_MODE_EL3h 0x0000000d
19#define PSR_MODE_MASK 0x0000000f
Ben Cheng655a7c02013-10-16 16:09:24 -070020#define PSR_MODE32_BIT 0x00000010
21#define PSR_F_BIT 0x00000040
22#define PSR_I_BIT 0x00000080
23#define PSR_A_BIT 0x00000100
Ben Cheng655a7c02013-10-16 16:09:24 -070024#define PSR_D_BIT 0x00000200
Christopher Ferris8177cdf2020-08-03 11:53:55 -070025#define PSR_BTYPE_MASK 0x00000c00
Christopher Ferris86a48372019-01-10 14:14:59 -080026#define PSR_SSBS_BIT 0x00001000
Christopher Ferris05d08e92016-02-04 13:16:38 -080027#define PSR_PAN_BIT 0x00400000
Christopher Ferris106b3a82016-08-24 12:15:38 -070028#define PSR_UAO_BIT 0x00800000
Christopher Ferrisbb9fcb42020-04-06 11:38:04 -070029#define PSR_DIT_BIT 0x01000000
Christopher Ferris32ff3f82020-12-14 13:10:04 -080030#define PSR_TCO_BIT 0x02000000
Christopher Ferris106b3a82016-08-24 12:15:38 -070031#define PSR_V_BIT 0x10000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080032#define PSR_C_BIT 0x20000000
Ben Cheng655a7c02013-10-16 16:09:24 -070033#define PSR_Z_BIT 0x40000000
34#define PSR_N_BIT 0x80000000
Christopher Ferris8177cdf2020-08-03 11:53:55 -070035#define PSR_BTYPE_SHIFT 10
Christopher Ferris106b3a82016-08-24 12:15:38 -070036#define PSR_f 0xff000000
Christopher Ferris05d08e92016-02-04 13:16:38 -080037#define PSR_s 0x00ff0000
Ben Cheng655a7c02013-10-16 16:09:24 -070038#define PSR_x 0x0000ff00
39#define PSR_c 0x000000ff
Christopher Ferris8177cdf2020-08-03 11:53:55 -070040#define PSR_BTYPE_NONE (0b00 << PSR_BTYPE_SHIFT)
41#define PSR_BTYPE_JC (0b01 << PSR_BTYPE_SHIFT)
42#define PSR_BTYPE_C (0b10 << PSR_BTYPE_SHIFT)
43#define PSR_BTYPE_J (0b11 << PSR_BTYPE_SHIFT)
Christopher Ferrisb8a95e22019-10-02 18:29:20 -070044#define PTRACE_SYSEMU 31
45#define PTRACE_SYSEMU_SINGLESTEP 32
Christopher Ferris32ff3f82020-12-14 13:10:04 -080046#define PTRACE_PEEKMTETAGS 33
47#define PTRACE_POKEMTETAGS 34
Christopher Ferris106b3a82016-08-24 12:15:38 -070048#ifndef __ASSEMBLY__
Christopher Ferris05d08e92016-02-04 13:16:38 -080049struct user_pt_regs {
Tao Baod7db5942015-01-28 10:07:51 -080050 __u64 regs[31];
51 __u64 sp;
Christopher Ferris106b3a82016-08-24 12:15:38 -070052 __u64 pc;
Christopher Ferris05d08e92016-02-04 13:16:38 -080053 __u64 pstate;
Ben Cheng655a7c02013-10-16 16:09:24 -070054};
55struct user_fpsimd_state {
Christopher Ferris106b3a82016-08-24 12:15:38 -070056 __uint128_t vregs[32];
Christopher Ferris05d08e92016-02-04 13:16:38 -080057 __u32 fpsr;
Tao Baod7db5942015-01-28 10:07:51 -080058 __u32 fpcr;
Christopher Ferris351a7962017-01-27 10:49:48 -080059 __u32 __reserved[2];
Christopher Ferris351a7962017-01-27 10:49:48 -080060};
Christopher Ferris106b3a82016-08-24 12:15:38 -070061struct user_hwdebug_state {
Christopher Ferris05d08e92016-02-04 13:16:38 -080062 __u32 dbg_info;
Tao Baod7db5942015-01-28 10:07:51 -080063 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080064 struct {
Christopher Ferris106b3a82016-08-24 12:15:38 -070065 __u64 addr;
Christopher Ferris05d08e92016-02-04 13:16:38 -080066 __u32 ctrl;
Tao Baod7db5942015-01-28 10:07:51 -080067 __u32 pad;
Christopher Ferris351a7962017-01-27 10:49:48 -080068 } dbg_regs[16];
Christopher Ferris106b3a82016-08-24 12:15:38 -070069};
Christopher Ferris934ec942018-01-31 15:29:16 -080070struct user_sve_header {
71 __u32 size;
72 __u32 max_size;
73 __u16 vl;
74 __u16 max_vl;
75 __u16 flags;
76 __u16 __reserved;
77};
78#define SVE_PT_REGS_MASK (1 << 0)
79#define SVE_PT_REGS_FPSIMD 0
80#define SVE_PT_REGS_SVE SVE_PT_REGS_MASK
Christopher Ferrisaeddbcf2019-07-08 12:45:46 -070081#define SVE_PT_VL_INHERIT ((1 << 17) >> 16)
82#define SVE_PT_VL_ONEXEC ((1 << 18) >> 16)
Christopher Ferrisd842e432019-03-07 10:21:59 -080083#define SVE_PT_REGS_OFFSET ((sizeof(struct user_sve_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris934ec942018-01-31 15:29:16 -080084#define SVE_PT_FPSIMD_OFFSET SVE_PT_REGS_OFFSET
85#define SVE_PT_FPSIMD_SIZE(vq,flags) (sizeof(struct user_fpsimd_state))
Christopher Ferrisd842e432019-03-07 10:21:59 -080086#define SVE_PT_SVE_ZREG_SIZE(vq) __SVE_ZREG_SIZE(vq)
87#define SVE_PT_SVE_PREG_SIZE(vq) __SVE_PREG_SIZE(vq)
88#define SVE_PT_SVE_FFR_SIZE(vq) __SVE_FFR_SIZE(vq)
Christopher Ferris934ec942018-01-31 15:29:16 -080089#define SVE_PT_SVE_FPSR_SIZE sizeof(__u32)
90#define SVE_PT_SVE_FPCR_SIZE sizeof(__u32)
Christopher Ferris934ec942018-01-31 15:29:16 -080091#define SVE_PT_SVE_OFFSET SVE_PT_REGS_OFFSET
Christopher Ferrisd842e432019-03-07 10:21:59 -080092#define SVE_PT_SVE_ZREGS_OFFSET (SVE_PT_REGS_OFFSET + __SVE_ZREGS_OFFSET)
93#define SVE_PT_SVE_ZREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_ZREG_OFFSET(vq, n))
94#define SVE_PT_SVE_ZREGS_SIZE(vq) (SVE_PT_SVE_ZREG_OFFSET(vq, __SVE_NUM_ZREGS) - SVE_PT_SVE_ZREGS_OFFSET)
95#define SVE_PT_SVE_PREGS_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_PREGS_OFFSET(vq))
96#define SVE_PT_SVE_PREG_OFFSET(vq,n) (SVE_PT_REGS_OFFSET + __SVE_PREG_OFFSET(vq, n))
97#define SVE_PT_SVE_PREGS_SIZE(vq) (SVE_PT_SVE_PREG_OFFSET(vq, __SVE_NUM_PREGS) - SVE_PT_SVE_PREGS_OFFSET(vq))
98#define SVE_PT_SVE_FFR_OFFSET(vq) (SVE_PT_REGS_OFFSET + __SVE_FFR_OFFSET(vq))
99#define SVE_PT_SVE_FPSR_OFFSET(vq) ((SVE_PT_SVE_FFR_OFFSET(vq) + SVE_PT_SVE_FFR_SIZE(vq) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris934ec942018-01-31 15:29:16 -0800100#define SVE_PT_SVE_FPCR_OFFSET(vq) (SVE_PT_SVE_FPSR_OFFSET(vq) + SVE_PT_SVE_FPSR_SIZE)
Christopher Ferrisd842e432019-03-07 10:21:59 -0800101#define SVE_PT_SVE_SIZE(vq,flags) ((SVE_PT_SVE_FPCR_OFFSET(vq) + SVE_PT_SVE_FPCR_SIZE - SVE_PT_SVE_OFFSET + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700102#define SVE_PT_SIZE(vq,flags) (((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_SVE ? SVE_PT_SVE_OFFSET + SVE_PT_SVE_SIZE(vq, flags) : ((((flags) & SVE_PT_REGS_MASK) == SVE_PT_REGS_FPSIMD ? SVE_PT_FPSIMD_OFFSET + SVE_PT_FPSIMD_SIZE(vq, flags) : SVE_PT_REGS_OFFSET)))
Christopher Ferrisd842e432019-03-07 10:21:59 -0800103struct user_pac_mask {
104 __u64 data_mask;
105 __u64 insn_mask;
106};
Christopher Ferris24f97eb2019-05-20 12:58:13 -0700107struct user_pac_address_keys {
108 __uint128_t apiakey;
109 __uint128_t apibkey;
110 __uint128_t apdakey;
111 __uint128_t apdbkey;
112};
113struct user_pac_generic_keys {
114 __uint128_t apgakey;
115};
Christopher Ferris80ae69d2022-08-02 16:32:21 -0700116struct user_za_header {
117 __u32 size;
118 __u32 max_size;
119 __u16 vl;
120 __u16 max_vl;
121 __u16 flags;
122 __u16 __reserved;
123};
124#define ZA_PT_VL_INHERIT ((1 << 17) >> 16)
125#define ZA_PT_VL_ONEXEC ((1 << 18) >> 16)
126#define ZA_PT_ZA_OFFSET ((sizeof(struct user_za_header) + (__SVE_VQ_BYTES - 1)) / __SVE_VQ_BYTES * __SVE_VQ_BYTES)
127#define ZA_PT_ZAV_OFFSET(vq,n) (ZA_PT_ZA_OFFSET + ((vq * __SVE_VQ_BYTES) * n))
128#define ZA_PT_ZA_SIZE(vq) ((vq * __SVE_VQ_BYTES) * (vq * __SVE_VQ_BYTES))
129#define ZA_PT_SIZE(vq) (ZA_PT_ZA_OFFSET + ZA_PT_ZA_SIZE(vq))
Ben Cheng655a7c02013-10-16 16:09:24 -0700130#endif
Christopher Ferris05d08e92016-02-04 13:16:38 -0800131#endif